1c02697cbSDavid Zhang /* SPDX-License-Identifier: GPL-2.0 */ 2c02697cbSDavid Zhang /* 3c02697cbSDavid Zhang * Copyright (C) 2026, Advanced Micro Devices, Inc. 4c02697cbSDavid Zhang */ 5c02697cbSDavid Zhang 6c02697cbSDavid Zhang #ifndef _AIE4_PCI_H_ 7c02697cbSDavid Zhang #define _AIE4_PCI_H_ 8c02697cbSDavid Zhang 9c02697cbSDavid Zhang #include <linux/device.h> 10c02697cbSDavid Zhang #include <linux/iopoll.h> 11c02697cbSDavid Zhang #include <linux/pci.h> 12c02697cbSDavid Zhang 13c02697cbSDavid Zhang #include "aie.h" 14c02697cbSDavid Zhang #include "amdxdna_mailbox.h" 15c02697cbSDavid Zhang 1619361279SDavid Zhang struct cert_comp { 1719361279SDavid Zhang struct amdxdna_dev_hdl *ndev; 1819361279SDavid Zhang u32 msix_idx; 1919361279SDavid Zhang int irq; 2019361279SDavid Zhang struct kref kref; 2119361279SDavid Zhang wait_queue_head_t waitq; 2219361279SDavid Zhang }; 2319361279SDavid Zhang 2419361279SDavid Zhang struct amdxdna_hwctx_priv { 2519361279SDavid Zhang struct amdxdna_gem_obj *umq_bo; 2619361279SDavid Zhang u64 *umq_read_index; 2719361279SDavid Zhang u64 *umq_write_index; 2819361279SDavid Zhang 2919361279SDavid Zhang struct cert_comp *cert_comp; 3019361279SDavid Zhang u32 hw_ctx_id; 3119361279SDavid Zhang }; 3219361279SDavid Zhang 33c02697cbSDavid Zhang struct amdxdna_dev_priv { 34e69ef214SDavid Zhang const char *npufw_path; 35e69ef214SDavid Zhang const char *certfw_path; 36c02697cbSDavid Zhang u32 mbox_bar; 37c02697cbSDavid Zhang u32 mbox_rbuf_bar; 38c02697cbSDavid Zhang u64 mbox_info_off; 3991f4da82SDavid Zhang u32 doorbell_off; 40e69ef214SDavid Zhang 41e69ef214SDavid Zhang struct aie_bar_off_pair psp_regs_off[PSP_MAX_REGS]; 4243c9a66eSDavid Zhang struct aie_bar_off_pair smu_regs_off[SMU_MAX_REGS]; 43c02697cbSDavid Zhang }; 44c02697cbSDavid Zhang 45c02697cbSDavid Zhang struct amdxdna_dev_hdl { 46c02697cbSDavid Zhang struct aie_device aie; 47c02697cbSDavid Zhang const struct amdxdna_dev_priv *priv; 48c02697cbSDavid Zhang void __iomem *mbox_base; 49c02697cbSDavid Zhang void __iomem *rbuf_base; 50c02697cbSDavid Zhang 51c02697cbSDavid Zhang struct mailbox *mbox; 52ce9414d0SDavid Zhang u32 partition_id; 5319361279SDavid Zhang 5419361279SDavid Zhang struct xarray cert_comp_xa; /* device level indexed by msix id */ 5519361279SDavid Zhang struct mutex cert_comp_lock; /* protects cert_comp operations*/ 56*c0069781SNishad Saraf 57*c0069781SNishad Saraf void *work_buf; 58*c0069781SNishad Saraf dma_addr_t work_buf_addr; 59*c0069781SNishad Saraf u32 work_buf_size; 60c02697cbSDavid Zhang }; 61c02697cbSDavid Zhang 62c02697cbSDavid Zhang /* aie4_message.c */ 630b087e06SDavid Zhang int aie4_query_aie_metadata(struct amdxdna_dev_hdl *ndev, 640b087e06SDavid Zhang struct amdxdna_drm_query_aie_metadata *metadata); 65c02697cbSDavid Zhang int aie4_suspend_fw(struct amdxdna_dev_hdl *ndev); 66*c0069781SNishad Saraf int aie4_attach_work_buffer(struct amdxdna_dev_hdl *ndev); 67c02697cbSDavid Zhang 6819361279SDavid Zhang /* aie4_ctx.c */ 6919361279SDavid Zhang int aie4_hwctx_init(struct amdxdna_hwctx *hwctx); 7019361279SDavid Zhang void aie4_hwctx_fini(struct amdxdna_hwctx *hwctx); 7191f4da82SDavid Zhang int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout); 7291f4da82SDavid Zhang int aie4_hwctx_valid_doorbell(struct amdxdna_client *client, u32 vm_pgoff); 7319361279SDavid Zhang 74c02697cbSDavid Zhang /* aie4_sriov.c */ 75c02697cbSDavid Zhang #if IS_ENABLED(CONFIG_PCI_IOV) 76c02697cbSDavid Zhang int aie4_sriov_configure(struct amdxdna_dev *xdna, int num_vfs); 77c02697cbSDavid Zhang int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev); 78c02697cbSDavid Zhang #else 79c02697cbSDavid Zhang #define aie4_sriov_configure NULL 80c02697cbSDavid Zhang static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev) 81c02697cbSDavid Zhang { 82c02697cbSDavid Zhang return 0; 83c02697cbSDavid Zhang } 84c02697cbSDavid Zhang #endif 85c02697cbSDavid Zhang 867b1a245bSDavid Zhang extern const struct amdxdna_dev_ops aie4_pf_ops; 877b1a245bSDavid Zhang extern const struct amdxdna_dev_ops aie4_vf_ops; 88c02697cbSDavid Zhang 89c02697cbSDavid Zhang #endif /* _AIE4_PCI_H_ */ 90