1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/drm_device.h> 7 #include <drm/drm_gem_shmem_helper.h> 8 #include <drm/drm_managed.h> 9 #include <drm/drm_print.h> 10 #include <drm/gpu_scheduler.h> 11 #include <linux/bitfield.h> 12 #include <linux/iopoll.h> 13 14 #include "aie2_pci.h" 15 #include "amdxdna_mailbox.h" 16 #include "amdxdna_pci_drv.h" 17 18 #define PSP_STATUS_READY BIT(31) 19 20 /* PSP commands */ 21 #define PSP_VALIDATE 1 22 #define PSP_START 2 23 #define PSP_RELEASE_TMR 3 24 25 /* PSP special arguments */ 26 #define PSP_START_COPY_FW 1 27 28 /* PSP response error code */ 29 #define PSP_ERROR_CANCEL 0xFFFF0002 30 #define PSP_ERROR_BAD_STATE 0xFFFF0007 31 32 #define PSP_FW_ALIGN 0x10000 33 #define PSP_POLL_INTERVAL 20000 /* us */ 34 #define PSP_POLL_TIMEOUT 1000000 /* us */ 35 36 #define PSP_REG(p, reg) ((p)->psp_regs[reg]) 37 38 struct psp_device { 39 struct drm_device *ddev; 40 struct psp_config conf; 41 u32 fw_buf_sz; 42 u64 fw_paddr; 43 void *fw_buffer; 44 void __iomem *psp_regs[PSP_MAX_REGS]; 45 }; 46 47 static int psp_exec(struct psp_device *psp, u32 *reg_vals) 48 { 49 u32 resp_code; 50 int ret, i; 51 u32 ready; 52 53 /* Write command and argument registers */ 54 for (i = 0; i < PSP_NUM_IN_REGS; i++) 55 writel(reg_vals[i], PSP_REG(psp, i)); 56 57 /* clear and set PSP INTR register to kick off */ 58 writel(0, PSP_REG(psp, PSP_INTR_REG)); 59 writel(1, PSP_REG(psp, PSP_INTR_REG)); 60 61 /* PSP should be busy. Wait for ready, so we know task is done. */ 62 ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_STATUS_REG), ready, 63 FIELD_GET(PSP_STATUS_READY, ready), 64 PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); 65 if (ret) { 66 drm_err(psp->ddev, "PSP is not ready, ret 0x%x", ret); 67 return ret; 68 } 69 70 resp_code = readl(PSP_REG(psp, PSP_RESP_REG)); 71 if (resp_code) { 72 drm_err(psp->ddev, "fw return error 0x%x", resp_code); 73 return -EIO; 74 } 75 76 return 0; 77 } 78 79 int aie2_psp_waitmode_poll(struct psp_device *psp) 80 { 81 struct amdxdna_dev *xdna = to_xdna_dev(psp->ddev); 82 u32 mode_reg; 83 int ret; 84 85 ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_PWAITMODE_REG), mode_reg, 86 (mode_reg & 0x1) == 1, 87 PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); 88 if (ret) 89 XDNA_ERR(xdna, "fw waitmode reg error, ret %d", ret); 90 91 return ret; 92 } 93 94 void aie2_psp_stop(struct psp_device *psp) 95 { 96 u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, }; 97 int ret; 98 99 ret = psp_exec(psp, reg_vals); 100 if (ret) 101 drm_err(psp->ddev, "release tmr failed, ret %d", ret); 102 } 103 104 int aie2_psp_start(struct psp_device *psp) 105 { 106 u32 reg_vals[PSP_NUM_IN_REGS]; 107 int ret; 108 109 reg_vals[0] = PSP_VALIDATE; 110 reg_vals[1] = lower_32_bits(psp->fw_paddr); 111 reg_vals[2] = upper_32_bits(psp->fw_paddr); 112 reg_vals[3] = psp->fw_buf_sz; 113 114 ret = psp_exec(psp, reg_vals); 115 if (ret) { 116 drm_err(psp->ddev, "failed to validate fw, ret %d", ret); 117 return ret; 118 } 119 120 memset(reg_vals, 0, sizeof(reg_vals)); 121 reg_vals[0] = PSP_START; 122 reg_vals[1] = PSP_START_COPY_FW; 123 ret = psp_exec(psp, reg_vals); 124 if (ret) { 125 drm_err(psp->ddev, "failed to start fw, ret %d", ret); 126 return ret; 127 } 128 129 return 0; 130 } 131 132 struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf) 133 { 134 struct psp_device *psp; 135 u64 offset; 136 137 psp = drmm_kzalloc(ddev, sizeof(*psp), GFP_KERNEL); 138 if (!psp) 139 return NULL; 140 141 psp->ddev = ddev; 142 memcpy(psp->psp_regs, conf->psp_regs, sizeof(psp->psp_regs)); 143 144 psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN); 145 psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz + PSP_FW_ALIGN, GFP_KERNEL); 146 if (!psp->fw_buffer) { 147 drm_err(ddev, "no memory for fw buffer"); 148 return NULL; 149 } 150 151 /* 152 * AMD Platform Security Processor(PSP) requires host physical 153 * address to load NPU firmware. 154 */ 155 psp->fw_paddr = virt_to_phys(psp->fw_buffer); 156 offset = ALIGN(psp->fw_paddr, PSP_FW_ALIGN) - psp->fw_paddr; 157 psp->fw_paddr += offset; 158 memcpy(psp->fw_buffer + offset, conf->fw_buf, conf->fw_size); 159 160 return psp; 161 } 162