1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/mem_encrypt.h> 22 #include <linux/smp.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/pgtable.h> 27 #include <linux/stackprotector.h> 28 #include <linux/utsname.h> 29 30 #include <asm/alternative.h> 31 #include <asm/cmdline.h> 32 #include <asm/cpuid/api.h> 33 #include <asm/perf_event.h> 34 #include <asm/mmu_context.h> 35 #include <asm/doublefault.h> 36 #include <asm/archrandom.h> 37 #include <asm/hypervisor.h> 38 #include <asm/processor.h> 39 #include <asm/tlbflush.h> 40 #include <asm/debugreg.h> 41 #include <asm/sections.h> 42 #include <asm/vsyscall.h> 43 #include <linux/topology.h> 44 #include <linux/cpumask.h> 45 #include <linux/atomic.h> 46 #include <asm/proto.h> 47 #include <asm/setup.h> 48 #include <asm/apic.h> 49 #include <asm/desc.h> 50 #include <asm/fpu/api.h> 51 #include <asm/mtrr.h> 52 #include <asm/hwcap2.h> 53 #include <linux/numa.h> 54 #include <asm/numa.h> 55 #include <asm/asm.h> 56 #include <asm/bugs.h> 57 #include <asm/cpu.h> 58 #include <asm/mce.h> 59 #include <asm/msr.h> 60 #include <asm/cacheinfo.h> 61 #include <asm/memtype.h> 62 #include <asm/microcode.h> 63 #include <asm/intel-family.h> 64 #include <asm/cpu_device_id.h> 65 #include <asm/fred.h> 66 #include <asm/uv/uv.h> 67 #include <asm/ia32.h> 68 #include <asm/set_memory.h> 69 #include <asm/traps.h> 70 #include <asm/sev.h> 71 #include <asm/tdx.h> 72 #include <asm/posted_intr.h> 73 #include <asm/runtime-const.h> 74 75 #include "cpu.h" 76 77 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 78 EXPORT_PER_CPU_SYMBOL(cpu_info); 79 80 u32 elf_hwcap2 __read_mostly; 81 82 /* Number of siblings per CPU package */ 83 unsigned int __max_threads_per_core __ro_after_init = 1; 84 EXPORT_SYMBOL(__max_threads_per_core); 85 86 unsigned int __max_dies_per_package __ro_after_init = 1; 87 EXPORT_SYMBOL(__max_dies_per_package); 88 89 unsigned int __max_logical_packages __ro_after_init = 1; 90 EXPORT_SYMBOL(__max_logical_packages); 91 92 unsigned int __num_cores_per_package __ro_after_init = 1; 93 EXPORT_SYMBOL(__num_cores_per_package); 94 95 unsigned int __num_threads_per_package __ro_after_init = 1; 96 EXPORT_SYMBOL(__num_threads_per_package); 97 98 static struct ppin_info { 99 int feature; 100 int msr_ppin_ctl; 101 int msr_ppin; 102 } ppin_info[] = { 103 [X86_VENDOR_INTEL] = { 104 .feature = X86_FEATURE_INTEL_PPIN, 105 .msr_ppin_ctl = MSR_PPIN_CTL, 106 .msr_ppin = MSR_PPIN 107 }, 108 [X86_VENDOR_AMD] = { 109 .feature = X86_FEATURE_AMD_PPIN, 110 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 111 .msr_ppin = MSR_AMD_PPIN 112 }, 113 }; 114 115 static const struct x86_cpu_id ppin_cpuids[] = { 116 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 117 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 118 119 /* Legacy models without CPUID enumeration */ 120 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 125 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 126 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 127 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 128 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 129 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 130 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 131 132 {} 133 }; 134 135 static void ppin_init(struct cpuinfo_x86 *c) 136 { 137 const struct x86_cpu_id *id; 138 unsigned long long val; 139 struct ppin_info *info; 140 141 id = x86_match_cpu(ppin_cpuids); 142 if (!id) 143 return; 144 145 /* 146 * Testing the presence of the MSR is not enough. Need to check 147 * that the PPIN_CTL allows reading of the PPIN. 148 */ 149 info = (struct ppin_info *)id->driver_data; 150 151 if (rdmsrq_safe(info->msr_ppin_ctl, &val)) 152 goto clear_ppin; 153 154 if ((val & 3UL) == 1UL) { 155 /* PPIN locked in disabled mode */ 156 goto clear_ppin; 157 } 158 159 /* If PPIN is disabled, try to enable */ 160 if (!(val & 2UL)) { 161 wrmsrq_safe(info->msr_ppin_ctl, val | 2UL); 162 rdmsrq_safe(info->msr_ppin_ctl, &val); 163 } 164 165 /* Is the enable bit set? */ 166 if (val & 2UL) { 167 c->ppin = native_rdmsrq(info->msr_ppin); 168 set_cpu_cap(c, info->feature); 169 return; 170 } 171 172 clear_ppin: 173 setup_clear_cpu_cap(info->feature); 174 } 175 176 static void default_init(struct cpuinfo_x86 *c) 177 { 178 #ifdef CONFIG_X86_64 179 cpu_detect_cache_sizes(c); 180 #else 181 /* Not much we can do here... */ 182 /* Check if at least it has cpuid */ 183 if (c->cpuid_level == -1) { 184 /* No cpuid. It must be an ancient CPU */ 185 if (c->x86 == 4) 186 strcpy(c->x86_model_id, "486"); 187 else if (c->x86 == 3) 188 strcpy(c->x86_model_id, "386"); 189 } 190 #endif 191 } 192 193 static const struct cpu_dev default_cpu = { 194 .c_init = default_init, 195 .c_vendor = "Unknown", 196 .c_x86_vendor = X86_VENDOR_UNKNOWN, 197 }; 198 199 static const struct cpu_dev *this_cpu = &default_cpu; 200 201 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 202 #ifdef CONFIG_X86_64 203 /* 204 * We need valid kernel segments for data and code in long mode too 205 * IRET will check the segment types kkeil 2000/10/28 206 * Also sysret mandates a special GDT layout 207 * 208 * TLS descriptors are currently at a different place compared to i386. 209 * Hopefully nobody expects them at a fixed place (Wine?) 210 */ 211 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 212 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 213 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff), 214 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 215 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff), 216 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff), 217 #else 218 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 219 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 220 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 221 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff), 222 /* 223 * Segments used for calling PnP BIOS have byte granularity. 224 * They code segments and data segments have fixed 64k limits, 225 * the transfer segment sizes are set at run time. 226 */ 227 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 228 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 229 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff), 230 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 231 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 232 /* 233 * The APM segments have byte granularity and their bases 234 * are set at run time. All have 64k limits. 235 */ 236 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 237 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 238 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff), 239 240 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 241 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 242 #endif 243 } }; 244 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 245 SYM_PIC_ALIAS(gdt_page); 246 247 #ifdef CONFIG_X86_64 248 static int __init x86_nopcid_setup(char *s) 249 { 250 /* nopcid doesn't accept parameters */ 251 if (s) 252 return -EINVAL; 253 254 /* do not emit a message if the feature is not present */ 255 if (!boot_cpu_has(X86_FEATURE_PCID)) 256 return 0; 257 258 setup_clear_cpu_cap(X86_FEATURE_PCID); 259 pr_info("nopcid: PCID feature disabled\n"); 260 return 0; 261 } 262 early_param("nopcid", x86_nopcid_setup); 263 #endif 264 265 static int __init x86_noinvpcid_setup(char *s) 266 { 267 /* noinvpcid doesn't accept parameters */ 268 if (s) 269 return -EINVAL; 270 271 /* do not emit a message if the feature is not present */ 272 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 273 return 0; 274 275 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 276 pr_info("noinvpcid: INVPCID feature disabled\n"); 277 return 0; 278 } 279 early_param("noinvpcid", x86_noinvpcid_setup); 280 281 /* Standard macro to see if a specific flag is changeable */ 282 static inline bool flag_is_changeable_p(unsigned long flag) 283 { 284 unsigned long f1, f2; 285 286 if (!IS_ENABLED(CONFIG_X86_32)) 287 return true; 288 289 /* 290 * Cyrix and IDT cpus allow disabling of CPUID 291 * so the code below may return different results 292 * when it is executed before and after enabling 293 * the CPUID. Add "volatile" to not allow gcc to 294 * optimize the subsequent calls to this function. 295 */ 296 asm volatile ("pushfl \n\t" 297 "pushfl \n\t" 298 "popl %0 \n\t" 299 "movl %0, %1 \n\t" 300 "xorl %2, %0 \n\t" 301 "pushl %0 \n\t" 302 "popfl \n\t" 303 "pushfl \n\t" 304 "popl %0 \n\t" 305 "popfl \n\t" 306 307 : "=&r" (f1), "=&r" (f2) 308 : "ir" (flag)); 309 310 return (f1 ^ f2) & flag; 311 } 312 313 #ifdef CONFIG_X86_32 314 static int cachesize_override = -1; 315 static int disable_x86_serial_nr = 1; 316 317 static int __init cachesize_setup(char *str) 318 { 319 get_option(&str, &cachesize_override); 320 return 1; 321 } 322 __setup("cachesize=", cachesize_setup); 323 324 /* Probe for the CPUID instruction */ 325 bool cpuid_feature(void) 326 { 327 return flag_is_changeable_p(X86_EFLAGS_ID); 328 } 329 330 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 331 { 332 unsigned long lo, hi; 333 334 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 335 return; 336 337 /* Disable processor serial number: */ 338 339 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 340 lo |= 0x200000; 341 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 342 343 pr_notice("CPU serial number disabled.\n"); 344 clear_cpu_cap(c, X86_FEATURE_PN); 345 346 /* Disabling the serial number may affect the cpuid level */ 347 c->cpuid_level = cpuid_eax(0); 348 } 349 350 static int __init x86_serial_nr_setup(char *s) 351 { 352 disable_x86_serial_nr = 0; 353 return 1; 354 } 355 __setup("serialnumber", x86_serial_nr_setup); 356 #else 357 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 358 { 359 } 360 #endif 361 362 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 363 { 364 if (cpu_has(c, X86_FEATURE_SMEP)) 365 cr4_set_bits(X86_CR4_SMEP); 366 } 367 368 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 369 { 370 unsigned long eflags = native_save_fl(); 371 372 /* This should have been cleared long ago */ 373 BUG_ON(eflags & X86_EFLAGS_AC); 374 375 if (cpu_has(c, X86_FEATURE_SMAP)) 376 cr4_set_bits(X86_CR4_SMAP); 377 } 378 379 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 380 { 381 /* Check the boot processor, plus build option for UMIP. */ 382 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 383 goto out; 384 385 /* Check the current processor's cpuid bits. */ 386 if (!cpu_has(c, X86_FEATURE_UMIP)) 387 goto out; 388 389 cr4_set_bits(X86_CR4_UMIP); 390 391 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 392 393 return; 394 395 out: 396 /* 397 * Make sure UMIP is disabled in case it was enabled in a 398 * previous boot (e.g., via kexec). 399 */ 400 cr4_clear_bits(X86_CR4_UMIP); 401 } 402 403 /* These bits should not change their value after CPU init is finished. */ 404 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 405 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; 406 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 407 static unsigned long cr4_pinned_bits __ro_after_init; 408 409 void native_write_cr0(unsigned long val) 410 { 411 unsigned long bits_missing = 0; 412 413 set_register: 414 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 415 416 if (static_branch_likely(&cr_pinning)) { 417 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 418 bits_missing = X86_CR0_WP; 419 val |= bits_missing; 420 goto set_register; 421 } 422 /* Warn after we've set the missing bits. */ 423 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 424 } 425 } 426 EXPORT_SYMBOL(native_write_cr0); 427 428 void __no_profile native_write_cr4(unsigned long val) 429 { 430 unsigned long bits_changed = 0; 431 432 set_register: 433 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 434 435 if (static_branch_likely(&cr_pinning)) { 436 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 437 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 438 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 439 goto set_register; 440 } 441 /* Warn after we've corrected the changed bits. */ 442 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 443 bits_changed); 444 } 445 } 446 #if IS_MODULE(CONFIG_LKDTM) 447 EXPORT_SYMBOL_GPL(native_write_cr4); 448 #endif 449 450 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 451 { 452 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 453 454 lockdep_assert_irqs_disabled(); 455 456 newval = (cr4 & ~clear) | set; 457 if (newval != cr4) { 458 this_cpu_write(cpu_tlbstate.cr4, newval); 459 __write_cr4(newval); 460 } 461 } 462 EXPORT_SYMBOL(cr4_update_irqsoff); 463 464 /* Read the CR4 shadow. */ 465 unsigned long cr4_read_shadow(void) 466 { 467 return this_cpu_read(cpu_tlbstate.cr4); 468 } 469 EXPORT_SYMBOL_GPL(cr4_read_shadow); 470 471 void cr4_init(void) 472 { 473 unsigned long cr4 = __read_cr4(); 474 475 if (boot_cpu_has(X86_FEATURE_PCID)) 476 cr4 |= X86_CR4_PCIDE; 477 if (static_branch_likely(&cr_pinning)) 478 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 479 480 __write_cr4(cr4); 481 482 /* Initialize cr4 shadow for this CPU. */ 483 this_cpu_write(cpu_tlbstate.cr4, cr4); 484 } 485 486 /* 487 * Once CPU feature detection is finished (and boot params have been 488 * parsed), record any of the sensitive CR bits that are set, and 489 * enable CR pinning. 490 */ 491 static void __init setup_cr_pinning(void) 492 { 493 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 494 static_key_enable(&cr_pinning.key); 495 } 496 497 static __init int x86_nofsgsbase_setup(char *arg) 498 { 499 /* Require an exact match without trailing characters. */ 500 if (strlen(arg)) 501 return 0; 502 503 /* Do not emit a message if the feature is not present. */ 504 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 505 return 1; 506 507 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 508 pr_info("FSGSBASE disabled via kernel command line\n"); 509 return 1; 510 } 511 __setup("nofsgsbase", x86_nofsgsbase_setup); 512 513 /* 514 * Protection Keys are not available in 32-bit mode. 515 */ 516 static bool pku_disabled; 517 518 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 519 { 520 if (c == &boot_cpu_data) { 521 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 522 return; 523 /* 524 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 525 * bit to be set. Enforce it. 526 */ 527 setup_force_cpu_cap(X86_FEATURE_OSPKE); 528 529 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 530 return; 531 } 532 533 cr4_set_bits(X86_CR4_PKE); 534 /* Load the default PKRU value */ 535 pkru_write_default(); 536 } 537 538 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 539 static __init int setup_disable_pku(char *arg) 540 { 541 /* 542 * Do not clear the X86_FEATURE_PKU bit. All of the 543 * runtime checks are against OSPKE so clearing the 544 * bit does nothing. 545 * 546 * This way, we will see "pku" in cpuinfo, but not 547 * "ospke", which is exactly what we want. It shows 548 * that the CPU has PKU, but the OS has not enabled it. 549 * This happens to be exactly how a system would look 550 * if we disabled the config option. 551 */ 552 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 553 pku_disabled = true; 554 return 1; 555 } 556 __setup("nopku", setup_disable_pku); 557 #endif 558 559 #ifdef CONFIG_X86_KERNEL_IBT 560 561 __noendbr u64 ibt_save(bool disable) 562 { 563 u64 msr = 0; 564 565 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 566 rdmsrq(MSR_IA32_S_CET, msr); 567 if (disable) 568 wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 569 } 570 571 return msr; 572 } 573 574 __noendbr void ibt_restore(u64 save) 575 { 576 u64 msr; 577 578 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 579 rdmsrq(MSR_IA32_S_CET, msr); 580 msr &= ~CET_ENDBR_EN; 581 msr |= (save & CET_ENDBR_EN); 582 wrmsrq(MSR_IA32_S_CET, msr); 583 } 584 } 585 586 #endif 587 588 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 589 { 590 bool user_shstk, kernel_ibt; 591 592 if (!IS_ENABLED(CONFIG_X86_CET)) 593 return; 594 595 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 596 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 597 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 598 599 if (!kernel_ibt && !user_shstk) 600 return; 601 602 if (user_shstk) 603 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 604 605 if (kernel_ibt) 606 wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN); 607 else 608 wrmsrq(MSR_IA32_S_CET, 0); 609 610 cr4_set_bits(X86_CR4_CET); 611 612 if (kernel_ibt && ibt_selftest()) { 613 pr_err("IBT selftest: Failed!\n"); 614 wrmsrq(MSR_IA32_S_CET, 0); 615 setup_clear_cpu_cap(X86_FEATURE_IBT); 616 } 617 } 618 619 __noendbr void cet_disable(void) 620 { 621 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 622 cpu_feature_enabled(X86_FEATURE_SHSTK))) 623 return; 624 625 wrmsrq(MSR_IA32_S_CET, 0); 626 wrmsrq(MSR_IA32_U_CET, 0); 627 } 628 629 /* 630 * Some CPU features depend on higher CPUID levels, which may not always 631 * be available due to CPUID level capping or broken virtualization 632 * software. Add those features to this table to auto-disable them. 633 */ 634 struct cpuid_dependent_feature { 635 u32 feature; 636 u32 level; 637 }; 638 639 static const struct cpuid_dependent_feature 640 cpuid_dependent_features[] = { 641 { X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT }, 642 { X86_FEATURE_DCA, CPUID_LEAF_DCA }, 643 { X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE }, 644 { 0, 0 } 645 }; 646 647 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 648 { 649 const struct cpuid_dependent_feature *df; 650 651 for (df = cpuid_dependent_features; df->feature; df++) { 652 653 if (!cpu_has(c, df->feature)) 654 continue; 655 /* 656 * Note: cpuid_level is set to -1 if unavailable, but 657 * extended_extended_level is set to 0 if unavailable 658 * and the legitimate extended levels are all negative 659 * when signed; hence the weird messing around with 660 * signs here... 661 */ 662 if (!((s32)df->level < 0 ? 663 (u32)df->level > (u32)c->extended_cpuid_level : 664 (s32)df->level > (s32)c->cpuid_level)) 665 continue; 666 667 clear_cpu_cap(c, df->feature); 668 if (!warn) 669 continue; 670 671 pr_warn("CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 672 x86_cap_flags[df->feature], df->level); 673 } 674 } 675 676 /* 677 * Naming convention should be: <Name> [(<Codename>)] 678 * This table only is used unless init_<vendor>() below doesn't set it; 679 * in particular, if CPUID levels 0x80000002..4 are supported, this 680 * isn't used 681 */ 682 683 /* Look up CPU names by table lookup. */ 684 static const char *table_lookup_model(struct cpuinfo_x86 *c) 685 { 686 #ifdef CONFIG_X86_32 687 const struct legacy_cpu_model_info *info; 688 689 if (c->x86_model >= 16) 690 return NULL; /* Range check */ 691 692 if (!this_cpu) 693 return NULL; 694 695 info = this_cpu->legacy_models; 696 697 while (info->family) { 698 if (info->family == c->x86) 699 return info->model_names[c->x86_model]; 700 info++; 701 } 702 #endif 703 return NULL; /* Not found */ 704 } 705 706 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 707 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 708 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 709 710 #ifdef CONFIG_X86_32 711 /* The 32-bit entry code needs to find cpu_entry_area. */ 712 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 713 #endif 714 715 /* Load the original GDT from the per-cpu structure */ 716 void load_direct_gdt(int cpu) 717 { 718 struct desc_ptr gdt_descr; 719 720 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 721 gdt_descr.size = GDT_SIZE - 1; 722 load_gdt(&gdt_descr); 723 } 724 EXPORT_SYMBOL_GPL(load_direct_gdt); 725 726 /* Load a fixmap remapping of the per-cpu GDT */ 727 void load_fixmap_gdt(int cpu) 728 { 729 struct desc_ptr gdt_descr; 730 731 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 732 gdt_descr.size = GDT_SIZE - 1; 733 load_gdt(&gdt_descr); 734 } 735 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 736 737 /** 738 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 739 * @cpu: The CPU number for which this is invoked 740 * 741 * Invoked during early boot to switch from early GDT and early per CPU to 742 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 743 * switch is implicit by loading the direct GDT. On 64bit this requires 744 * to update GSBASE. 745 */ 746 void __init switch_gdt_and_percpu_base(int cpu) 747 { 748 load_direct_gdt(cpu); 749 750 #ifdef CONFIG_X86_64 751 /* 752 * No need to load %gs. It is already correct. 753 * 754 * Writing %gs on 64bit would zero GSBASE which would make any per 755 * CPU operation up to the point of the wrmsrq() fault. 756 * 757 * Set GSBASE to the new offset. Until the wrmsrq() happens the 758 * early mapping is still valid. That means the GSBASE update will 759 * lose any prior per CPU data which was not copied over in 760 * setup_per_cpu_areas(). 761 * 762 * This works even with stackprotector enabled because the 763 * per CPU stack canary is 0 in both per CPU areas. 764 */ 765 wrmsrq(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 766 #else 767 /* 768 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 769 * it is required to load FS again so that the 'hidden' part is 770 * updated from the new GDT. Up to this point the early per CPU 771 * translation is active. Any content of the early per CPU data 772 * which was not copied over in setup_per_cpu_areas() is lost. 773 */ 774 loadsegment(fs, __KERNEL_PERCPU); 775 #endif 776 } 777 778 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 779 780 static void get_model_name(struct cpuinfo_x86 *c) 781 { 782 unsigned int *v; 783 char *p, *q, *s; 784 785 if (c->extended_cpuid_level < 0x80000004) 786 return; 787 788 v = (unsigned int *)c->x86_model_id; 789 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 790 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 791 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 792 c->x86_model_id[48] = 0; 793 794 /* Trim whitespace */ 795 p = q = s = &c->x86_model_id[0]; 796 797 while (*p == ' ') 798 p++; 799 800 while (*p) { 801 /* Note the last non-whitespace index */ 802 if (!isspace(*p)) 803 s = q; 804 805 *q++ = *p++; 806 } 807 808 *(s + 1) = '\0'; 809 } 810 811 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 812 { 813 unsigned int n, dummy, ebx, ecx, edx, l2size; 814 815 n = c->extended_cpuid_level; 816 817 if (n >= 0x80000005) { 818 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 819 c->x86_cache_size = (ecx>>24) + (edx>>24); 820 #ifdef CONFIG_X86_64 821 /* On K8 L1 TLB is inclusive, so don't count it */ 822 c->x86_tlbsize = 0; 823 #endif 824 } 825 826 if (n < 0x80000006) /* Some chips just has a large L1. */ 827 return; 828 829 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 830 l2size = ecx >> 16; 831 832 #ifdef CONFIG_X86_64 833 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 834 #else 835 /* do processor-specific cache resizing */ 836 if (this_cpu->legacy_cache_size) 837 l2size = this_cpu->legacy_cache_size(c, l2size); 838 839 /* Allow user to override all this if necessary. */ 840 if (cachesize_override != -1) 841 l2size = cachesize_override; 842 843 if (l2size == 0) 844 return; /* Again, no L2 cache is possible */ 845 #endif 846 847 c->x86_cache_size = l2size; 848 } 849 850 u16 __read_mostly tlb_lli_4k; 851 u16 __read_mostly tlb_lli_2m; 852 u16 __read_mostly tlb_lli_4m; 853 u16 __read_mostly tlb_lld_4k; 854 u16 __read_mostly tlb_lld_2m; 855 u16 __read_mostly tlb_lld_4m; 856 u16 __read_mostly tlb_lld_1g; 857 858 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 859 { 860 if (this_cpu->c_detect_tlb) 861 this_cpu->c_detect_tlb(c); 862 863 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 864 tlb_lli_4k, tlb_lli_2m, tlb_lli_4m); 865 866 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 867 tlb_lld_4k, tlb_lld_2m, tlb_lld_4m, tlb_lld_1g); 868 } 869 870 void get_cpu_vendor(struct cpuinfo_x86 *c) 871 { 872 char *v = c->x86_vendor_id; 873 int i; 874 875 for (i = 0; i < X86_VENDOR_NUM; i++) { 876 if (!cpu_devs[i]) 877 break; 878 879 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 880 (cpu_devs[i]->c_ident[1] && 881 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 882 883 this_cpu = cpu_devs[i]; 884 c->x86_vendor = this_cpu->c_x86_vendor; 885 return; 886 } 887 } 888 889 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 890 "CPU: Your system may be unstable.\n", v); 891 892 c->x86_vendor = X86_VENDOR_UNKNOWN; 893 this_cpu = &default_cpu; 894 } 895 896 void cpu_detect(struct cpuinfo_x86 *c) 897 { 898 /* Get vendor name */ 899 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 900 (unsigned int *)&c->x86_vendor_id[0], 901 (unsigned int *)&c->x86_vendor_id[8], 902 (unsigned int *)&c->x86_vendor_id[4]); 903 904 c->x86 = 4; 905 /* Intel-defined flags: level 0x00000001 */ 906 if (c->cpuid_level >= 0x00000001) { 907 u32 junk, tfms, cap0, misc; 908 909 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 910 c->x86 = x86_family(tfms); 911 c->x86_model = x86_model(tfms); 912 c->x86_stepping = x86_stepping(tfms); 913 914 if (cap0 & (1<<19)) { 915 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 916 c->x86_cache_alignment = c->x86_clflush_size; 917 } 918 } 919 } 920 921 static void apply_forced_caps(struct cpuinfo_x86 *c) 922 { 923 int i; 924 925 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 926 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 927 c->x86_capability[i] |= cpu_caps_set[i]; 928 } 929 } 930 931 static void init_speculation_control(struct cpuinfo_x86 *c) 932 { 933 /* 934 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 935 * and they also have a different bit for STIBP support. Also, 936 * a hypervisor might have set the individual AMD bits even on 937 * Intel CPUs, for finer-grained selection of what's available. 938 */ 939 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 940 set_cpu_cap(c, X86_FEATURE_IBRS); 941 set_cpu_cap(c, X86_FEATURE_IBPB); 942 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 943 } 944 945 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 946 set_cpu_cap(c, X86_FEATURE_STIBP); 947 948 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 949 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 950 set_cpu_cap(c, X86_FEATURE_SSBD); 951 952 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 953 set_cpu_cap(c, X86_FEATURE_IBRS); 954 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 955 } 956 957 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 958 set_cpu_cap(c, X86_FEATURE_IBPB); 959 960 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 961 set_cpu_cap(c, X86_FEATURE_STIBP); 962 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 963 } 964 965 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 966 set_cpu_cap(c, X86_FEATURE_SSBD); 967 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 968 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 969 } 970 } 971 972 void get_cpu_cap(struct cpuinfo_x86 *c) 973 { 974 u32 eax, ebx, ecx, edx; 975 976 /* Intel-defined flags: level 0x00000001 */ 977 if (c->cpuid_level >= 0x00000001) { 978 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 979 980 c->x86_capability[CPUID_1_ECX] = ecx; 981 c->x86_capability[CPUID_1_EDX] = edx; 982 } 983 984 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 985 if (c->cpuid_level >= 0x00000006) 986 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 987 988 /* Additional Intel-defined flags: level 0x00000007 */ 989 if (c->cpuid_level >= 0x00000007) { 990 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 991 c->x86_capability[CPUID_7_0_EBX] = ebx; 992 c->x86_capability[CPUID_7_ECX] = ecx; 993 c->x86_capability[CPUID_7_EDX] = edx; 994 995 /* Check valid sub-leaf index before accessing it */ 996 if (eax >= 1) { 997 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 998 c->x86_capability[CPUID_7_1_EAX] = eax; 999 } 1000 } 1001 1002 /* Extended state features: level 0x0000000d */ 1003 if (c->cpuid_level >= 0x0000000d) { 1004 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1005 1006 c->x86_capability[CPUID_D_1_EAX] = eax; 1007 } 1008 1009 /* 1010 * Check if extended CPUID leaves are implemented: Max extended 1011 * CPUID leaf must be in the 0x80000001-0x8000ffff range. 1012 */ 1013 eax = cpuid_eax(0x80000000); 1014 c->extended_cpuid_level = ((eax & 0xffff0000) == 0x80000000) ? eax : 0; 1015 1016 if (c->extended_cpuid_level >= 0x80000001) { 1017 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1018 1019 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1020 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1021 } 1022 1023 if (c->extended_cpuid_level >= 0x80000007) { 1024 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1025 1026 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1027 c->x86_power = edx; 1028 } 1029 1030 if (c->extended_cpuid_level >= 0x80000008) { 1031 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1032 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1033 } 1034 1035 if (c->extended_cpuid_level >= 0x8000000a) 1036 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1037 1038 if (c->extended_cpuid_level >= 0x8000001f) 1039 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1040 1041 if (c->extended_cpuid_level >= 0x80000021) 1042 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1043 1044 init_scattered_cpuid_features(c); 1045 init_speculation_control(c); 1046 1047 /* 1048 * Clear/Set all flags overridden by options, after probe. 1049 * This needs to happen each time we re-probe, which may happen 1050 * several times during CPU initialization. 1051 */ 1052 apply_forced_caps(c); 1053 } 1054 1055 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1056 { 1057 u32 eax, ebx, ecx, edx; 1058 1059 if (!cpu_has(c, X86_FEATURE_CPUID) || 1060 (c->extended_cpuid_level < 0x80000008)) { 1061 if (IS_ENABLED(CONFIG_X86_64)) { 1062 c->x86_clflush_size = 64; 1063 c->x86_phys_bits = 36; 1064 c->x86_virt_bits = 48; 1065 } else { 1066 c->x86_clflush_size = 32; 1067 c->x86_virt_bits = 32; 1068 c->x86_phys_bits = 32; 1069 1070 if (cpu_has(c, X86_FEATURE_PAE) || 1071 cpu_has(c, X86_FEATURE_PSE36)) 1072 c->x86_phys_bits = 36; 1073 } 1074 } else { 1075 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1076 1077 c->x86_virt_bits = (eax >> 8) & 0xff; 1078 c->x86_phys_bits = eax & 0xff; 1079 1080 /* Provide a sane default if not enumerated: */ 1081 if (!c->x86_clflush_size) 1082 c->x86_clflush_size = 32; 1083 } 1084 1085 c->x86_cache_bits = c->x86_phys_bits; 1086 c->x86_cache_alignment = c->x86_clflush_size; 1087 } 1088 1089 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1090 { 1091 int i; 1092 1093 /* 1094 * First of all, decide if this is a 486 or higher 1095 * It's a 486 if we can modify the AC flag 1096 */ 1097 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1098 c->x86 = 4; 1099 else 1100 c->x86 = 3; 1101 1102 for (i = 0; i < X86_VENDOR_NUM; i++) 1103 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1104 c->x86_vendor_id[0] = 0; 1105 cpu_devs[i]->c_identify(c); 1106 if (c->x86_vendor_id[0]) { 1107 get_cpu_vendor(c); 1108 break; 1109 } 1110 } 1111 } 1112 1113 #define NO_SPECULATION BIT(0) 1114 #define NO_MELTDOWN BIT(1) 1115 #define NO_SSB BIT(2) 1116 #define NO_L1TF BIT(3) 1117 #define NO_MDS BIT(4) 1118 #define MSBDS_ONLY BIT(5) 1119 #define NO_SWAPGS BIT(6) 1120 #define NO_ITLB_MULTIHIT BIT(7) 1121 #define NO_SPECTRE_V2 BIT(8) 1122 #define NO_MMIO BIT(9) 1123 #define NO_EIBRS_PBRSB BIT(10) 1124 #define NO_BHI BIT(11) 1125 1126 #define VULNWL(vendor, family, model, whitelist) \ 1127 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1128 1129 #define VULNWL_INTEL(vfm, whitelist) \ 1130 X86_MATCH_VFM(vfm, whitelist) 1131 1132 #define VULNWL_AMD(family, whitelist) \ 1133 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1134 1135 #define VULNWL_HYGON(family, whitelist) \ 1136 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1137 1138 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1139 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1140 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1141 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1142 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1143 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1144 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1145 1146 /* Intel Family 6 */ 1147 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), 1148 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), 1149 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), 1150 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), 1151 1152 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1153 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1154 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1155 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1156 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1157 1158 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1159 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1160 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1161 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1162 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1163 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1164 1165 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), 1166 1167 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY), 1168 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1169 1170 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1171 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1172 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1173 1174 /* 1175 * Technically, swapgs isn't serializing on AMD (despite it previously 1176 * being documented as such in the APM). But according to AMD, %gs is 1177 * updated non-speculatively, and the issuing of %gs-relative memory 1178 * operands will be blocked until the %gs update completes, which is 1179 * good enough for our purposes. 1180 */ 1181 1182 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), 1183 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1184 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1185 1186 /* AMD Family 0xf - 0x12 */ 1187 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1188 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1189 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1190 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1191 1192 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1193 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1194 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1195 1196 /* Zhaoxin Family 7 */ 1197 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1198 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1199 {} 1200 }; 1201 1202 #define VULNBL(vendor, family, model, blacklist) \ 1203 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1204 1205 #define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \ 1206 X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues) 1207 1208 #define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \ 1209 X86_MATCH_VFM_CPU_TYPE(vfm, INTEL_CPU_TYPE_##cpu_type, issues) 1210 1211 #define VULNBL_AMD(family, blacklist) \ 1212 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1213 1214 #define VULNBL_HYGON(family, blacklist) \ 1215 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1216 1217 #define SRBDS BIT(0) 1218 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1219 #define MMIO BIT(1) 1220 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1221 #define MMIO_SBDS BIT(2) 1222 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1223 #define RETBLEED BIT(3) 1224 /* CPU is affected by SMT (cross-thread) return predictions */ 1225 #define SMT_RSB BIT(4) 1226 /* CPU is affected by SRSO */ 1227 #define SRSO BIT(5) 1228 /* CPU is affected by GDS */ 1229 #define GDS BIT(6) 1230 /* CPU is affected by Register File Data Sampling */ 1231 #define RFDS BIT(7) 1232 /* CPU is affected by Indirect Target Selection */ 1233 #define ITS BIT(8) 1234 /* CPU is affected by Indirect Target Selection, but guest-host isolation is not affected */ 1235 #define ITS_NATIVE_ONLY BIT(9) 1236 /* CPU is affected by Transient Scheduler Attacks */ 1237 #define TSA BIT(10) 1238 1239 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1240 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS), 1241 VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS), 1242 VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS), 1243 VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS), 1244 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO), 1245 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO), 1246 VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS), 1247 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO), 1248 VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS), 1249 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, 0x5, MMIO | RETBLEED | GDS), 1250 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS), 1251 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS), 1252 VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS), 1253 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, 0xb, MMIO | RETBLEED | GDS | SRBDS), 1254 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS), 1255 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, 0xc, MMIO | RETBLEED | GDS | SRBDS), 1256 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS), 1257 VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED), 1258 VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1259 VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1260 VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1261 VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS), 1262 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED | ITS), 1263 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS), 1264 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1265 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1266 VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED), 1267 VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1268 VULNBL_INTEL_TYPE(INTEL_ALDERLAKE, ATOM, RFDS), 1269 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS), 1270 VULNBL_INTEL_TYPE(INTEL_RAPTORLAKE, ATOM, RFDS), 1271 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS), 1272 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS), 1273 VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS), 1274 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1275 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS), 1276 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1277 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS), 1278 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS), 1279 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS), 1280 1281 VULNBL_AMD(0x15, RETBLEED), 1282 VULNBL_AMD(0x16, RETBLEED), 1283 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), 1284 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), 1285 VULNBL_AMD(0x19, SRSO | TSA), 1286 VULNBL_AMD(0x1a, SRSO), 1287 {} 1288 }; 1289 1290 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1291 { 1292 const struct x86_cpu_id *m = x86_match_cpu(table); 1293 1294 return m && !!(m->driver_data & which); 1295 } 1296 1297 u64 x86_read_arch_cap_msr(void) 1298 { 1299 u64 x86_arch_cap_msr = 0; 1300 1301 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1302 rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1303 1304 return x86_arch_cap_msr; 1305 } 1306 1307 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr) 1308 { 1309 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO && 1310 x86_arch_cap_msr & ARCH_CAP_PSDP_NO && 1311 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO); 1312 } 1313 1314 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr) 1315 { 1316 /* The "immunity" bit trumps everything else: */ 1317 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO) 1318 return false; 1319 1320 /* 1321 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to 1322 * indicate that mitigation is needed because guest is running on a 1323 * vulnerable hardware or may migrate to such hardware: 1324 */ 1325 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 1326 return true; 1327 1328 /* Only consult the blacklist when there is no enumeration: */ 1329 return cpu_matches(cpu_vuln_blacklist, RFDS); 1330 } 1331 1332 static bool __init vulnerable_to_its(u64 x86_arch_cap_msr) 1333 { 1334 /* The "immunity" bit trumps everything else: */ 1335 if (x86_arch_cap_msr & ARCH_CAP_ITS_NO) 1336 return false; 1337 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 1338 return false; 1339 1340 /* None of the affected CPUs have BHI_CTRL */ 1341 if (boot_cpu_has(X86_FEATURE_BHI_CTRL)) 1342 return false; 1343 1344 /* 1345 * If a VMM did not expose ITS_NO, assume that a guest could 1346 * be running on a vulnerable hardware or may migrate to such 1347 * hardware. 1348 */ 1349 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1350 return true; 1351 1352 if (cpu_matches(cpu_vuln_blacklist, ITS)) 1353 return true; 1354 1355 return false; 1356 } 1357 1358 static struct x86_cpu_id cpu_latest_microcode[] = { 1359 #include "microcode/intel-ucode-defs.h" 1360 {} 1361 }; 1362 1363 static bool __init cpu_has_old_microcode(void) 1364 { 1365 const struct x86_cpu_id *m = x86_match_cpu(cpu_latest_microcode); 1366 1367 /* Give unknown CPUs a pass: */ 1368 if (!m) { 1369 /* Intel CPUs should be in the list. Warn if not: */ 1370 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 1371 pr_info("x86/CPU: Model not found in latest microcode list\n"); 1372 return false; 1373 } 1374 1375 /* 1376 * Hosts usually lie to guests with a super high microcode 1377 * version. Just ignore what hosts tell guests: 1378 */ 1379 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1380 return false; 1381 1382 /* Consider all debug microcode to be old: */ 1383 if (boot_cpu_data.microcode & BIT(31)) 1384 return true; 1385 1386 /* Give new microcode a pass: */ 1387 if (boot_cpu_data.microcode >= m->driver_data) 1388 return false; 1389 1390 /* Uh oh, too old: */ 1391 return true; 1392 } 1393 1394 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1395 { 1396 u64 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1397 1398 if (cpu_has_old_microcode()) { 1399 pr_warn("x86/CPU: Running old microcode\n"); 1400 setup_force_cpu_bug(X86_BUG_OLD_MICROCODE); 1401 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1402 } 1403 1404 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1405 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1406 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO)) 1407 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1408 1409 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1410 return; 1411 1412 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1413 1414 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) { 1415 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1416 setup_force_cpu_bug(X86_BUG_SPECTRE_V2_USER); 1417 } 1418 1419 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1420 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) && 1421 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1422 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1423 1424 /* 1425 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1426 * flag and protect from vendor-specific bugs via the whitelist. 1427 * 1428 * Don't use AutoIBRS when SNP is enabled because it degrades host 1429 * userspace indirect branch performance. 1430 */ 1431 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || 1432 (cpu_has(c, X86_FEATURE_AUTOIBRS) && 1433 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { 1434 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1435 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1436 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO)) 1437 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1438 } 1439 1440 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1441 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) { 1442 setup_force_cpu_bug(X86_BUG_MDS); 1443 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1444 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1445 } 1446 1447 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1448 setup_force_cpu_bug(X86_BUG_SWAPGS); 1449 1450 /* 1451 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1452 * - TSX is supported or 1453 * - TSX_CTRL is present 1454 * 1455 * TSX_CTRL check is needed for cases when TSX could be disabled before 1456 * the kernel boot e.g. kexec. 1457 * TSX_CTRL check alone is not sufficient for cases when the microcode 1458 * update is not present or running as guest that don't get TSX_CTRL. 1459 */ 1460 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) && 1461 (cpu_has(c, X86_FEATURE_RTM) || 1462 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))) 1463 setup_force_cpu_bug(X86_BUG_TAA); 1464 1465 /* 1466 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1467 * in the vulnerability blacklist. 1468 * 1469 * Some of the implications and mitigation of Shared Buffers Data 1470 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1471 * SRBDS. 1472 */ 1473 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1474 cpu_has(c, X86_FEATURE_RDSEED)) && 1475 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1476 setup_force_cpu_bug(X86_BUG_SRBDS); 1477 1478 /* 1479 * Processor MMIO Stale Data bug enumeration 1480 * 1481 * Affected CPU list is generally enough to enumerate the vulnerability, 1482 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1483 * not want the guest to enumerate the bug. 1484 */ 1485 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { 1486 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1487 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1488 } 1489 1490 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1491 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA)) 1492 setup_force_cpu_bug(X86_BUG_RETBLEED); 1493 } 1494 1495 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1496 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1497 1498 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1499 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1500 setup_force_cpu_bug(X86_BUG_SRSO); 1501 } 1502 1503 /* 1504 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1505 * an affected processor, the VMM may have disabled the use of GATHER by 1506 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1507 * which means that AVX will be disabled. 1508 */ 1509 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) && 1510 boot_cpu_has(X86_FEATURE_AVX)) 1511 setup_force_cpu_bug(X86_BUG_GDS); 1512 1513 if (vulnerable_to_rfds(x86_arch_cap_msr)) 1514 setup_force_cpu_bug(X86_BUG_RFDS); 1515 1516 /* 1517 * Intel parts with eIBRS are vulnerable to BHI attacks. Parts with 1518 * BHI_NO still need to use the BHI mitigation to prevent Intra-mode 1519 * attacks. When virtualized, eIBRS could be hidden, assume vulnerable. 1520 */ 1521 if (!cpu_matches(cpu_vuln_whitelist, NO_BHI) && 1522 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) || 1523 boot_cpu_has(X86_FEATURE_HYPERVISOR))) 1524 setup_force_cpu_bug(X86_BUG_BHI); 1525 1526 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET)) 1527 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET); 1528 1529 if (vulnerable_to_its(x86_arch_cap_msr)) { 1530 setup_force_cpu_bug(X86_BUG_ITS); 1531 if (cpu_matches(cpu_vuln_blacklist, ITS_NATIVE_ONLY)) 1532 setup_force_cpu_bug(X86_BUG_ITS_NATIVE_ONLY); 1533 } 1534 1535 if (c->x86_vendor == X86_VENDOR_AMD) { 1536 if (!cpu_has(c, X86_FEATURE_TSA_SQ_NO) || 1537 !cpu_has(c, X86_FEATURE_TSA_L1_NO)) { 1538 if (cpu_matches(cpu_vuln_blacklist, TSA) || 1539 /* Enable bug on Zen guests to allow for live migration. */ 1540 (cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_ZEN))) 1541 setup_force_cpu_bug(X86_BUG_TSA); 1542 } 1543 } 1544 1545 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1546 return; 1547 1548 /* Rogue Data Cache Load? No! */ 1549 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO) 1550 return; 1551 1552 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1553 1554 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1555 return; 1556 1557 setup_force_cpu_bug(X86_BUG_L1TF); 1558 } 1559 1560 /* 1561 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1562 * unfortunately, that's not true in practice because of early VIA 1563 * chips and (more importantly) broken virtualizers that are not easy 1564 * to detect. In the latter case it doesn't even *fail* reliably, so 1565 * probing for it doesn't even work. Disable it completely on 32-bit 1566 * unless we can find a reliable way to detect all the broken cases. 1567 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1568 */ 1569 static void detect_nopl(void) 1570 { 1571 #ifdef CONFIG_X86_32 1572 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1573 #else 1574 setup_force_cpu_cap(X86_FEATURE_NOPL); 1575 #endif 1576 } 1577 1578 static inline bool parse_set_clear_cpuid(char *arg, bool set) 1579 { 1580 char *opt; 1581 int taint = 0; 1582 1583 while (arg) { 1584 bool found __maybe_unused = false; 1585 unsigned int bit; 1586 1587 opt = strsep(&arg, ","); 1588 1589 /* 1590 * Handle naked numbers first for feature flags which don't 1591 * have names. It doesn't make sense for a bug not to have a 1592 * name so don't handle bug flags here. 1593 */ 1594 if (!kstrtouint(opt, 10, &bit)) { 1595 if (bit < NCAPINTS * 32) { 1596 1597 if (set) { 1598 pr_warn("setcpuid: force-enabling CPU feature flag:"); 1599 setup_force_cpu_cap(bit); 1600 } else { 1601 pr_warn("clearcpuid: force-disabling CPU feature flag:"); 1602 setup_clear_cpu_cap(bit); 1603 } 1604 /* empty-string, i.e., ""-defined feature flags */ 1605 if (!x86_cap_flags[bit]) 1606 pr_cont(" %d:%d\n", bit >> 5, bit & 31); 1607 else 1608 pr_cont(" %s\n", x86_cap_flags[bit]); 1609 1610 taint++; 1611 } 1612 /* 1613 * The assumption is that there are no feature names with only 1614 * numbers in the name thus go to the next argument. 1615 */ 1616 continue; 1617 } 1618 1619 for (bit = 0; bit < 32 * (NCAPINTS + NBUGINTS); bit++) { 1620 const char *flag; 1621 const char *kind; 1622 1623 if (bit < 32 * NCAPINTS) { 1624 flag = x86_cap_flags[bit]; 1625 kind = "feature"; 1626 } else { 1627 kind = "bug"; 1628 flag = x86_bug_flags[bit - (32 * NCAPINTS)]; 1629 } 1630 1631 if (!flag) 1632 continue; 1633 1634 if (strcmp(flag, opt)) 1635 continue; 1636 1637 if (set) { 1638 pr_warn("setcpuid: force-enabling CPU %s flag: %s\n", 1639 kind, flag); 1640 setup_force_cpu_cap(bit); 1641 } else { 1642 pr_warn("clearcpuid: force-disabling CPU %s flag: %s\n", 1643 kind, flag); 1644 setup_clear_cpu_cap(bit); 1645 } 1646 taint++; 1647 found = true; 1648 break; 1649 } 1650 1651 if (!found) 1652 pr_warn("%s: unknown CPU flag: %s", set ? "setcpuid" : "clearcpuid", opt); 1653 } 1654 1655 return taint; 1656 } 1657 1658 1659 /* 1660 * We parse cpu parameters early because fpu__init_system() is executed 1661 * before parse_early_param(). 1662 */ 1663 static void __init cpu_parse_early_param(void) 1664 { 1665 bool cpuid_taint = false; 1666 char arg[128]; 1667 int arglen; 1668 1669 #ifdef CONFIG_X86_32 1670 if (cmdline_find_option_bool(boot_command_line, "no387")) 1671 #ifdef CONFIG_MATH_EMULATION 1672 setup_clear_cpu_cap(X86_FEATURE_FPU); 1673 #else 1674 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1675 #endif 1676 1677 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1678 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1679 #endif 1680 1681 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1682 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1683 1684 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1685 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1686 1687 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1688 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1689 1690 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1691 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1692 1693 /* Minimize the gap between FRED is available and available but disabled. */ 1694 arglen = cmdline_find_option(boot_command_line, "fred", arg, sizeof(arg)); 1695 if (arglen != 2 || strncmp(arg, "on", 2)) 1696 setup_clear_cpu_cap(X86_FEATURE_FRED); 1697 1698 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1699 if (arglen > 0) 1700 cpuid_taint |= parse_set_clear_cpuid(arg, false); 1701 1702 arglen = cmdline_find_option(boot_command_line, "setcpuid", arg, sizeof(arg)); 1703 if (arglen > 0) 1704 cpuid_taint |= parse_set_clear_cpuid(arg, true); 1705 1706 if (cpuid_taint) { 1707 pr_warn("!!! setcpuid=/clearcpuid= in use, this is for TESTING ONLY, may break things horribly. Tainting kernel.\n"); 1708 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1709 } 1710 } 1711 1712 /* 1713 * Do minimum CPU detection early. 1714 * Fields really needed: vendor, cpuid_level, family, model, mask, 1715 * cache alignment. 1716 * The others are not touched to avoid unwanted side effects. 1717 * 1718 * WARNING: this function is only called on the boot CPU. Don't add code 1719 * here that is supposed to run on all CPUs. 1720 */ 1721 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1722 { 1723 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1724 c->extended_cpuid_level = 0; 1725 1726 if (!cpuid_feature()) 1727 identify_cpu_without_cpuid(c); 1728 1729 /* cyrix could have cpuid enabled via c_identify()*/ 1730 if (cpuid_feature()) { 1731 cpu_detect(c); 1732 get_cpu_vendor(c); 1733 intel_unlock_cpuid_leafs(c); 1734 get_cpu_cap(c); 1735 setup_force_cpu_cap(X86_FEATURE_CPUID); 1736 get_cpu_address_sizes(c); 1737 cpu_parse_early_param(); 1738 1739 cpu_init_topology(c); 1740 1741 if (this_cpu->c_early_init) 1742 this_cpu->c_early_init(c); 1743 1744 c->cpu_index = 0; 1745 filter_cpuid_features(c, false); 1746 check_cpufeature_deps(c); 1747 1748 if (this_cpu->c_bsp_init) 1749 this_cpu->c_bsp_init(c); 1750 } else { 1751 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1752 get_cpu_address_sizes(c); 1753 cpu_init_topology(c); 1754 } 1755 1756 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1757 1758 cpu_set_bug_bits(c); 1759 1760 sld_setup(c); 1761 1762 #ifdef CONFIG_X86_32 1763 /* 1764 * Regardless of whether PCID is enumerated, the SDM says 1765 * that it can't be enabled in 32-bit mode. 1766 */ 1767 setup_clear_cpu_cap(X86_FEATURE_PCID); 1768 #endif 1769 1770 /* 1771 * Later in the boot process pgtable_l5_enabled() relies on 1772 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1773 * enabled by this point we need to clear the feature bit to avoid 1774 * false-positives at the later stage. 1775 * 1776 * pgtable_l5_enabled() can be false here for several reasons: 1777 * - 5-level paging is disabled compile-time; 1778 * - it's 32-bit kernel; 1779 * - machine doesn't support 5-level paging; 1780 * - user specified 'no5lvl' in kernel command line. 1781 */ 1782 if (!pgtable_l5_enabled()) 1783 setup_clear_cpu_cap(X86_FEATURE_LA57); 1784 1785 detect_nopl(); 1786 } 1787 1788 void __init init_cpu_devs(void) 1789 { 1790 const struct cpu_dev *const *cdev; 1791 int count = 0; 1792 1793 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1794 const struct cpu_dev *cpudev = *cdev; 1795 1796 if (count >= X86_VENDOR_NUM) 1797 break; 1798 cpu_devs[count] = cpudev; 1799 count++; 1800 } 1801 } 1802 1803 void __init early_cpu_init(void) 1804 { 1805 #ifdef CONFIG_PROCESSOR_SELECT 1806 unsigned int i, j; 1807 1808 pr_info("KERNEL supported cpus:\n"); 1809 #endif 1810 1811 init_cpu_devs(); 1812 1813 #ifdef CONFIG_PROCESSOR_SELECT 1814 for (i = 0; i < X86_VENDOR_NUM && cpu_devs[i]; i++) { 1815 for (j = 0; j < 2; j++) { 1816 if (!cpu_devs[i]->c_ident[j]) 1817 continue; 1818 pr_info(" %s %s\n", cpu_devs[i]->c_vendor, 1819 cpu_devs[i]->c_ident[j]); 1820 } 1821 } 1822 #endif 1823 1824 early_identify_cpu(&boot_cpu_data); 1825 } 1826 1827 static bool detect_null_seg_behavior(void) 1828 { 1829 /* 1830 * Empirically, writing zero to a segment selector on AMD does 1831 * not clear the base, whereas writing zero to a segment 1832 * selector on Intel does clear the base. Intel's behavior 1833 * allows slightly faster context switches in the common case 1834 * where GS is unused by the prev and next threads. 1835 * 1836 * Since neither vendor documents this anywhere that I can see, 1837 * detect it directly instead of hard-coding the choice by 1838 * vendor. 1839 * 1840 * I've designated AMD's behavior as the "bug" because it's 1841 * counterintuitive and less friendly. 1842 */ 1843 1844 unsigned long old_base, tmp; 1845 rdmsrq(MSR_FS_BASE, old_base); 1846 wrmsrq(MSR_FS_BASE, 1); 1847 loadsegment(fs, 0); 1848 rdmsrq(MSR_FS_BASE, tmp); 1849 wrmsrq(MSR_FS_BASE, old_base); 1850 return tmp == 0; 1851 } 1852 1853 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1854 { 1855 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1856 if (!IS_ENABLED(CONFIG_X86_64)) 1857 return; 1858 1859 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1860 return; 1861 1862 /* 1863 * CPUID bit above wasn't set. If this kernel is still running 1864 * as a HV guest, then the HV has decided not to advertize 1865 * that CPUID bit for whatever reason. For example, one 1866 * member of the migration pool might be vulnerable. Which 1867 * means, the bug is present: set the BUG flag and return. 1868 */ 1869 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1870 set_cpu_bug(c, X86_BUG_NULL_SEG); 1871 return; 1872 } 1873 1874 /* 1875 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1876 * 0x18 is the respective family for Hygon. 1877 */ 1878 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1879 detect_null_seg_behavior()) 1880 return; 1881 1882 /* All the remaining ones are affected */ 1883 set_cpu_bug(c, X86_BUG_NULL_SEG); 1884 } 1885 1886 static void generic_identify(struct cpuinfo_x86 *c) 1887 { 1888 c->extended_cpuid_level = 0; 1889 1890 if (!cpuid_feature()) 1891 identify_cpu_without_cpuid(c); 1892 1893 /* cyrix could have cpuid enabled via c_identify()*/ 1894 if (!cpuid_feature()) 1895 return; 1896 1897 cpu_detect(c); 1898 1899 get_cpu_vendor(c); 1900 intel_unlock_cpuid_leafs(c); 1901 get_cpu_cap(c); 1902 1903 get_cpu_address_sizes(c); 1904 1905 get_model_name(c); /* Default name */ 1906 1907 /* 1908 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1909 * systems that run Linux at CPL > 0 may or may not have the 1910 * issue, but, even if they have the issue, there's absolutely 1911 * nothing we can do about it because we can't use the real IRET 1912 * instruction. 1913 * 1914 * NB: For the time being, only 32-bit kernels support 1915 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1916 * whether to apply espfix using paravirt hooks. If any 1917 * non-paravirt system ever shows up that does *not* have the 1918 * ESPFIX issue, we can change this. 1919 */ 1920 #ifdef CONFIG_X86_32 1921 set_cpu_bug(c, X86_BUG_ESPFIX); 1922 #endif 1923 } 1924 1925 /* 1926 * This does the hard work of actually picking apart the CPU stuff... 1927 */ 1928 static void identify_cpu(struct cpuinfo_x86 *c) 1929 { 1930 int i; 1931 1932 c->loops_per_jiffy = loops_per_jiffy; 1933 c->x86_cache_size = 0; 1934 c->x86_vendor = X86_VENDOR_UNKNOWN; 1935 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1936 c->x86_vendor_id[0] = '\0'; /* Unset */ 1937 c->x86_model_id[0] = '\0'; /* Unset */ 1938 #ifdef CONFIG_X86_64 1939 c->x86_clflush_size = 64; 1940 c->x86_phys_bits = 36; 1941 c->x86_virt_bits = 48; 1942 #else 1943 c->cpuid_level = -1; /* CPUID not detected */ 1944 c->x86_clflush_size = 32; 1945 c->x86_phys_bits = 32; 1946 c->x86_virt_bits = 32; 1947 #endif 1948 c->x86_cache_alignment = c->x86_clflush_size; 1949 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1950 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1951 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1952 #endif 1953 1954 generic_identify(c); 1955 1956 cpu_parse_topology(c); 1957 1958 if (this_cpu->c_identify) 1959 this_cpu->c_identify(c); 1960 1961 /* Clear/Set all flags overridden by options, after probe */ 1962 apply_forced_caps(c); 1963 1964 /* 1965 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 1966 * Hygon will clear it in ->c_init() below. 1967 */ 1968 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1969 1970 /* 1971 * Vendor-specific initialization. In this section we 1972 * canonicalize the feature flags, meaning if there are 1973 * features a certain CPU supports which CPUID doesn't 1974 * tell us, CPUID claiming incorrect flags, or other bugs, 1975 * we handle them here. 1976 * 1977 * At the end of this section, c->x86_capability better 1978 * indicate the features this CPU genuinely supports! 1979 */ 1980 if (this_cpu->c_init) 1981 this_cpu->c_init(c); 1982 1983 bus_lock_init(); 1984 1985 /* Disable the PN if appropriate */ 1986 squash_the_stupid_serial_number(c); 1987 1988 /* Set up SMEP/SMAP/UMIP */ 1989 setup_smep(c); 1990 setup_smap(c); 1991 setup_umip(c); 1992 1993 /* Enable FSGSBASE instructions if available. */ 1994 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1995 cr4_set_bits(X86_CR4_FSGSBASE); 1996 elf_hwcap2 |= HWCAP2_FSGSBASE; 1997 } 1998 1999 /* 2000 * The vendor-specific functions might have changed features. 2001 * Now we do "generic changes." 2002 */ 2003 2004 /* Filter out anything that depends on CPUID levels we don't have */ 2005 filter_cpuid_features(c, true); 2006 2007 /* Check for unmet dependencies based on the CPUID dependency table */ 2008 check_cpufeature_deps(c); 2009 2010 /* If the model name is still unset, do table lookup. */ 2011 if (!c->x86_model_id[0]) { 2012 const char *p; 2013 p = table_lookup_model(c); 2014 if (p) 2015 strcpy(c->x86_model_id, p); 2016 else 2017 /* Last resort... */ 2018 sprintf(c->x86_model_id, "%02x/%02x", 2019 c->x86, c->x86_model); 2020 } 2021 2022 x86_init_rdrand(c); 2023 setup_pku(c); 2024 setup_cet(c); 2025 2026 /* 2027 * Clear/Set all flags overridden by options, need do it 2028 * before following smp all cpus cap AND. 2029 */ 2030 apply_forced_caps(c); 2031 2032 /* 2033 * On SMP, boot_cpu_data holds the common feature set between 2034 * all CPUs; so make sure that we indicate which features are 2035 * common between the CPUs. The first time this routine gets 2036 * executed, c == &boot_cpu_data. 2037 */ 2038 if (c != &boot_cpu_data) { 2039 /* AND the already accumulated flags with these */ 2040 for (i = 0; i < NCAPINTS; i++) 2041 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 2042 2043 /* OR, i.e. replicate the bug flags */ 2044 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 2045 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 2046 } 2047 2048 ppin_init(c); 2049 2050 /* Init Machine Check Exception if available. */ 2051 mcheck_cpu_init(c); 2052 2053 numa_add_cpu(smp_processor_id()); 2054 } 2055 2056 /* 2057 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 2058 * on 32-bit kernels: 2059 */ 2060 #ifdef CONFIG_X86_32 2061 void enable_sep_cpu(void) 2062 { 2063 struct tss_struct *tss; 2064 int cpu; 2065 2066 if (!boot_cpu_has(X86_FEATURE_SEP)) 2067 return; 2068 2069 cpu = get_cpu(); 2070 tss = &per_cpu(cpu_tss_rw, cpu); 2071 2072 /* 2073 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 2074 * see the big comment in struct x86_hw_tss's definition. 2075 */ 2076 2077 tss->x86_tss.ss1 = __KERNEL_CS; 2078 wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1); 2079 wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 2080 wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32); 2081 2082 put_cpu(); 2083 } 2084 #endif 2085 2086 static __init void identify_boot_cpu(void) 2087 { 2088 identify_cpu(&boot_cpu_data); 2089 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 2090 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 2091 #ifdef CONFIG_X86_32 2092 enable_sep_cpu(); 2093 #endif 2094 cpu_detect_tlb(&boot_cpu_data); 2095 setup_cr_pinning(); 2096 2097 tsx_init(); 2098 tdx_init(); 2099 lkgs_init(); 2100 } 2101 2102 void identify_secondary_cpu(unsigned int cpu) 2103 { 2104 struct cpuinfo_x86 *c = &cpu_data(cpu); 2105 2106 /* Copy boot_cpu_data only on the first bringup */ 2107 if (!c->initialized) 2108 *c = boot_cpu_data; 2109 c->cpu_index = cpu; 2110 2111 identify_cpu(c); 2112 #ifdef CONFIG_X86_32 2113 enable_sep_cpu(); 2114 #endif 2115 x86_spec_ctrl_setup_ap(); 2116 update_srbds_msr(); 2117 if (boot_cpu_has_bug(X86_BUG_GDS)) 2118 update_gds_msr(); 2119 2120 tsx_ap_init(); 2121 c->initialized = true; 2122 } 2123 2124 void print_cpu_info(struct cpuinfo_x86 *c) 2125 { 2126 const char *vendor = NULL; 2127 2128 if (c->x86_vendor < X86_VENDOR_NUM) { 2129 vendor = this_cpu->c_vendor; 2130 } else { 2131 if (c->cpuid_level >= 0) 2132 vendor = c->x86_vendor_id; 2133 } 2134 2135 if (vendor && !strstr(c->x86_model_id, vendor)) 2136 pr_cont("%s ", vendor); 2137 2138 if (c->x86_model_id[0]) 2139 pr_cont("%s", c->x86_model_id); 2140 else 2141 pr_cont("%d86", c->x86); 2142 2143 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2144 2145 if (c->x86_stepping || c->cpuid_level >= 0) 2146 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2147 else 2148 pr_cont(")\n"); 2149 } 2150 2151 /* 2152 * clearcpuid= and setcpuid= were already parsed in cpu_parse_early_param(). 2153 * These dummy functions prevent them from becoming an environment variable for 2154 * init. 2155 */ 2156 2157 static __init int setup_clearcpuid(char *arg) 2158 { 2159 return 1; 2160 } 2161 __setup("clearcpuid=", setup_clearcpuid); 2162 2163 static __init int setup_setcpuid(char *arg) 2164 { 2165 return 1; 2166 } 2167 __setup("setcpuid=", setup_setcpuid); 2168 2169 DEFINE_PER_CPU_CACHE_HOT(struct task_struct *, current_task) = &init_task; 2170 EXPORT_PER_CPU_SYMBOL(current_task); 2171 EXPORT_PER_CPU_SYMBOL(const_current_task); 2172 2173 DEFINE_PER_CPU_CACHE_HOT(int, __preempt_count) = INIT_PREEMPT_COUNT; 2174 EXPORT_PER_CPU_SYMBOL(__preempt_count); 2175 2176 DEFINE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 2177 2178 #ifdef CONFIG_X86_64 2179 /* 2180 * Note: Do not make this dependant on CONFIG_MITIGATION_CALL_DEPTH_TRACKING 2181 * so that this space is reserved in the hot cache section even when the 2182 * mitigation is disabled. 2183 */ 2184 DEFINE_PER_CPU_CACHE_HOT(u64, __x86_call_depth); 2185 EXPORT_PER_CPU_SYMBOL(__x86_call_depth); 2186 2187 static void wrmsrq_cstar(unsigned long val) 2188 { 2189 /* 2190 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2191 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2192 * guest. Avoid the pointless write on all Intel CPUs. 2193 */ 2194 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2195 wrmsrq(MSR_CSTAR, val); 2196 } 2197 2198 static inline void idt_syscall_init(void) 2199 { 2200 wrmsrq(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2201 2202 if (ia32_enabled()) { 2203 wrmsrq_cstar((unsigned long)entry_SYSCALL_compat); 2204 /* 2205 * This only works on Intel CPUs. 2206 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2207 * This does not cause SYSENTER to jump to the wrong location, because 2208 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2209 */ 2210 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2211 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 2212 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2213 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2214 } else { 2215 wrmsrq_cstar((unsigned long)entry_SYSCALL32_ignore); 2216 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2217 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2218 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2219 } 2220 2221 /* 2222 * Flags to clear on syscall; clear as much as possible 2223 * to minimize user space-kernel interference. 2224 */ 2225 wrmsrq(MSR_SYSCALL_MASK, 2226 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2227 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2228 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2229 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2230 X86_EFLAGS_AC|X86_EFLAGS_ID); 2231 } 2232 2233 /* May not be marked __init: used by software suspend */ 2234 void syscall_init(void) 2235 { 2236 /* The default user and kernel segments */ 2237 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2238 2239 /* 2240 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and 2241 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED 2242 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit 2243 * instruction to return to ring 3 (both sysexit and sysret cause 2244 * #UD when FRED is enabled). 2245 */ 2246 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2247 idt_syscall_init(); 2248 } 2249 #endif /* CONFIG_X86_64 */ 2250 2251 #ifdef CONFIG_STACKPROTECTOR 2252 DEFINE_PER_CPU_CACHE_HOT(unsigned long, __stack_chk_guard); 2253 #ifndef CONFIG_SMP 2254 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2255 #endif 2256 #endif 2257 2258 static void initialize_debug_regs(void) 2259 { 2260 /* Control register first -- to make sure everything is disabled. */ 2261 set_debugreg(DR7_FIXED_1, 7); 2262 set_debugreg(DR6_RESERVED, 6); 2263 /* dr5 and dr4 don't exist */ 2264 set_debugreg(0, 3); 2265 set_debugreg(0, 2); 2266 set_debugreg(0, 1); 2267 set_debugreg(0, 0); 2268 } 2269 2270 #ifdef CONFIG_KGDB 2271 /* 2272 * Restore debug regs if using kgdbwait and you have a kernel debugger 2273 * connection established. 2274 */ 2275 static void dbg_restore_debug_regs(void) 2276 { 2277 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2278 arch_kgdb_ops.correct_hw_break(); 2279 } 2280 #else /* ! CONFIG_KGDB */ 2281 #define dbg_restore_debug_regs() 2282 #endif /* ! CONFIG_KGDB */ 2283 2284 static inline void setup_getcpu(int cpu) 2285 { 2286 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2287 struct desc_struct d = { }; 2288 2289 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2290 wrmsrq(MSR_TSC_AUX, cpudata); 2291 2292 /* Store CPU and node number in limit. */ 2293 d.limit0 = cpudata; 2294 d.limit1 = cpudata >> 16; 2295 2296 d.type = 5; /* RO data, expand down, accessed */ 2297 d.dpl = 3; /* Visible to user code */ 2298 d.s = 1; /* Not a system segment */ 2299 d.p = 1; /* Present */ 2300 d.d = 1; /* 32-bit */ 2301 2302 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2303 } 2304 2305 #ifdef CONFIG_X86_64 2306 static inline void tss_setup_ist(struct tss_struct *tss) 2307 { 2308 /* Set up the per-CPU TSS IST stacks */ 2309 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2310 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2311 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2312 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2313 /* Only mapped when SEV-ES is active */ 2314 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2315 } 2316 #else /* CONFIG_X86_64 */ 2317 static inline void tss_setup_ist(struct tss_struct *tss) { } 2318 #endif /* !CONFIG_X86_64 */ 2319 2320 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2321 { 2322 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2323 2324 #ifdef CONFIG_X86_IOPL_IOPERM 2325 tss->io_bitmap.prev_max = 0; 2326 tss->io_bitmap.prev_sequence = 0; 2327 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2328 /* 2329 * Invalidate the extra array entry past the end of the all 2330 * permission bitmap as required by the hardware. 2331 */ 2332 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2333 #endif 2334 } 2335 2336 /* 2337 * Setup everything needed to handle exceptions from the IDT, including the IST 2338 * exceptions which use paranoid_entry(). 2339 */ 2340 void cpu_init_exception_handling(bool boot_cpu) 2341 { 2342 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2343 int cpu = raw_smp_processor_id(); 2344 2345 /* paranoid_entry() gets the CPU number from the GDT */ 2346 setup_getcpu(cpu); 2347 2348 /* For IDT mode, IST vectors need to be set in TSS. */ 2349 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2350 tss_setup_ist(tss); 2351 tss_setup_io_bitmap(tss); 2352 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2353 2354 load_TR_desc(); 2355 2356 /* GHCB needs to be setup to handle #VC. */ 2357 setup_ghcb(); 2358 2359 if (cpu_feature_enabled(X86_FEATURE_FRED)) { 2360 /* The boot CPU has enabled FRED during early boot */ 2361 if (!boot_cpu) 2362 cpu_init_fred_exceptions(); 2363 2364 cpu_init_fred_rsps(); 2365 } else { 2366 load_current_idt(); 2367 } 2368 } 2369 2370 void __init cpu_init_replace_early_idt(void) 2371 { 2372 if (cpu_feature_enabled(X86_FEATURE_FRED)) 2373 cpu_init_fred_exceptions(); 2374 else 2375 idt_setup_early_pf(); 2376 } 2377 2378 /* 2379 * cpu_init() initializes state that is per-CPU. Some data is already 2380 * initialized (naturally) in the bootstrap process, such as the GDT. We 2381 * reload it nevertheless, this function acts as a 'CPU state barrier', 2382 * nothing should get across. 2383 */ 2384 void cpu_init(void) 2385 { 2386 struct task_struct *cur = current; 2387 int cpu = raw_smp_processor_id(); 2388 2389 #ifdef CONFIG_NUMA 2390 if (this_cpu_read(numa_node) == 0 && 2391 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2392 set_numa_node(early_cpu_to_node(cpu)); 2393 #endif 2394 pr_debug("Initializing CPU#%d\n", cpu); 2395 2396 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2397 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2398 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2399 2400 if (IS_ENABLED(CONFIG_X86_64)) { 2401 loadsegment(fs, 0); 2402 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2403 syscall_init(); 2404 2405 wrmsrq(MSR_FS_BASE, 0); 2406 wrmsrq(MSR_KERNEL_GS_BASE, 0); 2407 barrier(); 2408 2409 x2apic_setup(); 2410 2411 intel_posted_msi_init(); 2412 } 2413 2414 mmgrab(&init_mm); 2415 cur->active_mm = &init_mm; 2416 BUG_ON(cur->mm); 2417 initialize_tlbstate_and_flush(); 2418 enter_lazy_tlb(&init_mm, cur); 2419 2420 /* 2421 * sp0 points to the entry trampoline stack regardless of what task 2422 * is running. 2423 */ 2424 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2425 2426 load_mm_ldt(&init_mm); 2427 2428 initialize_debug_regs(); 2429 dbg_restore_debug_regs(); 2430 2431 doublefault_init_cpu_tss(); 2432 2433 if (is_uv_system()) 2434 uv_cpu_init(); 2435 2436 load_fixmap_gdt(cpu); 2437 } 2438 2439 #ifdef CONFIG_MICROCODE_LATE_LOADING 2440 /** 2441 * store_cpu_caps() - Store a snapshot of CPU capabilities 2442 * @curr_info: Pointer where to store it 2443 * 2444 * Returns: None 2445 */ 2446 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2447 { 2448 /* Reload CPUID max function as it might've changed. */ 2449 curr_info->cpuid_level = cpuid_eax(0); 2450 2451 /* Copy all capability leafs and pick up the synthetic ones. */ 2452 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2453 sizeof(curr_info->x86_capability)); 2454 2455 /* Get the hardware CPUID leafs */ 2456 get_cpu_cap(curr_info); 2457 } 2458 2459 /** 2460 * microcode_check() - Check if any CPU capabilities changed after an update. 2461 * @prev_info: CPU capabilities stored before an update. 2462 * 2463 * The microcode loader calls this upon late microcode load to recheck features, 2464 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2465 * 2466 * Return: None 2467 */ 2468 void microcode_check(struct cpuinfo_x86 *prev_info) 2469 { 2470 struct cpuinfo_x86 curr_info; 2471 2472 perf_check_microcode(); 2473 2474 amd_check_microcode(); 2475 2476 store_cpu_caps(&curr_info); 2477 2478 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2479 sizeof(prev_info->x86_capability))) 2480 return; 2481 2482 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2483 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2484 } 2485 #endif 2486 2487 /* 2488 * Invoked from core CPU hotplug code after hotplug operations 2489 */ 2490 void arch_smt_update(void) 2491 { 2492 /* Handle the speculative execution misfeatures */ 2493 cpu_bugs_smt_update(); 2494 /* Check whether IPI broadcasting can be enabled */ 2495 apic_smt_update(); 2496 } 2497 2498 void __init arch_cpu_finalize_init(void) 2499 { 2500 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 2501 2502 identify_boot_cpu(); 2503 2504 select_idle_routine(); 2505 2506 /* 2507 * identify_boot_cpu() initialized SMT support information, let the 2508 * core code know. 2509 */ 2510 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core); 2511 2512 if (!IS_ENABLED(CONFIG_SMP)) { 2513 pr_info("CPU: "); 2514 print_cpu_info(&boot_cpu_data); 2515 } 2516 2517 cpu_select_mitigations(); 2518 2519 arch_smt_update(); 2520 2521 if (IS_ENABLED(CONFIG_X86_32)) { 2522 /* 2523 * Check whether this is a real i386 which is not longer 2524 * supported and fixup the utsname. 2525 */ 2526 if (boot_cpu_data.x86 < 4) 2527 panic("Kernel requires i486+ for 'invlpg' and other features"); 2528 2529 init_utsname()->machine[1] = 2530 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2531 } 2532 2533 /* 2534 * Must be before alternatives because it might set or clear 2535 * feature bits. 2536 */ 2537 fpu__init_system(); 2538 fpu__init_cpu(); 2539 2540 /* 2541 * Ensure that access to the per CPU representation has the initial 2542 * boot CPU configuration. 2543 */ 2544 *c = boot_cpu_data; 2545 c->initialized = true; 2546 2547 alternative_instructions(); 2548 2549 if (IS_ENABLED(CONFIG_X86_64)) { 2550 unsigned long USER_PTR_MAX = TASK_SIZE_MAX; 2551 2552 /* 2553 * Enable this when LAM is gated on LASS support 2554 if (cpu_feature_enabled(X86_FEATURE_LAM)) 2555 USER_PTR_MAX = (1ul << 63) - PAGE_SIZE; 2556 */ 2557 runtime_const_init(ptr, USER_PTR_MAX); 2558 2559 /* 2560 * Make sure the first 2MB area is not mapped by huge pages 2561 * There are typically fixed size MTRRs in there and overlapping 2562 * MTRRs into large pages causes slow downs. 2563 * 2564 * Right now we don't do that with gbpages because there seems 2565 * very little benefit for that case. 2566 */ 2567 if (!direct_gbpages) 2568 set_memory_4k((unsigned long)__va(0), 1); 2569 } else { 2570 fpu__init_check_bugs(); 2571 } 2572 2573 /* 2574 * This needs to be called before any devices perform DMA 2575 * operations that might use the SWIOTLB bounce buffers. It will 2576 * mark the bounce buffers as decrypted so that their usage will 2577 * not cause "plain-text" data to be decrypted when accessed. It 2578 * must be called after late_time_init() so that Hyper-V x86/x64 2579 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2580 */ 2581 mem_encrypt_init(); 2582 } 2583