1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/mem_encrypt.h> 22 #include <linux/smp.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/pgtable.h> 27 #include <linux/stackprotector.h> 28 #include <linux/utsname.h> 29 30 #include <asm/alternative.h> 31 #include <asm/cmdline.h> 32 #include <asm/perf_event.h> 33 #include <asm/mmu_context.h> 34 #include <asm/doublefault.h> 35 #include <asm/archrandom.h> 36 #include <asm/hypervisor.h> 37 #include <asm/processor.h> 38 #include <asm/tlbflush.h> 39 #include <asm/debugreg.h> 40 #include <asm/sections.h> 41 #include <asm/vsyscall.h> 42 #include <linux/topology.h> 43 #include <linux/cpumask.h> 44 #include <linux/atomic.h> 45 #include <asm/proto.h> 46 #include <asm/setup.h> 47 #include <asm/apic.h> 48 #include <asm/desc.h> 49 #include <asm/fpu/api.h> 50 #include <asm/mtrr.h> 51 #include <asm/hwcap2.h> 52 #include <linux/numa.h> 53 #include <asm/numa.h> 54 #include <asm/asm.h> 55 #include <asm/bugs.h> 56 #include <asm/cpu.h> 57 #include <asm/mce.h> 58 #include <asm/msr.h> 59 #include <asm/cacheinfo.h> 60 #include <asm/memtype.h> 61 #include <asm/microcode.h> 62 #include <asm/intel-family.h> 63 #include <asm/cpu_device_id.h> 64 #include <asm/uv/uv.h> 65 #include <asm/set_memory.h> 66 #include <asm/traps.h> 67 #include <asm/sev.h> 68 69 #include "cpu.h" 70 71 u32 elf_hwcap2 __read_mostly; 72 73 /* Number of siblings per CPU package */ 74 int smp_num_siblings = 1; 75 EXPORT_SYMBOL(smp_num_siblings); 76 77 /* Last level cache ID of each logical CPU */ 78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 79 80 u16 get_llc_id(unsigned int cpu) 81 { 82 return per_cpu(cpu_llc_id, cpu); 83 } 84 EXPORT_SYMBOL_GPL(get_llc_id); 85 86 /* L2 cache ID of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 88 89 static struct ppin_info { 90 int feature; 91 int msr_ppin_ctl; 92 int msr_ppin; 93 } ppin_info[] = { 94 [X86_VENDOR_INTEL] = { 95 .feature = X86_FEATURE_INTEL_PPIN, 96 .msr_ppin_ctl = MSR_PPIN_CTL, 97 .msr_ppin = MSR_PPIN 98 }, 99 [X86_VENDOR_AMD] = { 100 .feature = X86_FEATURE_AMD_PPIN, 101 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 102 .msr_ppin = MSR_AMD_PPIN 103 }, 104 }; 105 106 static const struct x86_cpu_id ppin_cpuids[] = { 107 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 108 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 109 110 /* Legacy models without CPUID enumeration */ 111 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 112 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 113 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 114 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 115 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 116 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 117 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 122 123 {} 124 }; 125 126 static void ppin_init(struct cpuinfo_x86 *c) 127 { 128 const struct x86_cpu_id *id; 129 unsigned long long val; 130 struct ppin_info *info; 131 132 id = x86_match_cpu(ppin_cpuids); 133 if (!id) 134 return; 135 136 /* 137 * Testing the presence of the MSR is not enough. Need to check 138 * that the PPIN_CTL allows reading of the PPIN. 139 */ 140 info = (struct ppin_info *)id->driver_data; 141 142 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 143 goto clear_ppin; 144 145 if ((val & 3UL) == 1UL) { 146 /* PPIN locked in disabled mode */ 147 goto clear_ppin; 148 } 149 150 /* If PPIN is disabled, try to enable */ 151 if (!(val & 2UL)) { 152 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 153 rdmsrl_safe(info->msr_ppin_ctl, &val); 154 } 155 156 /* Is the enable bit set? */ 157 if (val & 2UL) { 158 c->ppin = __rdmsr(info->msr_ppin); 159 set_cpu_cap(c, info->feature); 160 return; 161 } 162 163 clear_ppin: 164 clear_cpu_cap(c, info->feature); 165 } 166 167 static void default_init(struct cpuinfo_x86 *c) 168 { 169 #ifdef CONFIG_X86_64 170 cpu_detect_cache_sizes(c); 171 #else 172 /* Not much we can do here... */ 173 /* Check if at least it has cpuid */ 174 if (c->cpuid_level == -1) { 175 /* No cpuid. It must be an ancient CPU */ 176 if (c->x86 == 4) 177 strcpy(c->x86_model_id, "486"); 178 else if (c->x86 == 3) 179 strcpy(c->x86_model_id, "386"); 180 } 181 #endif 182 } 183 184 static const struct cpu_dev default_cpu = { 185 .c_init = default_init, 186 .c_vendor = "Unknown", 187 .c_x86_vendor = X86_VENDOR_UNKNOWN, 188 }; 189 190 static const struct cpu_dev *this_cpu = &default_cpu; 191 192 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 193 #ifdef CONFIG_X86_64 194 /* 195 * We need valid kernel segments for data and code in long mode too 196 * IRET will check the segment types kkeil 2000/10/28 197 * Also sysret mandates a special GDT layout 198 * 199 * TLS descriptors are currently at a different place compared to i386. 200 * Hopefully nobody expects them at a fixed place (Wine?) 201 */ 202 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 203 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 204 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 205 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 206 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 207 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 208 #else 209 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 210 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 211 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 212 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 213 /* 214 * Segments used for calling PnP BIOS have byte granularity. 215 * They code segments and data segments have fixed 64k limits, 216 * the transfer segment sizes are set at run time. 217 */ 218 /* 32-bit code */ 219 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 220 /* 16-bit code */ 221 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 222 /* 16-bit data */ 223 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 224 /* 16-bit data */ 225 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 226 /* 16-bit data */ 227 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 228 /* 229 * The APM segments have byte granularity and their bases 230 * are set at run time. All have 64k limits. 231 */ 232 /* 32-bit code */ 233 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 234 /* 16-bit code */ 235 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 236 /* data */ 237 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 238 239 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 240 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 241 #endif 242 } }; 243 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 244 245 #ifdef CONFIG_X86_64 246 static int __init x86_nopcid_setup(char *s) 247 { 248 /* nopcid doesn't accept parameters */ 249 if (s) 250 return -EINVAL; 251 252 /* do not emit a message if the feature is not present */ 253 if (!boot_cpu_has(X86_FEATURE_PCID)) 254 return 0; 255 256 setup_clear_cpu_cap(X86_FEATURE_PCID); 257 pr_info("nopcid: PCID feature disabled\n"); 258 return 0; 259 } 260 early_param("nopcid", x86_nopcid_setup); 261 #endif 262 263 static int __init x86_noinvpcid_setup(char *s) 264 { 265 /* noinvpcid doesn't accept parameters */ 266 if (s) 267 return -EINVAL; 268 269 /* do not emit a message if the feature is not present */ 270 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 271 return 0; 272 273 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 274 pr_info("noinvpcid: INVPCID feature disabled\n"); 275 return 0; 276 } 277 early_param("noinvpcid", x86_noinvpcid_setup); 278 279 #ifdef CONFIG_X86_32 280 static int cachesize_override = -1; 281 static int disable_x86_serial_nr = 1; 282 283 static int __init cachesize_setup(char *str) 284 { 285 get_option(&str, &cachesize_override); 286 return 1; 287 } 288 __setup("cachesize=", cachesize_setup); 289 290 /* Standard macro to see if a specific flag is changeable */ 291 static inline int flag_is_changeable_p(u32 flag) 292 { 293 u32 f1, f2; 294 295 /* 296 * Cyrix and IDT cpus allow disabling of CPUID 297 * so the code below may return different results 298 * when it is executed before and after enabling 299 * the CPUID. Add "volatile" to not allow gcc to 300 * optimize the subsequent calls to this function. 301 */ 302 asm volatile ("pushfl \n\t" 303 "pushfl \n\t" 304 "popl %0 \n\t" 305 "movl %0, %1 \n\t" 306 "xorl %2, %0 \n\t" 307 "pushl %0 \n\t" 308 "popfl \n\t" 309 "pushfl \n\t" 310 "popl %0 \n\t" 311 "popfl \n\t" 312 313 : "=&r" (f1), "=&r" (f2) 314 : "ir" (flag)); 315 316 return ((f1^f2) & flag) != 0; 317 } 318 319 /* Probe for the CPUID instruction */ 320 int have_cpuid_p(void) 321 { 322 return flag_is_changeable_p(X86_EFLAGS_ID); 323 } 324 325 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 326 { 327 unsigned long lo, hi; 328 329 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 330 return; 331 332 /* Disable processor serial number: */ 333 334 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 335 lo |= 0x200000; 336 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 337 338 pr_notice("CPU serial number disabled.\n"); 339 clear_cpu_cap(c, X86_FEATURE_PN); 340 341 /* Disabling the serial number may affect the cpuid level */ 342 c->cpuid_level = cpuid_eax(0); 343 } 344 345 static int __init x86_serial_nr_setup(char *s) 346 { 347 disable_x86_serial_nr = 0; 348 return 1; 349 } 350 __setup("serialnumber", x86_serial_nr_setup); 351 #else 352 static inline int flag_is_changeable_p(u32 flag) 353 { 354 return 1; 355 } 356 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 357 { 358 } 359 #endif 360 361 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 362 { 363 if (cpu_has(c, X86_FEATURE_SMEP)) 364 cr4_set_bits(X86_CR4_SMEP); 365 } 366 367 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 368 { 369 unsigned long eflags = native_save_fl(); 370 371 /* This should have been cleared long ago */ 372 BUG_ON(eflags & X86_EFLAGS_AC); 373 374 if (cpu_has(c, X86_FEATURE_SMAP)) 375 cr4_set_bits(X86_CR4_SMAP); 376 } 377 378 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 379 { 380 /* Check the boot processor, plus build option for UMIP. */ 381 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 382 goto out; 383 384 /* Check the current processor's cpuid bits. */ 385 if (!cpu_has(c, X86_FEATURE_UMIP)) 386 goto out; 387 388 cr4_set_bits(X86_CR4_UMIP); 389 390 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 391 392 return; 393 394 out: 395 /* 396 * Make sure UMIP is disabled in case it was enabled in a 397 * previous boot (e.g., via kexec). 398 */ 399 cr4_clear_bits(X86_CR4_UMIP); 400 } 401 402 /* These bits should not change their value after CPU init is finished. */ 403 static const unsigned long cr4_pinned_mask = 404 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 405 X86_CR4_FSGSBASE | X86_CR4_CET; 406 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 407 static unsigned long cr4_pinned_bits __ro_after_init; 408 409 void native_write_cr0(unsigned long val) 410 { 411 unsigned long bits_missing = 0; 412 413 set_register: 414 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 415 416 if (static_branch_likely(&cr_pinning)) { 417 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 418 bits_missing = X86_CR0_WP; 419 val |= bits_missing; 420 goto set_register; 421 } 422 /* Warn after we've set the missing bits. */ 423 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 424 } 425 } 426 EXPORT_SYMBOL(native_write_cr0); 427 428 void __no_profile native_write_cr4(unsigned long val) 429 { 430 unsigned long bits_changed = 0; 431 432 set_register: 433 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 434 435 if (static_branch_likely(&cr_pinning)) { 436 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 437 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 438 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 439 goto set_register; 440 } 441 /* Warn after we've corrected the changed bits. */ 442 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 443 bits_changed); 444 } 445 } 446 #if IS_MODULE(CONFIG_LKDTM) 447 EXPORT_SYMBOL_GPL(native_write_cr4); 448 #endif 449 450 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 451 { 452 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 453 454 lockdep_assert_irqs_disabled(); 455 456 newval = (cr4 & ~clear) | set; 457 if (newval != cr4) { 458 this_cpu_write(cpu_tlbstate.cr4, newval); 459 __write_cr4(newval); 460 } 461 } 462 EXPORT_SYMBOL(cr4_update_irqsoff); 463 464 /* Read the CR4 shadow. */ 465 unsigned long cr4_read_shadow(void) 466 { 467 return this_cpu_read(cpu_tlbstate.cr4); 468 } 469 EXPORT_SYMBOL_GPL(cr4_read_shadow); 470 471 void cr4_init(void) 472 { 473 unsigned long cr4 = __read_cr4(); 474 475 if (boot_cpu_has(X86_FEATURE_PCID)) 476 cr4 |= X86_CR4_PCIDE; 477 if (static_branch_likely(&cr_pinning)) 478 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 479 480 __write_cr4(cr4); 481 482 /* Initialize cr4 shadow for this CPU. */ 483 this_cpu_write(cpu_tlbstate.cr4, cr4); 484 } 485 486 /* 487 * Once CPU feature detection is finished (and boot params have been 488 * parsed), record any of the sensitive CR bits that are set, and 489 * enable CR pinning. 490 */ 491 static void __init setup_cr_pinning(void) 492 { 493 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 494 static_key_enable(&cr_pinning.key); 495 } 496 497 static __init int x86_nofsgsbase_setup(char *arg) 498 { 499 /* Require an exact match without trailing characters. */ 500 if (strlen(arg)) 501 return 0; 502 503 /* Do not emit a message if the feature is not present. */ 504 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 505 return 1; 506 507 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 508 pr_info("FSGSBASE disabled via kernel command line\n"); 509 return 1; 510 } 511 __setup("nofsgsbase", x86_nofsgsbase_setup); 512 513 /* 514 * Protection Keys are not available in 32-bit mode. 515 */ 516 static bool pku_disabled; 517 518 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 519 { 520 if (c == &boot_cpu_data) { 521 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 522 return; 523 /* 524 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 525 * bit to be set. Enforce it. 526 */ 527 setup_force_cpu_cap(X86_FEATURE_OSPKE); 528 529 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 530 return; 531 } 532 533 cr4_set_bits(X86_CR4_PKE); 534 /* Load the default PKRU value */ 535 pkru_write_default(); 536 } 537 538 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 539 static __init int setup_disable_pku(char *arg) 540 { 541 /* 542 * Do not clear the X86_FEATURE_PKU bit. All of the 543 * runtime checks are against OSPKE so clearing the 544 * bit does nothing. 545 * 546 * This way, we will see "pku" in cpuinfo, but not 547 * "ospke", which is exactly what we want. It shows 548 * that the CPU has PKU, but the OS has not enabled it. 549 * This happens to be exactly how a system would look 550 * if we disabled the config option. 551 */ 552 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 553 pku_disabled = true; 554 return 1; 555 } 556 __setup("nopku", setup_disable_pku); 557 #endif 558 559 #ifdef CONFIG_X86_KERNEL_IBT 560 561 __noendbr u64 ibt_save(bool disable) 562 { 563 u64 msr = 0; 564 565 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 566 rdmsrl(MSR_IA32_S_CET, msr); 567 if (disable) 568 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 569 } 570 571 return msr; 572 } 573 574 __noendbr void ibt_restore(u64 save) 575 { 576 u64 msr; 577 578 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 579 rdmsrl(MSR_IA32_S_CET, msr); 580 msr &= ~CET_ENDBR_EN; 581 msr |= (save & CET_ENDBR_EN); 582 wrmsrl(MSR_IA32_S_CET, msr); 583 } 584 } 585 586 #endif 587 588 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 589 { 590 u64 msr = CET_ENDBR_EN; 591 592 if (!HAS_KERNEL_IBT || 593 !cpu_feature_enabled(X86_FEATURE_IBT)) 594 return; 595 596 wrmsrl(MSR_IA32_S_CET, msr); 597 cr4_set_bits(X86_CR4_CET); 598 599 if (!ibt_selftest()) { 600 pr_err("IBT selftest: Failed!\n"); 601 wrmsrl(MSR_IA32_S_CET, 0); 602 setup_clear_cpu_cap(X86_FEATURE_IBT); 603 return; 604 } 605 } 606 607 __noendbr void cet_disable(void) 608 { 609 if (cpu_feature_enabled(X86_FEATURE_IBT)) 610 wrmsrl(MSR_IA32_S_CET, 0); 611 } 612 613 /* 614 * Some CPU features depend on higher CPUID levels, which may not always 615 * be available due to CPUID level capping or broken virtualization 616 * software. Add those features to this table to auto-disable them. 617 */ 618 struct cpuid_dependent_feature { 619 u32 feature; 620 u32 level; 621 }; 622 623 static const struct cpuid_dependent_feature 624 cpuid_dependent_features[] = { 625 { X86_FEATURE_MWAIT, 0x00000005 }, 626 { X86_FEATURE_DCA, 0x00000009 }, 627 { X86_FEATURE_XSAVE, 0x0000000d }, 628 { 0, 0 } 629 }; 630 631 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 632 { 633 const struct cpuid_dependent_feature *df; 634 635 for (df = cpuid_dependent_features; df->feature; df++) { 636 637 if (!cpu_has(c, df->feature)) 638 continue; 639 /* 640 * Note: cpuid_level is set to -1 if unavailable, but 641 * extended_extended_level is set to 0 if unavailable 642 * and the legitimate extended levels are all negative 643 * when signed; hence the weird messing around with 644 * signs here... 645 */ 646 if (!((s32)df->level < 0 ? 647 (u32)df->level > (u32)c->extended_cpuid_level : 648 (s32)df->level > (s32)c->cpuid_level)) 649 continue; 650 651 clear_cpu_cap(c, df->feature); 652 if (!warn) 653 continue; 654 655 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 656 x86_cap_flag(df->feature), df->level); 657 } 658 } 659 660 /* 661 * Naming convention should be: <Name> [(<Codename>)] 662 * This table only is used unless init_<vendor>() below doesn't set it; 663 * in particular, if CPUID levels 0x80000002..4 are supported, this 664 * isn't used 665 */ 666 667 /* Look up CPU names by table lookup. */ 668 static const char *table_lookup_model(struct cpuinfo_x86 *c) 669 { 670 #ifdef CONFIG_X86_32 671 const struct legacy_cpu_model_info *info; 672 673 if (c->x86_model >= 16) 674 return NULL; /* Range check */ 675 676 if (!this_cpu) 677 return NULL; 678 679 info = this_cpu->legacy_models; 680 681 while (info->family) { 682 if (info->family == c->x86) 683 return info->model_names[c->x86_model]; 684 info++; 685 } 686 #endif 687 return NULL; /* Not found */ 688 } 689 690 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 691 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 692 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 693 694 #ifdef CONFIG_X86_32 695 /* The 32-bit entry code needs to find cpu_entry_area. */ 696 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 697 #endif 698 699 /* Load the original GDT from the per-cpu structure */ 700 void load_direct_gdt(int cpu) 701 { 702 struct desc_ptr gdt_descr; 703 704 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 705 gdt_descr.size = GDT_SIZE - 1; 706 load_gdt(&gdt_descr); 707 } 708 EXPORT_SYMBOL_GPL(load_direct_gdt); 709 710 /* Load a fixmap remapping of the per-cpu GDT */ 711 void load_fixmap_gdt(int cpu) 712 { 713 struct desc_ptr gdt_descr; 714 715 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 716 gdt_descr.size = GDT_SIZE - 1; 717 load_gdt(&gdt_descr); 718 } 719 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 720 721 /** 722 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 723 * @cpu: The CPU number for which this is invoked 724 * 725 * Invoked during early boot to switch from early GDT and early per CPU to 726 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 727 * switch is implicit by loading the direct GDT. On 64bit this requires 728 * to update GSBASE. 729 */ 730 void __init switch_gdt_and_percpu_base(int cpu) 731 { 732 load_direct_gdt(cpu); 733 734 #ifdef CONFIG_X86_64 735 /* 736 * No need to load %gs. It is already correct. 737 * 738 * Writing %gs on 64bit would zero GSBASE which would make any per 739 * CPU operation up to the point of the wrmsrl() fault. 740 * 741 * Set GSBASE to the new offset. Until the wrmsrl() happens the 742 * early mapping is still valid. That means the GSBASE update will 743 * lose any prior per CPU data which was not copied over in 744 * setup_per_cpu_areas(). 745 * 746 * This works even with stackprotector enabled because the 747 * per CPU stack canary is 0 in both per CPU areas. 748 */ 749 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 750 #else 751 /* 752 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 753 * it is required to load FS again so that the 'hidden' part is 754 * updated from the new GDT. Up to this point the early per CPU 755 * translation is active. Any content of the early per CPU data 756 * which was not copied over in setup_per_cpu_areas() is lost. 757 */ 758 loadsegment(fs, __KERNEL_PERCPU); 759 #endif 760 } 761 762 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 763 764 static void get_model_name(struct cpuinfo_x86 *c) 765 { 766 unsigned int *v; 767 char *p, *q, *s; 768 769 if (c->extended_cpuid_level < 0x80000004) 770 return; 771 772 v = (unsigned int *)c->x86_model_id; 773 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 774 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 775 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 776 c->x86_model_id[48] = 0; 777 778 /* Trim whitespace */ 779 p = q = s = &c->x86_model_id[0]; 780 781 while (*p == ' ') 782 p++; 783 784 while (*p) { 785 /* Note the last non-whitespace index */ 786 if (!isspace(*p)) 787 s = q; 788 789 *q++ = *p++; 790 } 791 792 *(s + 1) = '\0'; 793 } 794 795 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 796 { 797 unsigned int eax, ebx, ecx, edx; 798 799 c->x86_max_cores = 1; 800 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 801 return; 802 803 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 804 if (eax & 0x1f) 805 c->x86_max_cores = (eax >> 26) + 1; 806 } 807 808 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 809 { 810 unsigned int n, dummy, ebx, ecx, edx, l2size; 811 812 n = c->extended_cpuid_level; 813 814 if (n >= 0x80000005) { 815 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 816 c->x86_cache_size = (ecx>>24) + (edx>>24); 817 #ifdef CONFIG_X86_64 818 /* On K8 L1 TLB is inclusive, so don't count it */ 819 c->x86_tlbsize = 0; 820 #endif 821 } 822 823 if (n < 0x80000006) /* Some chips just has a large L1. */ 824 return; 825 826 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 827 l2size = ecx >> 16; 828 829 #ifdef CONFIG_X86_64 830 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 831 #else 832 /* do processor-specific cache resizing */ 833 if (this_cpu->legacy_cache_size) 834 l2size = this_cpu->legacy_cache_size(c, l2size); 835 836 /* Allow user to override all this if necessary. */ 837 if (cachesize_override != -1) 838 l2size = cachesize_override; 839 840 if (l2size == 0) 841 return; /* Again, no L2 cache is possible */ 842 #endif 843 844 c->x86_cache_size = l2size; 845 } 846 847 u16 __read_mostly tlb_lli_4k[NR_INFO]; 848 u16 __read_mostly tlb_lli_2m[NR_INFO]; 849 u16 __read_mostly tlb_lli_4m[NR_INFO]; 850 u16 __read_mostly tlb_lld_4k[NR_INFO]; 851 u16 __read_mostly tlb_lld_2m[NR_INFO]; 852 u16 __read_mostly tlb_lld_4m[NR_INFO]; 853 u16 __read_mostly tlb_lld_1g[NR_INFO]; 854 855 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 856 { 857 if (this_cpu->c_detect_tlb) 858 this_cpu->c_detect_tlb(c); 859 860 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 861 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 862 tlb_lli_4m[ENTRIES]); 863 864 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 865 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 866 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 867 } 868 869 int detect_ht_early(struct cpuinfo_x86 *c) 870 { 871 #ifdef CONFIG_SMP 872 u32 eax, ebx, ecx, edx; 873 874 if (!cpu_has(c, X86_FEATURE_HT)) 875 return -1; 876 877 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 878 return -1; 879 880 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 881 return -1; 882 883 cpuid(1, &eax, &ebx, &ecx, &edx); 884 885 smp_num_siblings = (ebx & 0xff0000) >> 16; 886 if (smp_num_siblings == 1) 887 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 888 #endif 889 return 0; 890 } 891 892 void detect_ht(struct cpuinfo_x86 *c) 893 { 894 #ifdef CONFIG_SMP 895 int index_msb, core_bits; 896 897 if (detect_ht_early(c) < 0) 898 return; 899 900 index_msb = get_count_order(smp_num_siblings); 901 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 902 903 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 904 905 index_msb = get_count_order(smp_num_siblings); 906 907 core_bits = get_count_order(c->x86_max_cores); 908 909 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 910 ((1 << core_bits) - 1); 911 #endif 912 } 913 914 static void get_cpu_vendor(struct cpuinfo_x86 *c) 915 { 916 char *v = c->x86_vendor_id; 917 int i; 918 919 for (i = 0; i < X86_VENDOR_NUM; i++) { 920 if (!cpu_devs[i]) 921 break; 922 923 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 924 (cpu_devs[i]->c_ident[1] && 925 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 926 927 this_cpu = cpu_devs[i]; 928 c->x86_vendor = this_cpu->c_x86_vendor; 929 return; 930 } 931 } 932 933 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 934 "CPU: Your system may be unstable.\n", v); 935 936 c->x86_vendor = X86_VENDOR_UNKNOWN; 937 this_cpu = &default_cpu; 938 } 939 940 void cpu_detect(struct cpuinfo_x86 *c) 941 { 942 /* Get vendor name */ 943 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 944 (unsigned int *)&c->x86_vendor_id[0], 945 (unsigned int *)&c->x86_vendor_id[8], 946 (unsigned int *)&c->x86_vendor_id[4]); 947 948 c->x86 = 4; 949 /* Intel-defined flags: level 0x00000001 */ 950 if (c->cpuid_level >= 0x00000001) { 951 u32 junk, tfms, cap0, misc; 952 953 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 954 c->x86 = x86_family(tfms); 955 c->x86_model = x86_model(tfms); 956 c->x86_stepping = x86_stepping(tfms); 957 958 if (cap0 & (1<<19)) { 959 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 960 c->x86_cache_alignment = c->x86_clflush_size; 961 } 962 } 963 } 964 965 static void apply_forced_caps(struct cpuinfo_x86 *c) 966 { 967 int i; 968 969 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 970 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 971 c->x86_capability[i] |= cpu_caps_set[i]; 972 } 973 } 974 975 static void init_speculation_control(struct cpuinfo_x86 *c) 976 { 977 /* 978 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 979 * and they also have a different bit for STIBP support. Also, 980 * a hypervisor might have set the individual AMD bits even on 981 * Intel CPUs, for finer-grained selection of what's available. 982 */ 983 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 984 set_cpu_cap(c, X86_FEATURE_IBRS); 985 set_cpu_cap(c, X86_FEATURE_IBPB); 986 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 987 } 988 989 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 990 set_cpu_cap(c, X86_FEATURE_STIBP); 991 992 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 993 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 994 set_cpu_cap(c, X86_FEATURE_SSBD); 995 996 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 997 set_cpu_cap(c, X86_FEATURE_IBRS); 998 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 999 } 1000 1001 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 1002 set_cpu_cap(c, X86_FEATURE_IBPB); 1003 1004 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 1005 set_cpu_cap(c, X86_FEATURE_STIBP); 1006 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1007 } 1008 1009 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1010 set_cpu_cap(c, X86_FEATURE_SSBD); 1011 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1012 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1013 } 1014 } 1015 1016 void get_cpu_cap(struct cpuinfo_x86 *c) 1017 { 1018 u32 eax, ebx, ecx, edx; 1019 1020 /* Intel-defined flags: level 0x00000001 */ 1021 if (c->cpuid_level >= 0x00000001) { 1022 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1023 1024 c->x86_capability[CPUID_1_ECX] = ecx; 1025 c->x86_capability[CPUID_1_EDX] = edx; 1026 } 1027 1028 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1029 if (c->cpuid_level >= 0x00000006) 1030 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1031 1032 /* Additional Intel-defined flags: level 0x00000007 */ 1033 if (c->cpuid_level >= 0x00000007) { 1034 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1035 c->x86_capability[CPUID_7_0_EBX] = ebx; 1036 c->x86_capability[CPUID_7_ECX] = ecx; 1037 c->x86_capability[CPUID_7_EDX] = edx; 1038 1039 /* Check valid sub-leaf index before accessing it */ 1040 if (eax >= 1) { 1041 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1042 c->x86_capability[CPUID_7_1_EAX] = eax; 1043 } 1044 } 1045 1046 /* Extended state features: level 0x0000000d */ 1047 if (c->cpuid_level >= 0x0000000d) { 1048 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1049 1050 c->x86_capability[CPUID_D_1_EAX] = eax; 1051 } 1052 1053 /* AMD-defined flags: level 0x80000001 */ 1054 eax = cpuid_eax(0x80000000); 1055 c->extended_cpuid_level = eax; 1056 1057 if ((eax & 0xffff0000) == 0x80000000) { 1058 if (eax >= 0x80000001) { 1059 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1060 1061 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1062 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1063 } 1064 } 1065 1066 if (c->extended_cpuid_level >= 0x80000007) { 1067 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1068 1069 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1070 c->x86_power = edx; 1071 } 1072 1073 if (c->extended_cpuid_level >= 0x80000008) { 1074 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1075 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1076 } 1077 1078 if (c->extended_cpuid_level >= 0x8000000a) 1079 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1080 1081 if (c->extended_cpuid_level >= 0x8000001f) 1082 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1083 1084 if (c->extended_cpuid_level >= 0x80000021) 1085 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1086 1087 init_scattered_cpuid_features(c); 1088 init_speculation_control(c); 1089 1090 /* 1091 * Clear/Set all flags overridden by options, after probe. 1092 * This needs to happen each time we re-probe, which may happen 1093 * several times during CPU initialization. 1094 */ 1095 apply_forced_caps(c); 1096 } 1097 1098 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1099 { 1100 u32 eax, ebx, ecx, edx; 1101 1102 if (c->extended_cpuid_level >= 0x80000008) { 1103 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1104 1105 c->x86_virt_bits = (eax >> 8) & 0xff; 1106 c->x86_phys_bits = eax & 0xff; 1107 } 1108 #ifdef CONFIG_X86_32 1109 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 1110 c->x86_phys_bits = 36; 1111 #endif 1112 c->x86_cache_bits = c->x86_phys_bits; 1113 } 1114 1115 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1116 { 1117 #ifdef CONFIG_X86_32 1118 int i; 1119 1120 /* 1121 * First of all, decide if this is a 486 or higher 1122 * It's a 486 if we can modify the AC flag 1123 */ 1124 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1125 c->x86 = 4; 1126 else 1127 c->x86 = 3; 1128 1129 for (i = 0; i < X86_VENDOR_NUM; i++) 1130 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1131 c->x86_vendor_id[0] = 0; 1132 cpu_devs[i]->c_identify(c); 1133 if (c->x86_vendor_id[0]) { 1134 get_cpu_vendor(c); 1135 break; 1136 } 1137 } 1138 #endif 1139 } 1140 1141 #define NO_SPECULATION BIT(0) 1142 #define NO_MELTDOWN BIT(1) 1143 #define NO_SSB BIT(2) 1144 #define NO_L1TF BIT(3) 1145 #define NO_MDS BIT(4) 1146 #define MSBDS_ONLY BIT(5) 1147 #define NO_SWAPGS BIT(6) 1148 #define NO_ITLB_MULTIHIT BIT(7) 1149 #define NO_SPECTRE_V2 BIT(8) 1150 #define NO_MMIO BIT(9) 1151 #define NO_EIBRS_PBRSB BIT(10) 1152 1153 #define VULNWL(vendor, family, model, whitelist) \ 1154 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1155 1156 #define VULNWL_INTEL(model, whitelist) \ 1157 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1158 1159 #define VULNWL_AMD(family, whitelist) \ 1160 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1161 1162 #define VULNWL_HYGON(family, whitelist) \ 1163 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1164 1165 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1166 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1167 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1168 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1169 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1170 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1171 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1172 1173 /* Intel Family 6 */ 1174 VULNWL_INTEL(TIGERLAKE, NO_MMIO), 1175 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), 1176 VULNWL_INTEL(ALDERLAKE, NO_MMIO), 1177 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), 1178 1179 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1180 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1181 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1182 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1183 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1184 1185 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1186 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1187 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1188 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1189 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1190 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1191 1192 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1193 1194 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1195 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1196 1197 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1198 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1199 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1200 1201 /* 1202 * Technically, swapgs isn't serializing on AMD (despite it previously 1203 * being documented as such in the APM). But according to AMD, %gs is 1204 * updated non-speculatively, and the issuing of %gs-relative memory 1205 * operands will be blocked until the %gs update completes, which is 1206 * good enough for our purposes. 1207 */ 1208 1209 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), 1210 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1211 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1212 1213 /* AMD Family 0xf - 0x12 */ 1214 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1215 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1216 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1217 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1218 1219 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1220 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1221 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1222 1223 /* Zhaoxin Family 7 */ 1224 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1225 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1226 {} 1227 }; 1228 1229 #define VULNBL(vendor, family, model, blacklist) \ 1230 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1231 1232 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1233 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1234 INTEL_FAM6_##model, steppings, \ 1235 X86_FEATURE_ANY, issues) 1236 1237 #define VULNBL_AMD(family, blacklist) \ 1238 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1239 1240 #define VULNBL_HYGON(family, blacklist) \ 1241 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1242 1243 #define SRBDS BIT(0) 1244 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1245 #define MMIO BIT(1) 1246 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1247 #define MMIO_SBDS BIT(2) 1248 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1249 #define RETBLEED BIT(3) 1250 /* CPU is affected by SMT (cross-thread) return predictions */ 1251 #define SMT_RSB BIT(4) 1252 /* CPU is affected by SRSO */ 1253 #define SRSO BIT(5) 1254 /* CPU is affected by GDS */ 1255 #define GDS BIT(6) 1256 1257 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1258 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1259 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1260 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1261 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1262 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), 1263 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), 1264 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1265 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), 1266 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1267 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1268 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1269 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1270 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS), 1271 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS), 1272 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), 1273 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1274 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), 1275 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), 1276 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1277 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), 1278 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1279 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS), 1280 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS), 1281 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1282 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1283 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1284 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO), 1285 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1286 1287 VULNBL_AMD(0x15, RETBLEED), 1288 VULNBL_AMD(0x16, RETBLEED), 1289 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), 1290 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB), 1291 VULNBL_AMD(0x19, SRSO), 1292 {} 1293 }; 1294 1295 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1296 { 1297 const struct x86_cpu_id *m = x86_match_cpu(table); 1298 1299 return m && !!(m->driver_data & which); 1300 } 1301 1302 u64 x86_read_arch_cap_msr(void) 1303 { 1304 u64 ia32_cap = 0; 1305 1306 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1307 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1308 1309 return ia32_cap; 1310 } 1311 1312 static bool arch_cap_mmio_immune(u64 ia32_cap) 1313 { 1314 return (ia32_cap & ARCH_CAP_FBSDP_NO && 1315 ia32_cap & ARCH_CAP_PSDP_NO && 1316 ia32_cap & ARCH_CAP_SBDR_SSDP_NO); 1317 } 1318 1319 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1320 { 1321 u64 ia32_cap = x86_read_arch_cap_msr(); 1322 1323 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1324 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1325 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1326 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1327 1328 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1329 return; 1330 1331 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1332 1333 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1334 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1335 1336 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1337 !(ia32_cap & ARCH_CAP_SSB_NO) && 1338 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1339 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1340 1341 /* 1342 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1343 * flag and protect from vendor-specific bugs via the whitelist. 1344 */ 1345 if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { 1346 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1347 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1348 !(ia32_cap & ARCH_CAP_PBRSB_NO)) 1349 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1350 } 1351 1352 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1353 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1354 setup_force_cpu_bug(X86_BUG_MDS); 1355 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1356 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1357 } 1358 1359 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1360 setup_force_cpu_bug(X86_BUG_SWAPGS); 1361 1362 /* 1363 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1364 * - TSX is supported or 1365 * - TSX_CTRL is present 1366 * 1367 * TSX_CTRL check is needed for cases when TSX could be disabled before 1368 * the kernel boot e.g. kexec. 1369 * TSX_CTRL check alone is not sufficient for cases when the microcode 1370 * update is not present or running as guest that don't get TSX_CTRL. 1371 */ 1372 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1373 (cpu_has(c, X86_FEATURE_RTM) || 1374 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1375 setup_force_cpu_bug(X86_BUG_TAA); 1376 1377 /* 1378 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1379 * in the vulnerability blacklist. 1380 * 1381 * Some of the implications and mitigation of Shared Buffers Data 1382 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1383 * SRBDS. 1384 */ 1385 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1386 cpu_has(c, X86_FEATURE_RDSEED)) && 1387 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1388 setup_force_cpu_bug(X86_BUG_SRBDS); 1389 1390 /* 1391 * Processor MMIO Stale Data bug enumeration 1392 * 1393 * Affected CPU list is generally enough to enumerate the vulnerability, 1394 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1395 * not want the guest to enumerate the bug. 1396 * 1397 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1398 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1399 */ 1400 if (!arch_cap_mmio_immune(ia32_cap)) { 1401 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1402 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1403 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1404 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1405 } 1406 1407 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1408 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA)) 1409 setup_force_cpu_bug(X86_BUG_RETBLEED); 1410 } 1411 1412 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1413 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1414 1415 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1416 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1417 setup_force_cpu_bug(X86_BUG_SRSO); 1418 } 1419 1420 /* 1421 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1422 * an affected processor, the VMM may have disabled the use of GATHER by 1423 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1424 * which means that AVX will be disabled. 1425 */ 1426 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) && 1427 boot_cpu_has(X86_FEATURE_AVX)) 1428 setup_force_cpu_bug(X86_BUG_GDS); 1429 1430 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1431 return; 1432 1433 /* Rogue Data Cache Load? No! */ 1434 if (ia32_cap & ARCH_CAP_RDCL_NO) 1435 return; 1436 1437 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1438 1439 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1440 return; 1441 1442 setup_force_cpu_bug(X86_BUG_L1TF); 1443 } 1444 1445 /* 1446 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1447 * unfortunately, that's not true in practice because of early VIA 1448 * chips and (more importantly) broken virtualizers that are not easy 1449 * to detect. In the latter case it doesn't even *fail* reliably, so 1450 * probing for it doesn't even work. Disable it completely on 32-bit 1451 * unless we can find a reliable way to detect all the broken cases. 1452 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1453 */ 1454 static void detect_nopl(void) 1455 { 1456 #ifdef CONFIG_X86_32 1457 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1458 #else 1459 setup_force_cpu_cap(X86_FEATURE_NOPL); 1460 #endif 1461 } 1462 1463 /* 1464 * We parse cpu parameters early because fpu__init_system() is executed 1465 * before parse_early_param(). 1466 */ 1467 static void __init cpu_parse_early_param(void) 1468 { 1469 char arg[128]; 1470 char *argptr = arg, *opt; 1471 int arglen, taint = 0; 1472 1473 #ifdef CONFIG_X86_32 1474 if (cmdline_find_option_bool(boot_command_line, "no387")) 1475 #ifdef CONFIG_MATH_EMULATION 1476 setup_clear_cpu_cap(X86_FEATURE_FPU); 1477 #else 1478 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1479 #endif 1480 1481 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1482 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1483 #endif 1484 1485 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1486 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1487 1488 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1489 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1490 1491 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1492 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1493 1494 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1495 if (arglen <= 0) 1496 return; 1497 1498 pr_info("Clearing CPUID bits:"); 1499 1500 while (argptr) { 1501 bool found __maybe_unused = false; 1502 unsigned int bit; 1503 1504 opt = strsep(&argptr, ","); 1505 1506 /* 1507 * Handle naked numbers first for feature flags which don't 1508 * have names. 1509 */ 1510 if (!kstrtouint(opt, 10, &bit)) { 1511 if (bit < NCAPINTS * 32) { 1512 1513 /* empty-string, i.e., ""-defined feature flags */ 1514 if (!x86_cap_flags[bit]) 1515 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1516 else 1517 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1518 1519 setup_clear_cpu_cap(bit); 1520 taint++; 1521 } 1522 /* 1523 * The assumption is that there are no feature names with only 1524 * numbers in the name thus go to the next argument. 1525 */ 1526 continue; 1527 } 1528 1529 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1530 if (!x86_cap_flag(bit)) 1531 continue; 1532 1533 if (strcmp(x86_cap_flag(bit), opt)) 1534 continue; 1535 1536 pr_cont(" %s", opt); 1537 setup_clear_cpu_cap(bit); 1538 taint++; 1539 found = true; 1540 break; 1541 } 1542 1543 if (!found) 1544 pr_cont(" (unknown: %s)", opt); 1545 } 1546 pr_cont("\n"); 1547 1548 if (taint) 1549 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1550 } 1551 1552 /* 1553 * Do minimum CPU detection early. 1554 * Fields really needed: vendor, cpuid_level, family, model, mask, 1555 * cache alignment. 1556 * The others are not touched to avoid unwanted side effects. 1557 * 1558 * WARNING: this function is only called on the boot CPU. Don't add code 1559 * here that is supposed to run on all CPUs. 1560 */ 1561 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1562 { 1563 #ifdef CONFIG_X86_64 1564 c->x86_clflush_size = 64; 1565 c->x86_phys_bits = 36; 1566 c->x86_virt_bits = 48; 1567 #else 1568 c->x86_clflush_size = 32; 1569 c->x86_phys_bits = 32; 1570 c->x86_virt_bits = 32; 1571 #endif 1572 c->x86_cache_alignment = c->x86_clflush_size; 1573 1574 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1575 c->extended_cpuid_level = 0; 1576 1577 if (!have_cpuid_p()) 1578 identify_cpu_without_cpuid(c); 1579 1580 /* cyrix could have cpuid enabled via c_identify()*/ 1581 if (have_cpuid_p()) { 1582 cpu_detect(c); 1583 get_cpu_vendor(c); 1584 get_cpu_cap(c); 1585 get_cpu_address_sizes(c); 1586 setup_force_cpu_cap(X86_FEATURE_CPUID); 1587 cpu_parse_early_param(); 1588 1589 if (this_cpu->c_early_init) 1590 this_cpu->c_early_init(c); 1591 1592 c->cpu_index = 0; 1593 filter_cpuid_features(c, false); 1594 1595 if (this_cpu->c_bsp_init) 1596 this_cpu->c_bsp_init(c); 1597 } else { 1598 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1599 } 1600 1601 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1602 1603 cpu_set_bug_bits(c); 1604 1605 sld_setup(c); 1606 1607 #ifdef CONFIG_X86_32 1608 /* 1609 * Regardless of whether PCID is enumerated, the SDM says 1610 * that it can't be enabled in 32-bit mode. 1611 */ 1612 setup_clear_cpu_cap(X86_FEATURE_PCID); 1613 #endif 1614 1615 /* 1616 * Later in the boot process pgtable_l5_enabled() relies on 1617 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1618 * enabled by this point we need to clear the feature bit to avoid 1619 * false-positives at the later stage. 1620 * 1621 * pgtable_l5_enabled() can be false here for several reasons: 1622 * - 5-level paging is disabled compile-time; 1623 * - it's 32-bit kernel; 1624 * - machine doesn't support 5-level paging; 1625 * - user specified 'no5lvl' in kernel command line. 1626 */ 1627 if (!pgtable_l5_enabled()) 1628 setup_clear_cpu_cap(X86_FEATURE_LA57); 1629 1630 detect_nopl(); 1631 } 1632 1633 void __init early_cpu_init(void) 1634 { 1635 const struct cpu_dev *const *cdev; 1636 int count = 0; 1637 1638 #ifdef CONFIG_PROCESSOR_SELECT 1639 pr_info("KERNEL supported cpus:\n"); 1640 #endif 1641 1642 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1643 const struct cpu_dev *cpudev = *cdev; 1644 1645 if (count >= X86_VENDOR_NUM) 1646 break; 1647 cpu_devs[count] = cpudev; 1648 count++; 1649 1650 #ifdef CONFIG_PROCESSOR_SELECT 1651 { 1652 unsigned int j; 1653 1654 for (j = 0; j < 2; j++) { 1655 if (!cpudev->c_ident[j]) 1656 continue; 1657 pr_info(" %s %s\n", cpudev->c_vendor, 1658 cpudev->c_ident[j]); 1659 } 1660 } 1661 #endif 1662 } 1663 early_identify_cpu(&boot_cpu_data); 1664 } 1665 1666 static bool detect_null_seg_behavior(void) 1667 { 1668 /* 1669 * Empirically, writing zero to a segment selector on AMD does 1670 * not clear the base, whereas writing zero to a segment 1671 * selector on Intel does clear the base. Intel's behavior 1672 * allows slightly faster context switches in the common case 1673 * where GS is unused by the prev and next threads. 1674 * 1675 * Since neither vendor documents this anywhere that I can see, 1676 * detect it directly instead of hard-coding the choice by 1677 * vendor. 1678 * 1679 * I've designated AMD's behavior as the "bug" because it's 1680 * counterintuitive and less friendly. 1681 */ 1682 1683 unsigned long old_base, tmp; 1684 rdmsrl(MSR_FS_BASE, old_base); 1685 wrmsrl(MSR_FS_BASE, 1); 1686 loadsegment(fs, 0); 1687 rdmsrl(MSR_FS_BASE, tmp); 1688 wrmsrl(MSR_FS_BASE, old_base); 1689 return tmp == 0; 1690 } 1691 1692 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1693 { 1694 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1695 if (!IS_ENABLED(CONFIG_X86_64)) 1696 return; 1697 1698 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1699 return; 1700 1701 /* 1702 * CPUID bit above wasn't set. If this kernel is still running 1703 * as a HV guest, then the HV has decided not to advertize 1704 * that CPUID bit for whatever reason. For example, one 1705 * member of the migration pool might be vulnerable. Which 1706 * means, the bug is present: set the BUG flag and return. 1707 */ 1708 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1709 set_cpu_bug(c, X86_BUG_NULL_SEG); 1710 return; 1711 } 1712 1713 /* 1714 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1715 * 0x18 is the respective family for Hygon. 1716 */ 1717 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1718 detect_null_seg_behavior()) 1719 return; 1720 1721 /* All the remaining ones are affected */ 1722 set_cpu_bug(c, X86_BUG_NULL_SEG); 1723 } 1724 1725 static void generic_identify(struct cpuinfo_x86 *c) 1726 { 1727 c->extended_cpuid_level = 0; 1728 1729 if (!have_cpuid_p()) 1730 identify_cpu_without_cpuid(c); 1731 1732 /* cyrix could have cpuid enabled via c_identify()*/ 1733 if (!have_cpuid_p()) 1734 return; 1735 1736 cpu_detect(c); 1737 1738 get_cpu_vendor(c); 1739 1740 get_cpu_cap(c); 1741 1742 get_cpu_address_sizes(c); 1743 1744 if (c->cpuid_level >= 0x00000001) { 1745 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1746 #ifdef CONFIG_X86_32 1747 # ifdef CONFIG_SMP 1748 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1749 # else 1750 c->apicid = c->initial_apicid; 1751 # endif 1752 #endif 1753 c->phys_proc_id = c->initial_apicid; 1754 } 1755 1756 get_model_name(c); /* Default name */ 1757 1758 /* 1759 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1760 * systems that run Linux at CPL > 0 may or may not have the 1761 * issue, but, even if they have the issue, there's absolutely 1762 * nothing we can do about it because we can't use the real IRET 1763 * instruction. 1764 * 1765 * NB: For the time being, only 32-bit kernels support 1766 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1767 * whether to apply espfix using paravirt hooks. If any 1768 * non-paravirt system ever shows up that does *not* have the 1769 * ESPFIX issue, we can change this. 1770 */ 1771 #ifdef CONFIG_X86_32 1772 set_cpu_bug(c, X86_BUG_ESPFIX); 1773 #endif 1774 } 1775 1776 /* 1777 * Validate that ACPI/mptables have the same information about the 1778 * effective APIC id and update the package map. 1779 */ 1780 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1781 { 1782 #ifdef CONFIG_SMP 1783 unsigned int apicid, cpu = smp_processor_id(); 1784 1785 apicid = apic->cpu_present_to_apicid(cpu); 1786 1787 if (apicid != c->apicid) { 1788 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1789 cpu, apicid, c->initial_apicid); 1790 } 1791 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1792 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1793 #else 1794 c->logical_proc_id = 0; 1795 #endif 1796 } 1797 1798 /* 1799 * This does the hard work of actually picking apart the CPU stuff... 1800 */ 1801 static void identify_cpu(struct cpuinfo_x86 *c) 1802 { 1803 int i; 1804 1805 c->loops_per_jiffy = loops_per_jiffy; 1806 c->x86_cache_size = 0; 1807 c->x86_vendor = X86_VENDOR_UNKNOWN; 1808 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1809 c->x86_vendor_id[0] = '\0'; /* Unset */ 1810 c->x86_model_id[0] = '\0'; /* Unset */ 1811 c->x86_max_cores = 1; 1812 c->x86_coreid_bits = 0; 1813 c->cu_id = 0xff; 1814 #ifdef CONFIG_X86_64 1815 c->x86_clflush_size = 64; 1816 c->x86_phys_bits = 36; 1817 c->x86_virt_bits = 48; 1818 #else 1819 c->cpuid_level = -1; /* CPUID not detected */ 1820 c->x86_clflush_size = 32; 1821 c->x86_phys_bits = 32; 1822 c->x86_virt_bits = 32; 1823 #endif 1824 c->x86_cache_alignment = c->x86_clflush_size; 1825 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1826 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1827 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1828 #endif 1829 1830 generic_identify(c); 1831 1832 if (this_cpu->c_identify) 1833 this_cpu->c_identify(c); 1834 1835 /* Clear/Set all flags overridden by options, after probe */ 1836 apply_forced_caps(c); 1837 1838 #ifdef CONFIG_X86_64 1839 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1840 #endif 1841 1842 /* 1843 * Vendor-specific initialization. In this section we 1844 * canonicalize the feature flags, meaning if there are 1845 * features a certain CPU supports which CPUID doesn't 1846 * tell us, CPUID claiming incorrect flags, or other bugs, 1847 * we handle them here. 1848 * 1849 * At the end of this section, c->x86_capability better 1850 * indicate the features this CPU genuinely supports! 1851 */ 1852 if (this_cpu->c_init) 1853 this_cpu->c_init(c); 1854 1855 /* Disable the PN if appropriate */ 1856 squash_the_stupid_serial_number(c); 1857 1858 /* Set up SMEP/SMAP/UMIP */ 1859 setup_smep(c); 1860 setup_smap(c); 1861 setup_umip(c); 1862 1863 /* Enable FSGSBASE instructions if available. */ 1864 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1865 cr4_set_bits(X86_CR4_FSGSBASE); 1866 elf_hwcap2 |= HWCAP2_FSGSBASE; 1867 } 1868 1869 /* 1870 * The vendor-specific functions might have changed features. 1871 * Now we do "generic changes." 1872 */ 1873 1874 /* Filter out anything that depends on CPUID levels we don't have */ 1875 filter_cpuid_features(c, true); 1876 1877 /* If the model name is still unset, do table lookup. */ 1878 if (!c->x86_model_id[0]) { 1879 const char *p; 1880 p = table_lookup_model(c); 1881 if (p) 1882 strcpy(c->x86_model_id, p); 1883 else 1884 /* Last resort... */ 1885 sprintf(c->x86_model_id, "%02x/%02x", 1886 c->x86, c->x86_model); 1887 } 1888 1889 #ifdef CONFIG_X86_64 1890 detect_ht(c); 1891 #endif 1892 1893 x86_init_rdrand(c); 1894 setup_pku(c); 1895 setup_cet(c); 1896 1897 /* 1898 * Clear/Set all flags overridden by options, need do it 1899 * before following smp all cpus cap AND. 1900 */ 1901 apply_forced_caps(c); 1902 1903 /* 1904 * On SMP, boot_cpu_data holds the common feature set between 1905 * all CPUs; so make sure that we indicate which features are 1906 * common between the CPUs. The first time this routine gets 1907 * executed, c == &boot_cpu_data. 1908 */ 1909 if (c != &boot_cpu_data) { 1910 /* AND the already accumulated flags with these */ 1911 for (i = 0; i < NCAPINTS; i++) 1912 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1913 1914 /* OR, i.e. replicate the bug flags */ 1915 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1916 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1917 } 1918 1919 ppin_init(c); 1920 1921 /* Init Machine Check Exception if available. */ 1922 mcheck_cpu_init(c); 1923 1924 select_idle_routine(c); 1925 1926 #ifdef CONFIG_NUMA 1927 numa_add_cpu(smp_processor_id()); 1928 #endif 1929 } 1930 1931 /* 1932 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1933 * on 32-bit kernels: 1934 */ 1935 #ifdef CONFIG_X86_32 1936 void enable_sep_cpu(void) 1937 { 1938 struct tss_struct *tss; 1939 int cpu; 1940 1941 if (!boot_cpu_has(X86_FEATURE_SEP)) 1942 return; 1943 1944 cpu = get_cpu(); 1945 tss = &per_cpu(cpu_tss_rw, cpu); 1946 1947 /* 1948 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1949 * see the big comment in struct x86_hw_tss's definition. 1950 */ 1951 1952 tss->x86_tss.ss1 = __KERNEL_CS; 1953 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1954 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1955 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1956 1957 put_cpu(); 1958 } 1959 #endif 1960 1961 void __init identify_boot_cpu(void) 1962 { 1963 identify_cpu(&boot_cpu_data); 1964 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1965 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1966 #ifdef CONFIG_X86_32 1967 enable_sep_cpu(); 1968 #endif 1969 cpu_detect_tlb(&boot_cpu_data); 1970 setup_cr_pinning(); 1971 1972 tsx_init(); 1973 lkgs_init(); 1974 } 1975 1976 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1977 { 1978 BUG_ON(c == &boot_cpu_data); 1979 identify_cpu(c); 1980 #ifdef CONFIG_X86_32 1981 enable_sep_cpu(); 1982 #endif 1983 validate_apic_and_package_id(c); 1984 x86_spec_ctrl_setup_ap(); 1985 update_srbds_msr(); 1986 if (boot_cpu_has_bug(X86_BUG_GDS)) 1987 update_gds_msr(); 1988 1989 tsx_ap_init(); 1990 } 1991 1992 void print_cpu_info(struct cpuinfo_x86 *c) 1993 { 1994 const char *vendor = NULL; 1995 1996 if (c->x86_vendor < X86_VENDOR_NUM) { 1997 vendor = this_cpu->c_vendor; 1998 } else { 1999 if (c->cpuid_level >= 0) 2000 vendor = c->x86_vendor_id; 2001 } 2002 2003 if (vendor && !strstr(c->x86_model_id, vendor)) 2004 pr_cont("%s ", vendor); 2005 2006 if (c->x86_model_id[0]) 2007 pr_cont("%s", c->x86_model_id); 2008 else 2009 pr_cont("%d86", c->x86); 2010 2011 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2012 2013 if (c->x86_stepping || c->cpuid_level >= 0) 2014 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2015 else 2016 pr_cont(")\n"); 2017 } 2018 2019 /* 2020 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 2021 * function prevents it from becoming an environment variable for init. 2022 */ 2023 static __init int setup_clearcpuid(char *arg) 2024 { 2025 return 1; 2026 } 2027 __setup("clearcpuid=", setup_clearcpuid); 2028 2029 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = { 2030 .current_task = &init_task, 2031 .preempt_count = INIT_PREEMPT_COUNT, 2032 .top_of_stack = TOP_OF_INIT_STACK, 2033 }; 2034 EXPORT_PER_CPU_SYMBOL(pcpu_hot); 2035 2036 #ifdef CONFIG_X86_64 2037 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 2038 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 2039 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2040 2041 static void wrmsrl_cstar(unsigned long val) 2042 { 2043 /* 2044 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2045 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2046 * guest. Avoid the pointless write on all Intel CPUs. 2047 */ 2048 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2049 wrmsrl(MSR_CSTAR, val); 2050 } 2051 2052 /* May not be marked __init: used by software suspend */ 2053 void syscall_init(void) 2054 { 2055 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2056 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2057 2058 #ifdef CONFIG_IA32_EMULATION 2059 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2060 /* 2061 * This only works on Intel CPUs. 2062 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2063 * This does not cause SYSENTER to jump to the wrong location, because 2064 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2065 */ 2066 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2067 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2068 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2069 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2070 #else 2071 wrmsrl_cstar((unsigned long)ignore_sysret); 2072 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2073 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2074 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2075 #endif 2076 2077 /* 2078 * Flags to clear on syscall; clear as much as possible 2079 * to minimize user space-kernel interference. 2080 */ 2081 wrmsrl(MSR_SYSCALL_MASK, 2082 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2083 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2084 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2085 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2086 X86_EFLAGS_AC|X86_EFLAGS_ID); 2087 } 2088 2089 #else /* CONFIG_X86_64 */ 2090 2091 #ifdef CONFIG_STACKPROTECTOR 2092 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2093 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2094 #endif 2095 2096 #endif /* CONFIG_X86_64 */ 2097 2098 /* 2099 * Clear all 6 debug registers: 2100 */ 2101 static void clear_all_debug_regs(void) 2102 { 2103 int i; 2104 2105 for (i = 0; i < 8; i++) { 2106 /* Ignore db4, db5 */ 2107 if ((i == 4) || (i == 5)) 2108 continue; 2109 2110 set_debugreg(0, i); 2111 } 2112 } 2113 2114 #ifdef CONFIG_KGDB 2115 /* 2116 * Restore debug regs if using kgdbwait and you have a kernel debugger 2117 * connection established. 2118 */ 2119 static void dbg_restore_debug_regs(void) 2120 { 2121 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2122 arch_kgdb_ops.correct_hw_break(); 2123 } 2124 #else /* ! CONFIG_KGDB */ 2125 #define dbg_restore_debug_regs() 2126 #endif /* ! CONFIG_KGDB */ 2127 2128 static inline void setup_getcpu(int cpu) 2129 { 2130 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2131 struct desc_struct d = { }; 2132 2133 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2134 wrmsr(MSR_TSC_AUX, cpudata, 0); 2135 2136 /* Store CPU and node number in limit. */ 2137 d.limit0 = cpudata; 2138 d.limit1 = cpudata >> 16; 2139 2140 d.type = 5; /* RO data, expand down, accessed */ 2141 d.dpl = 3; /* Visible to user code */ 2142 d.s = 1; /* Not a system segment */ 2143 d.p = 1; /* Present */ 2144 d.d = 1; /* 32-bit */ 2145 2146 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2147 } 2148 2149 #ifdef CONFIG_X86_64 2150 static inline void ucode_cpu_init(int cpu) { } 2151 2152 static inline void tss_setup_ist(struct tss_struct *tss) 2153 { 2154 /* Set up the per-CPU TSS IST stacks */ 2155 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2156 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2157 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2158 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2159 /* Only mapped when SEV-ES is active */ 2160 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2161 } 2162 2163 #else /* CONFIG_X86_64 */ 2164 2165 static inline void ucode_cpu_init(int cpu) 2166 { 2167 show_ucode_info_early(); 2168 } 2169 2170 static inline void tss_setup_ist(struct tss_struct *tss) { } 2171 2172 #endif /* !CONFIG_X86_64 */ 2173 2174 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2175 { 2176 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2177 2178 #ifdef CONFIG_X86_IOPL_IOPERM 2179 tss->io_bitmap.prev_max = 0; 2180 tss->io_bitmap.prev_sequence = 0; 2181 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2182 /* 2183 * Invalidate the extra array entry past the end of the all 2184 * permission bitmap as required by the hardware. 2185 */ 2186 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2187 #endif 2188 } 2189 2190 /* 2191 * Setup everything needed to handle exceptions from the IDT, including the IST 2192 * exceptions which use paranoid_entry(). 2193 */ 2194 void cpu_init_exception_handling(void) 2195 { 2196 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2197 int cpu = raw_smp_processor_id(); 2198 2199 /* paranoid_entry() gets the CPU number from the GDT */ 2200 setup_getcpu(cpu); 2201 2202 /* IST vectors need TSS to be set up. */ 2203 tss_setup_ist(tss); 2204 tss_setup_io_bitmap(tss); 2205 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2206 2207 load_TR_desc(); 2208 2209 /* GHCB needs to be setup to handle #VC. */ 2210 setup_ghcb(); 2211 2212 /* Finally load the IDT */ 2213 load_current_idt(); 2214 } 2215 2216 /* 2217 * cpu_init() initializes state that is per-CPU. Some data is already 2218 * initialized (naturally) in the bootstrap process, such as the GDT. We 2219 * reload it nevertheless, this function acts as a 'CPU state barrier', 2220 * nothing should get across. 2221 */ 2222 void cpu_init(void) 2223 { 2224 struct task_struct *cur = current; 2225 int cpu = raw_smp_processor_id(); 2226 2227 ucode_cpu_init(cpu); 2228 2229 #ifdef CONFIG_NUMA 2230 if (this_cpu_read(numa_node) == 0 && 2231 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2232 set_numa_node(early_cpu_to_node(cpu)); 2233 #endif 2234 pr_debug("Initializing CPU#%d\n", cpu); 2235 2236 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2237 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2238 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2239 2240 if (IS_ENABLED(CONFIG_X86_64)) { 2241 loadsegment(fs, 0); 2242 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2243 syscall_init(); 2244 2245 wrmsrl(MSR_FS_BASE, 0); 2246 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2247 barrier(); 2248 2249 x2apic_setup(); 2250 } 2251 2252 mmgrab(&init_mm); 2253 cur->active_mm = &init_mm; 2254 BUG_ON(cur->mm); 2255 initialize_tlbstate_and_flush(); 2256 enter_lazy_tlb(&init_mm, cur); 2257 2258 /* 2259 * sp0 points to the entry trampoline stack regardless of what task 2260 * is running. 2261 */ 2262 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2263 2264 load_mm_ldt(&init_mm); 2265 2266 clear_all_debug_regs(); 2267 dbg_restore_debug_regs(); 2268 2269 doublefault_init_cpu_tss(); 2270 2271 if (is_uv_system()) 2272 uv_cpu_init(); 2273 2274 load_fixmap_gdt(cpu); 2275 } 2276 2277 #ifdef CONFIG_MICROCODE_LATE_LOADING 2278 /** 2279 * store_cpu_caps() - Store a snapshot of CPU capabilities 2280 * @curr_info: Pointer where to store it 2281 * 2282 * Returns: None 2283 */ 2284 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2285 { 2286 /* Reload CPUID max function as it might've changed. */ 2287 curr_info->cpuid_level = cpuid_eax(0); 2288 2289 /* Copy all capability leafs and pick up the synthetic ones. */ 2290 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2291 sizeof(curr_info->x86_capability)); 2292 2293 /* Get the hardware CPUID leafs */ 2294 get_cpu_cap(curr_info); 2295 } 2296 2297 /** 2298 * microcode_check() - Check if any CPU capabilities changed after an update. 2299 * @prev_info: CPU capabilities stored before an update. 2300 * 2301 * The microcode loader calls this upon late microcode load to recheck features, 2302 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2303 * 2304 * Return: None 2305 */ 2306 void microcode_check(struct cpuinfo_x86 *prev_info) 2307 { 2308 struct cpuinfo_x86 curr_info; 2309 2310 perf_check_microcode(); 2311 2312 amd_check_microcode(); 2313 2314 store_cpu_caps(&curr_info); 2315 2316 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2317 sizeof(prev_info->x86_capability))) 2318 return; 2319 2320 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2321 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2322 } 2323 #endif 2324 2325 /* 2326 * Invoked from core CPU hotplug code after hotplug operations 2327 */ 2328 void arch_smt_update(void) 2329 { 2330 /* Handle the speculative execution misfeatures */ 2331 cpu_bugs_smt_update(); 2332 /* Check whether IPI broadcasting can be enabled */ 2333 apic_smt_update(); 2334 } 2335 2336 void __init arch_cpu_finalize_init(void) 2337 { 2338 identify_boot_cpu(); 2339 2340 /* 2341 * identify_boot_cpu() initialized SMT support information, let the 2342 * core code know. 2343 */ 2344 cpu_smt_set_num_threads(smp_num_siblings, smp_num_siblings); 2345 2346 if (!IS_ENABLED(CONFIG_SMP)) { 2347 pr_info("CPU: "); 2348 print_cpu_info(&boot_cpu_data); 2349 } 2350 2351 cpu_select_mitigations(); 2352 2353 arch_smt_update(); 2354 2355 if (IS_ENABLED(CONFIG_X86_32)) { 2356 /* 2357 * Check whether this is a real i386 which is not longer 2358 * supported and fixup the utsname. 2359 */ 2360 if (boot_cpu_data.x86 < 4) 2361 panic("Kernel requires i486+ for 'invlpg' and other features"); 2362 2363 init_utsname()->machine[1] = 2364 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2365 } 2366 2367 /* 2368 * Must be before alternatives because it might set or clear 2369 * feature bits. 2370 */ 2371 fpu__init_system(); 2372 fpu__init_cpu(); 2373 2374 alternative_instructions(); 2375 2376 if (IS_ENABLED(CONFIG_X86_64)) { 2377 /* 2378 * Make sure the first 2MB area is not mapped by huge pages 2379 * There are typically fixed size MTRRs in there and overlapping 2380 * MTRRs into large pages causes slow downs. 2381 * 2382 * Right now we don't do that with gbpages because there seems 2383 * very little benefit for that case. 2384 */ 2385 if (!direct_gbpages) 2386 set_memory_4k((unsigned long)__va(0), 1); 2387 } else { 2388 fpu__init_check_bugs(); 2389 } 2390 2391 /* 2392 * This needs to be called before any devices perform DMA 2393 * operations that might use the SWIOTLB bounce buffers. It will 2394 * mark the bounce buffers as decrypted so that their usage will 2395 * not cause "plain-text" data to be decrypted when accessed. It 2396 * must be called after late_time_init() so that Hyper-V x86/x64 2397 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2398 */ 2399 mem_encrypt_init(); 2400 } 2401