1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 51 #ifdef CONFIG_X86_LOCAL_APIC 52 #include <asm/uv/uv.h> 53 #endif 54 55 #include "cpu.h" 56 57 u32 elf_hwcap2 __read_mostly; 58 59 /* all of these masks are initialized in setup_cpu_local_masks() */ 60 cpumask_var_t cpu_initialized_mask; 61 cpumask_var_t cpu_callout_mask; 62 cpumask_var_t cpu_callin_mask; 63 64 /* representing cpus for which sibling maps can be computed */ 65 cpumask_var_t cpu_sibling_setup_mask; 66 67 /* correctly size the local cpu masks */ 68 void __init setup_cpu_local_masks(void) 69 { 70 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 71 alloc_bootmem_cpumask_var(&cpu_callin_mask); 72 alloc_bootmem_cpumask_var(&cpu_callout_mask); 73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 74 } 75 76 static void default_init(struct cpuinfo_x86 *c) 77 { 78 #ifdef CONFIG_X86_64 79 cpu_detect_cache_sizes(c); 80 #else 81 /* Not much we can do here... */ 82 /* Check if at least it has cpuid */ 83 if (c->cpuid_level == -1) { 84 /* No cpuid. It must be an ancient CPU */ 85 if (c->x86 == 4) 86 strcpy(c->x86_model_id, "486"); 87 else if (c->x86 == 3) 88 strcpy(c->x86_model_id, "386"); 89 } 90 #endif 91 } 92 93 static const struct cpu_dev default_cpu = { 94 .c_init = default_init, 95 .c_vendor = "Unknown", 96 .c_x86_vendor = X86_VENDOR_UNKNOWN, 97 }; 98 99 static const struct cpu_dev *this_cpu = &default_cpu; 100 101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 102 #ifdef CONFIG_X86_64 103 /* 104 * We need valid kernel segments for data and code in long mode too 105 * IRET will check the segment types kkeil 2000/10/28 106 * Also sysret mandates a special GDT layout 107 * 108 * TLS descriptors are currently at a different place compared to i386. 109 * Hopefully nobody expects them at a fixed place (Wine?) 110 */ 111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 117 #else 118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 122 /* 123 * Segments used for calling PnP BIOS have byte granularity. 124 * They code segments and data segments have fixed 64k limits, 125 * the transfer segment sizes are set at run time. 126 */ 127 /* 32-bit code */ 128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 129 /* 16-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 131 /* 16-bit data */ 132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 138 * The APM segments have byte granularity and their bases 139 * are set at run time. All have 64k limits. 140 */ 141 /* 32-bit code */ 142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 143 /* 16-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 145 /* data */ 146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 147 148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 150 GDT_STACK_CANARY_INIT 151 #endif 152 } }; 153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 154 155 static int __init x86_mpx_setup(char *s) 156 { 157 /* require an exact match without trailing characters */ 158 if (strlen(s)) 159 return 0; 160 161 /* do not emit a message if the feature is not present */ 162 if (!boot_cpu_has(X86_FEATURE_MPX)) 163 return 1; 164 165 setup_clear_cpu_cap(X86_FEATURE_MPX); 166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 167 return 1; 168 } 169 __setup("nompx", x86_mpx_setup); 170 171 #ifdef CONFIG_X86_64 172 static int __init x86_nopcid_setup(char *s) 173 { 174 /* nopcid doesn't accept parameters */ 175 if (s) 176 return -EINVAL; 177 178 /* do not emit a message if the feature is not present */ 179 if (!boot_cpu_has(X86_FEATURE_PCID)) 180 return 0; 181 182 setup_clear_cpu_cap(X86_FEATURE_PCID); 183 pr_info("nopcid: PCID feature disabled\n"); 184 return 0; 185 } 186 early_param("nopcid", x86_nopcid_setup); 187 #endif 188 189 static int __init x86_noinvpcid_setup(char *s) 190 { 191 /* noinvpcid doesn't accept parameters */ 192 if (s) 193 return -EINVAL; 194 195 /* do not emit a message if the feature is not present */ 196 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 197 return 0; 198 199 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 200 pr_info("noinvpcid: INVPCID feature disabled\n"); 201 return 0; 202 } 203 early_param("noinvpcid", x86_noinvpcid_setup); 204 205 #ifdef CONFIG_X86_32 206 static int cachesize_override = -1; 207 static int disable_x86_serial_nr = 1; 208 209 static int __init cachesize_setup(char *str) 210 { 211 get_option(&str, &cachesize_override); 212 return 1; 213 } 214 __setup("cachesize=", cachesize_setup); 215 216 static int __init x86_sep_setup(char *s) 217 { 218 setup_clear_cpu_cap(X86_FEATURE_SEP); 219 return 1; 220 } 221 __setup("nosep", x86_sep_setup); 222 223 /* Standard macro to see if a specific flag is changeable */ 224 static inline int flag_is_changeable_p(u32 flag) 225 { 226 u32 f1, f2; 227 228 /* 229 * Cyrix and IDT cpus allow disabling of CPUID 230 * so the code below may return different results 231 * when it is executed before and after enabling 232 * the CPUID. Add "volatile" to not allow gcc to 233 * optimize the subsequent calls to this function. 234 */ 235 asm volatile ("pushfl \n\t" 236 "pushfl \n\t" 237 "popl %0 \n\t" 238 "movl %0, %1 \n\t" 239 "xorl %2, %0 \n\t" 240 "pushl %0 \n\t" 241 "popfl \n\t" 242 "pushfl \n\t" 243 "popl %0 \n\t" 244 "popfl \n\t" 245 246 : "=&r" (f1), "=&r" (f2) 247 : "ir" (flag)); 248 249 return ((f1^f2) & flag) != 0; 250 } 251 252 /* Probe for the CPUID instruction */ 253 int have_cpuid_p(void) 254 { 255 return flag_is_changeable_p(X86_EFLAGS_ID); 256 } 257 258 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 259 { 260 unsigned long lo, hi; 261 262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 263 return; 264 265 /* Disable processor serial number: */ 266 267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 268 lo |= 0x200000; 269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 270 271 pr_notice("CPU serial number disabled.\n"); 272 clear_cpu_cap(c, X86_FEATURE_PN); 273 274 /* Disabling the serial number may affect the cpuid level */ 275 c->cpuid_level = cpuid_eax(0); 276 } 277 278 static int __init x86_serial_nr_setup(char *s) 279 { 280 disable_x86_serial_nr = 0; 281 return 1; 282 } 283 __setup("serialnumber", x86_serial_nr_setup); 284 #else 285 static inline int flag_is_changeable_p(u32 flag) 286 { 287 return 1; 288 } 289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 290 { 291 } 292 #endif 293 294 static __init int setup_disable_smep(char *arg) 295 { 296 setup_clear_cpu_cap(X86_FEATURE_SMEP); 297 /* Check for things that depend on SMEP being enabled: */ 298 check_mpx_erratum(&boot_cpu_data); 299 return 1; 300 } 301 __setup("nosmep", setup_disable_smep); 302 303 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 304 { 305 if (cpu_has(c, X86_FEATURE_SMEP)) 306 cr4_set_bits(X86_CR4_SMEP); 307 } 308 309 static __init int setup_disable_smap(char *arg) 310 { 311 setup_clear_cpu_cap(X86_FEATURE_SMAP); 312 return 1; 313 } 314 __setup("nosmap", setup_disable_smap); 315 316 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 317 { 318 unsigned long eflags = native_save_fl(); 319 320 /* This should have been cleared long ago */ 321 BUG_ON(eflags & X86_EFLAGS_AC); 322 323 if (cpu_has(c, X86_FEATURE_SMAP)) { 324 #ifdef CONFIG_X86_SMAP 325 cr4_set_bits(X86_CR4_SMAP); 326 #else 327 cr4_clear_bits(X86_CR4_SMAP); 328 #endif 329 } 330 } 331 332 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 333 { 334 /* Check the boot processor, plus build option for UMIP. */ 335 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 336 goto out; 337 338 /* Check the current processor's cpuid bits. */ 339 if (!cpu_has(c, X86_FEATURE_UMIP)) 340 goto out; 341 342 cr4_set_bits(X86_CR4_UMIP); 343 344 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); 345 346 return; 347 348 out: 349 /* 350 * Make sure UMIP is disabled in case it was enabled in a 351 * previous boot (e.g., via kexec). 352 */ 353 cr4_clear_bits(X86_CR4_UMIP); 354 } 355 356 /* 357 * Protection Keys are not available in 32-bit mode. 358 */ 359 static bool pku_disabled; 360 361 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 362 { 363 /* check the boot processor, plus compile options for PKU: */ 364 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 365 return; 366 /* checks the actual processor's cpuid bits: */ 367 if (!cpu_has(c, X86_FEATURE_PKU)) 368 return; 369 if (pku_disabled) 370 return; 371 372 cr4_set_bits(X86_CR4_PKE); 373 /* 374 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 375 * cpuid bit to be set. We need to ensure that we 376 * update that bit in this CPU's "cpu_info". 377 */ 378 get_cpu_cap(c); 379 } 380 381 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 382 static __init int setup_disable_pku(char *arg) 383 { 384 /* 385 * Do not clear the X86_FEATURE_PKU bit. All of the 386 * runtime checks are against OSPKE so clearing the 387 * bit does nothing. 388 * 389 * This way, we will see "pku" in cpuinfo, but not 390 * "ospke", which is exactly what we want. It shows 391 * that the CPU has PKU, but the OS has not enabled it. 392 * This happens to be exactly how a system would look 393 * if we disabled the config option. 394 */ 395 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 396 pku_disabled = true; 397 return 1; 398 } 399 __setup("nopku", setup_disable_pku); 400 #endif /* CONFIG_X86_64 */ 401 402 /* 403 * Some CPU features depend on higher CPUID levels, which may not always 404 * be available due to CPUID level capping or broken virtualization 405 * software. Add those features to this table to auto-disable them. 406 */ 407 struct cpuid_dependent_feature { 408 u32 feature; 409 u32 level; 410 }; 411 412 static const struct cpuid_dependent_feature 413 cpuid_dependent_features[] = { 414 { X86_FEATURE_MWAIT, 0x00000005 }, 415 { X86_FEATURE_DCA, 0x00000009 }, 416 { X86_FEATURE_XSAVE, 0x0000000d }, 417 { 0, 0 } 418 }; 419 420 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 421 { 422 const struct cpuid_dependent_feature *df; 423 424 for (df = cpuid_dependent_features; df->feature; df++) { 425 426 if (!cpu_has(c, df->feature)) 427 continue; 428 /* 429 * Note: cpuid_level is set to -1 if unavailable, but 430 * extended_extended_level is set to 0 if unavailable 431 * and the legitimate extended levels are all negative 432 * when signed; hence the weird messing around with 433 * signs here... 434 */ 435 if (!((s32)df->level < 0 ? 436 (u32)df->level > (u32)c->extended_cpuid_level : 437 (s32)df->level > (s32)c->cpuid_level)) 438 continue; 439 440 clear_cpu_cap(c, df->feature); 441 if (!warn) 442 continue; 443 444 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 445 x86_cap_flag(df->feature), df->level); 446 } 447 } 448 449 /* 450 * Naming convention should be: <Name> [(<Codename>)] 451 * This table only is used unless init_<vendor>() below doesn't set it; 452 * in particular, if CPUID levels 0x80000002..4 are supported, this 453 * isn't used 454 */ 455 456 /* Look up CPU names by table lookup. */ 457 static const char *table_lookup_model(struct cpuinfo_x86 *c) 458 { 459 #ifdef CONFIG_X86_32 460 const struct legacy_cpu_model_info *info; 461 462 if (c->x86_model >= 16) 463 return NULL; /* Range check */ 464 465 if (!this_cpu) 466 return NULL; 467 468 info = this_cpu->legacy_models; 469 470 while (info->family) { 471 if (info->family == c->x86) 472 return info->model_names[c->x86_model]; 473 info++; 474 } 475 #endif 476 return NULL; /* Not found */ 477 } 478 479 __u32 cpu_caps_cleared[NCAPINTS]; 480 __u32 cpu_caps_set[NCAPINTS]; 481 482 void load_percpu_segment(int cpu) 483 { 484 #ifdef CONFIG_X86_32 485 loadsegment(fs, __KERNEL_PERCPU); 486 #else 487 __loadsegment_simple(gs, 0); 488 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 489 #endif 490 load_stack_canary_segment(); 491 } 492 493 /* Setup the fixmap mapping only once per-processor */ 494 static inline void setup_fixmap_gdt(int cpu) 495 { 496 #ifdef CONFIG_X86_64 497 /* On 64-bit systems, we use a read-only fixmap GDT. */ 498 pgprot_t prot = PAGE_KERNEL_RO; 499 #else 500 /* 501 * On native 32-bit systems, the GDT cannot be read-only because 502 * our double fault handler uses a task gate, and entering through 503 * a task gate needs to change an available TSS to busy. If the GDT 504 * is read-only, that will triple fault. 505 * 506 * On Xen PV, the GDT must be read-only because the hypervisor requires 507 * it. 508 */ 509 pgprot_t prot = boot_cpu_has(X86_FEATURE_XENPV) ? 510 PAGE_KERNEL_RO : PAGE_KERNEL; 511 #endif 512 513 __set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot); 514 } 515 516 /* Load the original GDT from the per-cpu structure */ 517 void load_direct_gdt(int cpu) 518 { 519 struct desc_ptr gdt_descr; 520 521 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 522 gdt_descr.size = GDT_SIZE - 1; 523 load_gdt(&gdt_descr); 524 } 525 EXPORT_SYMBOL_GPL(load_direct_gdt); 526 527 /* Load a fixmap remapping of the per-cpu GDT */ 528 void load_fixmap_gdt(int cpu) 529 { 530 struct desc_ptr gdt_descr; 531 532 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 533 gdt_descr.size = GDT_SIZE - 1; 534 load_gdt(&gdt_descr); 535 } 536 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 537 538 /* 539 * Current gdt points %fs at the "master" per-cpu area: after this, 540 * it's on the real one. 541 */ 542 void switch_to_new_gdt(int cpu) 543 { 544 /* Load the original GDT */ 545 load_direct_gdt(cpu); 546 /* Reload the per-cpu base */ 547 load_percpu_segment(cpu); 548 } 549 550 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 551 552 static void get_model_name(struct cpuinfo_x86 *c) 553 { 554 unsigned int *v; 555 char *p, *q, *s; 556 557 if (c->extended_cpuid_level < 0x80000004) 558 return; 559 560 v = (unsigned int *)c->x86_model_id; 561 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 562 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 563 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 564 c->x86_model_id[48] = 0; 565 566 /* Trim whitespace */ 567 p = q = s = &c->x86_model_id[0]; 568 569 while (*p == ' ') 570 p++; 571 572 while (*p) { 573 /* Note the last non-whitespace index */ 574 if (!isspace(*p)) 575 s = q; 576 577 *q++ = *p++; 578 } 579 580 *(s + 1) = '\0'; 581 } 582 583 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 584 { 585 unsigned int n, dummy, ebx, ecx, edx, l2size; 586 587 n = c->extended_cpuid_level; 588 589 if (n >= 0x80000005) { 590 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 591 c->x86_cache_size = (ecx>>24) + (edx>>24); 592 #ifdef CONFIG_X86_64 593 /* On K8 L1 TLB is inclusive, so don't count it */ 594 c->x86_tlbsize = 0; 595 #endif 596 } 597 598 if (n < 0x80000006) /* Some chips just has a large L1. */ 599 return; 600 601 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 602 l2size = ecx >> 16; 603 604 #ifdef CONFIG_X86_64 605 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 606 #else 607 /* do processor-specific cache resizing */ 608 if (this_cpu->legacy_cache_size) 609 l2size = this_cpu->legacy_cache_size(c, l2size); 610 611 /* Allow user to override all this if necessary. */ 612 if (cachesize_override != -1) 613 l2size = cachesize_override; 614 615 if (l2size == 0) 616 return; /* Again, no L2 cache is possible */ 617 #endif 618 619 c->x86_cache_size = l2size; 620 } 621 622 u16 __read_mostly tlb_lli_4k[NR_INFO]; 623 u16 __read_mostly tlb_lli_2m[NR_INFO]; 624 u16 __read_mostly tlb_lli_4m[NR_INFO]; 625 u16 __read_mostly tlb_lld_4k[NR_INFO]; 626 u16 __read_mostly tlb_lld_2m[NR_INFO]; 627 u16 __read_mostly tlb_lld_4m[NR_INFO]; 628 u16 __read_mostly tlb_lld_1g[NR_INFO]; 629 630 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 631 { 632 if (this_cpu->c_detect_tlb) 633 this_cpu->c_detect_tlb(c); 634 635 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 636 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 637 tlb_lli_4m[ENTRIES]); 638 639 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 640 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 641 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 642 } 643 644 void detect_ht(struct cpuinfo_x86 *c) 645 { 646 #ifdef CONFIG_SMP 647 u32 eax, ebx, ecx, edx; 648 int index_msb, core_bits; 649 static bool printed; 650 651 if (!cpu_has(c, X86_FEATURE_HT)) 652 return; 653 654 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 655 goto out; 656 657 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 658 return; 659 660 cpuid(1, &eax, &ebx, &ecx, &edx); 661 662 smp_num_siblings = (ebx & 0xff0000) >> 16; 663 664 if (smp_num_siblings == 1) { 665 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 666 goto out; 667 } 668 669 if (smp_num_siblings <= 1) 670 goto out; 671 672 index_msb = get_count_order(smp_num_siblings); 673 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 674 675 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 676 677 index_msb = get_count_order(smp_num_siblings); 678 679 core_bits = get_count_order(c->x86_max_cores); 680 681 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 682 ((1 << core_bits) - 1); 683 684 out: 685 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 686 pr_info("CPU: Physical Processor ID: %d\n", 687 c->phys_proc_id); 688 pr_info("CPU: Processor Core ID: %d\n", 689 c->cpu_core_id); 690 printed = 1; 691 } 692 #endif 693 } 694 695 static void get_cpu_vendor(struct cpuinfo_x86 *c) 696 { 697 char *v = c->x86_vendor_id; 698 int i; 699 700 for (i = 0; i < X86_VENDOR_NUM; i++) { 701 if (!cpu_devs[i]) 702 break; 703 704 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 705 (cpu_devs[i]->c_ident[1] && 706 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 707 708 this_cpu = cpu_devs[i]; 709 c->x86_vendor = this_cpu->c_x86_vendor; 710 return; 711 } 712 } 713 714 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 715 "CPU: Your system may be unstable.\n", v); 716 717 c->x86_vendor = X86_VENDOR_UNKNOWN; 718 this_cpu = &default_cpu; 719 } 720 721 void cpu_detect(struct cpuinfo_x86 *c) 722 { 723 /* Get vendor name */ 724 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 725 (unsigned int *)&c->x86_vendor_id[0], 726 (unsigned int *)&c->x86_vendor_id[8], 727 (unsigned int *)&c->x86_vendor_id[4]); 728 729 c->x86 = 4; 730 /* Intel-defined flags: level 0x00000001 */ 731 if (c->cpuid_level >= 0x00000001) { 732 u32 junk, tfms, cap0, misc; 733 734 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 735 c->x86 = x86_family(tfms); 736 c->x86_model = x86_model(tfms); 737 c->x86_mask = x86_stepping(tfms); 738 739 if (cap0 & (1<<19)) { 740 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 741 c->x86_cache_alignment = c->x86_clflush_size; 742 } 743 } 744 } 745 746 static void apply_forced_caps(struct cpuinfo_x86 *c) 747 { 748 int i; 749 750 for (i = 0; i < NCAPINTS; i++) { 751 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 752 c->x86_capability[i] |= cpu_caps_set[i]; 753 } 754 } 755 756 void get_cpu_cap(struct cpuinfo_x86 *c) 757 { 758 u32 eax, ebx, ecx, edx; 759 760 /* Intel-defined flags: level 0x00000001 */ 761 if (c->cpuid_level >= 0x00000001) { 762 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 763 764 c->x86_capability[CPUID_1_ECX] = ecx; 765 c->x86_capability[CPUID_1_EDX] = edx; 766 } 767 768 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 769 if (c->cpuid_level >= 0x00000006) 770 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 771 772 /* Additional Intel-defined flags: level 0x00000007 */ 773 if (c->cpuid_level >= 0x00000007) { 774 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 775 c->x86_capability[CPUID_7_0_EBX] = ebx; 776 c->x86_capability[CPUID_7_ECX] = ecx; 777 } 778 779 /* Extended state features: level 0x0000000d */ 780 if (c->cpuid_level >= 0x0000000d) { 781 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 782 783 c->x86_capability[CPUID_D_1_EAX] = eax; 784 } 785 786 /* Additional Intel-defined flags: level 0x0000000F */ 787 if (c->cpuid_level >= 0x0000000F) { 788 789 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 790 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 791 c->x86_capability[CPUID_F_0_EDX] = edx; 792 793 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 794 /* will be overridden if occupancy monitoring exists */ 795 c->x86_cache_max_rmid = ebx; 796 797 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 798 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 799 c->x86_capability[CPUID_F_1_EDX] = edx; 800 801 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 802 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 803 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 804 c->x86_cache_max_rmid = ecx; 805 c->x86_cache_occ_scale = ebx; 806 } 807 } else { 808 c->x86_cache_max_rmid = -1; 809 c->x86_cache_occ_scale = -1; 810 } 811 } 812 813 /* AMD-defined flags: level 0x80000001 */ 814 eax = cpuid_eax(0x80000000); 815 c->extended_cpuid_level = eax; 816 817 if ((eax & 0xffff0000) == 0x80000000) { 818 if (eax >= 0x80000001) { 819 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 820 821 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 822 c->x86_capability[CPUID_8000_0001_EDX] = edx; 823 } 824 } 825 826 if (c->extended_cpuid_level >= 0x80000007) { 827 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 828 829 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 830 c->x86_power = edx; 831 } 832 833 if (c->extended_cpuid_level >= 0x80000008) { 834 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 835 836 c->x86_virt_bits = (eax >> 8) & 0xff; 837 c->x86_phys_bits = eax & 0xff; 838 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 839 } 840 #ifdef CONFIG_X86_32 841 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 842 c->x86_phys_bits = 36; 843 #endif 844 845 if (c->extended_cpuid_level >= 0x8000000a) 846 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 847 848 init_scattered_cpuid_features(c); 849 850 /* 851 * Clear/Set all flags overridden by options, after probe. 852 * This needs to happen each time we re-probe, which may happen 853 * several times during CPU initialization. 854 */ 855 apply_forced_caps(c); 856 } 857 858 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 859 { 860 #ifdef CONFIG_X86_32 861 int i; 862 863 /* 864 * First of all, decide if this is a 486 or higher 865 * It's a 486 if we can modify the AC flag 866 */ 867 if (flag_is_changeable_p(X86_EFLAGS_AC)) 868 c->x86 = 4; 869 else 870 c->x86 = 3; 871 872 for (i = 0; i < X86_VENDOR_NUM; i++) 873 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 874 c->x86_vendor_id[0] = 0; 875 cpu_devs[i]->c_identify(c); 876 if (c->x86_vendor_id[0]) { 877 get_cpu_vendor(c); 878 break; 879 } 880 } 881 #endif 882 } 883 884 /* 885 * Do minimum CPU detection early. 886 * Fields really needed: vendor, cpuid_level, family, model, mask, 887 * cache alignment. 888 * The others are not touched to avoid unwanted side effects. 889 * 890 * WARNING: this function is only called on the boot CPU. Don't add code 891 * here that is supposed to run on all CPUs. 892 */ 893 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 894 { 895 #ifdef CONFIG_X86_64 896 c->x86_clflush_size = 64; 897 c->x86_phys_bits = 36; 898 c->x86_virt_bits = 48; 899 #else 900 c->x86_clflush_size = 32; 901 c->x86_phys_bits = 32; 902 c->x86_virt_bits = 32; 903 #endif 904 c->x86_cache_alignment = c->x86_clflush_size; 905 906 memset(&c->x86_capability, 0, sizeof c->x86_capability); 907 c->extended_cpuid_level = 0; 908 909 /* cyrix could have cpuid enabled via c_identify()*/ 910 if (have_cpuid_p()) { 911 cpu_detect(c); 912 get_cpu_vendor(c); 913 get_cpu_cap(c); 914 setup_force_cpu_cap(X86_FEATURE_CPUID); 915 916 if (this_cpu->c_early_init) 917 this_cpu->c_early_init(c); 918 919 c->cpu_index = 0; 920 filter_cpuid_features(c, false); 921 922 if (this_cpu->c_bsp_init) 923 this_cpu->c_bsp_init(c); 924 } else { 925 identify_cpu_without_cpuid(c); 926 setup_clear_cpu_cap(X86_FEATURE_CPUID); 927 } 928 929 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 930 fpu__init_system(c); 931 932 #ifdef CONFIG_X86_32 933 /* 934 * Regardless of whether PCID is enumerated, the SDM says 935 * that it can't be enabled in 32-bit mode. 936 */ 937 setup_clear_cpu_cap(X86_FEATURE_PCID); 938 #endif 939 } 940 941 void __init early_cpu_init(void) 942 { 943 const struct cpu_dev *const *cdev; 944 int count = 0; 945 946 #ifdef CONFIG_PROCESSOR_SELECT 947 pr_info("KERNEL supported cpus:\n"); 948 #endif 949 950 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 951 const struct cpu_dev *cpudev = *cdev; 952 953 if (count >= X86_VENDOR_NUM) 954 break; 955 cpu_devs[count] = cpudev; 956 count++; 957 958 #ifdef CONFIG_PROCESSOR_SELECT 959 { 960 unsigned int j; 961 962 for (j = 0; j < 2; j++) { 963 if (!cpudev->c_ident[j]) 964 continue; 965 pr_info(" %s %s\n", cpudev->c_vendor, 966 cpudev->c_ident[j]); 967 } 968 } 969 #endif 970 } 971 early_identify_cpu(&boot_cpu_data); 972 } 973 974 /* 975 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 976 * unfortunately, that's not true in practice because of early VIA 977 * chips and (more importantly) broken virtualizers that are not easy 978 * to detect. In the latter case it doesn't even *fail* reliably, so 979 * probing for it doesn't even work. Disable it completely on 32-bit 980 * unless we can find a reliable way to detect all the broken cases. 981 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 982 */ 983 static void detect_nopl(struct cpuinfo_x86 *c) 984 { 985 #ifdef CONFIG_X86_32 986 clear_cpu_cap(c, X86_FEATURE_NOPL); 987 #else 988 set_cpu_cap(c, X86_FEATURE_NOPL); 989 #endif 990 } 991 992 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 993 { 994 #ifdef CONFIG_X86_64 995 /* 996 * Empirically, writing zero to a segment selector on AMD does 997 * not clear the base, whereas writing zero to a segment 998 * selector on Intel does clear the base. Intel's behavior 999 * allows slightly faster context switches in the common case 1000 * where GS is unused by the prev and next threads. 1001 * 1002 * Since neither vendor documents this anywhere that I can see, 1003 * detect it directly instead of hardcoding the choice by 1004 * vendor. 1005 * 1006 * I've designated AMD's behavior as the "bug" because it's 1007 * counterintuitive and less friendly. 1008 */ 1009 1010 unsigned long old_base, tmp; 1011 rdmsrl(MSR_FS_BASE, old_base); 1012 wrmsrl(MSR_FS_BASE, 1); 1013 loadsegment(fs, 0); 1014 rdmsrl(MSR_FS_BASE, tmp); 1015 if (tmp != 0) 1016 set_cpu_bug(c, X86_BUG_NULL_SEG); 1017 wrmsrl(MSR_FS_BASE, old_base); 1018 #endif 1019 } 1020 1021 static void generic_identify(struct cpuinfo_x86 *c) 1022 { 1023 c->extended_cpuid_level = 0; 1024 1025 if (!have_cpuid_p()) 1026 identify_cpu_without_cpuid(c); 1027 1028 /* cyrix could have cpuid enabled via c_identify()*/ 1029 if (!have_cpuid_p()) 1030 return; 1031 1032 cpu_detect(c); 1033 1034 get_cpu_vendor(c); 1035 1036 get_cpu_cap(c); 1037 1038 if (c->cpuid_level >= 0x00000001) { 1039 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1040 #ifdef CONFIG_X86_32 1041 # ifdef CONFIG_SMP 1042 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1043 # else 1044 c->apicid = c->initial_apicid; 1045 # endif 1046 #endif 1047 c->phys_proc_id = c->initial_apicid; 1048 } 1049 1050 get_model_name(c); /* Default name */ 1051 1052 detect_nopl(c); 1053 1054 detect_null_seg_behavior(c); 1055 1056 /* 1057 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1058 * systems that run Linux at CPL > 0 may or may not have the 1059 * issue, but, even if they have the issue, there's absolutely 1060 * nothing we can do about it because we can't use the real IRET 1061 * instruction. 1062 * 1063 * NB: For the time being, only 32-bit kernels support 1064 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1065 * whether to apply espfix using paravirt hooks. If any 1066 * non-paravirt system ever shows up that does *not* have the 1067 * ESPFIX issue, we can change this. 1068 */ 1069 #ifdef CONFIG_X86_32 1070 # ifdef CONFIG_PARAVIRT 1071 do { 1072 extern void native_iret(void); 1073 if (pv_cpu_ops.iret == native_iret) 1074 set_cpu_bug(c, X86_BUG_ESPFIX); 1075 } while (0); 1076 # else 1077 set_cpu_bug(c, X86_BUG_ESPFIX); 1078 # endif 1079 #endif 1080 } 1081 1082 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1083 { 1084 /* 1085 * The heavy lifting of max_rmid and cache_occ_scale are handled 1086 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1087 * in case CQM bits really aren't there in this CPU. 1088 */ 1089 if (c != &boot_cpu_data) { 1090 boot_cpu_data.x86_cache_max_rmid = 1091 min(boot_cpu_data.x86_cache_max_rmid, 1092 c->x86_cache_max_rmid); 1093 } 1094 } 1095 1096 /* 1097 * Validate that ACPI/mptables have the same information about the 1098 * effective APIC id and update the package map. 1099 */ 1100 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1101 { 1102 #ifdef CONFIG_SMP 1103 unsigned int apicid, cpu = smp_processor_id(); 1104 1105 apicid = apic->cpu_present_to_apicid(cpu); 1106 1107 if (apicid != c->apicid) { 1108 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1109 cpu, apicid, c->initial_apicid); 1110 } 1111 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1112 #else 1113 c->logical_proc_id = 0; 1114 #endif 1115 } 1116 1117 /* 1118 * This does the hard work of actually picking apart the CPU stuff... 1119 */ 1120 static void identify_cpu(struct cpuinfo_x86 *c) 1121 { 1122 int i; 1123 1124 c->loops_per_jiffy = loops_per_jiffy; 1125 c->x86_cache_size = -1; 1126 c->x86_vendor = X86_VENDOR_UNKNOWN; 1127 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 1128 c->x86_vendor_id[0] = '\0'; /* Unset */ 1129 c->x86_model_id[0] = '\0'; /* Unset */ 1130 c->x86_max_cores = 1; 1131 c->x86_coreid_bits = 0; 1132 c->cu_id = 0xff; 1133 #ifdef CONFIG_X86_64 1134 c->x86_clflush_size = 64; 1135 c->x86_phys_bits = 36; 1136 c->x86_virt_bits = 48; 1137 #else 1138 c->cpuid_level = -1; /* CPUID not detected */ 1139 c->x86_clflush_size = 32; 1140 c->x86_phys_bits = 32; 1141 c->x86_virt_bits = 32; 1142 #endif 1143 c->x86_cache_alignment = c->x86_clflush_size; 1144 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1145 1146 generic_identify(c); 1147 1148 if (this_cpu->c_identify) 1149 this_cpu->c_identify(c); 1150 1151 /* Clear/Set all flags overridden by options, after probe */ 1152 apply_forced_caps(c); 1153 1154 #ifdef CONFIG_X86_64 1155 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1156 #endif 1157 1158 /* 1159 * Vendor-specific initialization. In this section we 1160 * canonicalize the feature flags, meaning if there are 1161 * features a certain CPU supports which CPUID doesn't 1162 * tell us, CPUID claiming incorrect flags, or other bugs, 1163 * we handle them here. 1164 * 1165 * At the end of this section, c->x86_capability better 1166 * indicate the features this CPU genuinely supports! 1167 */ 1168 if (this_cpu->c_init) 1169 this_cpu->c_init(c); 1170 1171 /* Disable the PN if appropriate */ 1172 squash_the_stupid_serial_number(c); 1173 1174 /* Set up SMEP/SMAP/UMIP */ 1175 setup_smep(c); 1176 setup_smap(c); 1177 setup_umip(c); 1178 1179 /* 1180 * The vendor-specific functions might have changed features. 1181 * Now we do "generic changes." 1182 */ 1183 1184 /* Filter out anything that depends on CPUID levels we don't have */ 1185 filter_cpuid_features(c, true); 1186 1187 /* If the model name is still unset, do table lookup. */ 1188 if (!c->x86_model_id[0]) { 1189 const char *p; 1190 p = table_lookup_model(c); 1191 if (p) 1192 strcpy(c->x86_model_id, p); 1193 else 1194 /* Last resort... */ 1195 sprintf(c->x86_model_id, "%02x/%02x", 1196 c->x86, c->x86_model); 1197 } 1198 1199 #ifdef CONFIG_X86_64 1200 detect_ht(c); 1201 #endif 1202 1203 x86_init_rdrand(c); 1204 x86_init_cache_qos(c); 1205 setup_pku(c); 1206 1207 /* 1208 * Clear/Set all flags overridden by options, need do it 1209 * before following smp all cpus cap AND. 1210 */ 1211 apply_forced_caps(c); 1212 1213 /* 1214 * On SMP, boot_cpu_data holds the common feature set between 1215 * all CPUs; so make sure that we indicate which features are 1216 * common between the CPUs. The first time this routine gets 1217 * executed, c == &boot_cpu_data. 1218 */ 1219 if (c != &boot_cpu_data) { 1220 /* AND the already accumulated flags with these */ 1221 for (i = 0; i < NCAPINTS; i++) 1222 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1223 1224 /* OR, i.e. replicate the bug flags */ 1225 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1226 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1227 } 1228 1229 /* Init Machine Check Exception if available. */ 1230 mcheck_cpu_init(c); 1231 1232 select_idle_routine(c); 1233 1234 #ifdef CONFIG_NUMA 1235 numa_add_cpu(smp_processor_id()); 1236 #endif 1237 } 1238 1239 /* 1240 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1241 * on 32-bit kernels: 1242 */ 1243 #ifdef CONFIG_X86_32 1244 void enable_sep_cpu(void) 1245 { 1246 struct tss_struct *tss; 1247 int cpu; 1248 1249 if (!boot_cpu_has(X86_FEATURE_SEP)) 1250 return; 1251 1252 cpu = get_cpu(); 1253 tss = &per_cpu(cpu_tss, cpu); 1254 1255 /* 1256 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1257 * see the big comment in struct x86_hw_tss's definition. 1258 */ 1259 1260 tss->x86_tss.ss1 = __KERNEL_CS; 1261 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1262 1263 wrmsr(MSR_IA32_SYSENTER_ESP, 1264 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1265 0); 1266 1267 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1268 1269 put_cpu(); 1270 } 1271 #endif 1272 1273 void __init identify_boot_cpu(void) 1274 { 1275 identify_cpu(&boot_cpu_data); 1276 #ifdef CONFIG_X86_32 1277 sysenter_setup(); 1278 enable_sep_cpu(); 1279 #endif 1280 cpu_detect_tlb(&boot_cpu_data); 1281 } 1282 1283 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1284 { 1285 BUG_ON(c == &boot_cpu_data); 1286 identify_cpu(c); 1287 #ifdef CONFIG_X86_32 1288 enable_sep_cpu(); 1289 #endif 1290 mtrr_ap_init(); 1291 validate_apic_and_package_id(c); 1292 } 1293 1294 static __init int setup_noclflush(char *arg) 1295 { 1296 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1297 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1298 return 1; 1299 } 1300 __setup("noclflush", setup_noclflush); 1301 1302 void print_cpu_info(struct cpuinfo_x86 *c) 1303 { 1304 const char *vendor = NULL; 1305 1306 if (c->x86_vendor < X86_VENDOR_NUM) { 1307 vendor = this_cpu->c_vendor; 1308 } else { 1309 if (c->cpuid_level >= 0) 1310 vendor = c->x86_vendor_id; 1311 } 1312 1313 if (vendor && !strstr(c->x86_model_id, vendor)) 1314 pr_cont("%s ", vendor); 1315 1316 if (c->x86_model_id[0]) 1317 pr_cont("%s", c->x86_model_id); 1318 else 1319 pr_cont("%d86", c->x86); 1320 1321 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1322 1323 if (c->x86_mask || c->cpuid_level >= 0) 1324 pr_cont(", stepping: 0x%x)\n", c->x86_mask); 1325 else 1326 pr_cont(")\n"); 1327 } 1328 1329 /* 1330 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1331 * But we need to keep a dummy __setup around otherwise it would 1332 * show up as an environment variable for init. 1333 */ 1334 static __init int setup_clearcpuid(char *arg) 1335 { 1336 return 1; 1337 } 1338 __setup("clearcpuid=", setup_clearcpuid); 1339 1340 #ifdef CONFIG_X86_64 1341 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1342 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1343 1344 /* 1345 * The following percpu variables are hot. Align current_task to 1346 * cacheline size such that they fall in the same cacheline. 1347 */ 1348 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1349 &init_task; 1350 EXPORT_PER_CPU_SYMBOL(current_task); 1351 1352 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1353 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1354 1355 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1356 1357 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1358 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1359 1360 /* 1361 * Special IST stacks which the CPU switches to when it calls 1362 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1363 * limit), all of them are 4K, except the debug stack which 1364 * is 8K. 1365 */ 1366 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1367 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1368 [DEBUG_STACK - 1] = DEBUG_STKSZ 1369 }; 1370 1371 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1372 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1373 1374 /* May not be marked __init: used by software suspend */ 1375 void syscall_init(void) 1376 { 1377 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1378 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1379 1380 #ifdef CONFIG_IA32_EMULATION 1381 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1382 /* 1383 * This only works on Intel CPUs. 1384 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1385 * This does not cause SYSENTER to jump to the wrong location, because 1386 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1387 */ 1388 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1389 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1390 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1391 #else 1392 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1393 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1394 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1395 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1396 #endif 1397 1398 /* Flags to clear on syscall */ 1399 wrmsrl(MSR_SYSCALL_MASK, 1400 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1401 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1402 } 1403 1404 /* 1405 * Copies of the original ist values from the tss are only accessed during 1406 * debugging, no special alignment required. 1407 */ 1408 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1409 1410 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1411 DEFINE_PER_CPU(int, debug_stack_usage); 1412 1413 int is_debug_stack(unsigned long addr) 1414 { 1415 return __this_cpu_read(debug_stack_usage) || 1416 (addr <= __this_cpu_read(debug_stack_addr) && 1417 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1418 } 1419 NOKPROBE_SYMBOL(is_debug_stack); 1420 1421 DEFINE_PER_CPU(u32, debug_idt_ctr); 1422 1423 void debug_stack_set_zero(void) 1424 { 1425 this_cpu_inc(debug_idt_ctr); 1426 load_current_idt(); 1427 } 1428 NOKPROBE_SYMBOL(debug_stack_set_zero); 1429 1430 void debug_stack_reset(void) 1431 { 1432 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1433 return; 1434 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1435 load_current_idt(); 1436 } 1437 NOKPROBE_SYMBOL(debug_stack_reset); 1438 1439 #else /* CONFIG_X86_64 */ 1440 1441 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1442 EXPORT_PER_CPU_SYMBOL(current_task); 1443 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1444 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1445 1446 /* 1447 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1448 * the top of the kernel stack. Use an extra percpu variable to track the 1449 * top of the kernel stack directly. 1450 */ 1451 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1452 (unsigned long)&init_thread_union + THREAD_SIZE; 1453 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1454 1455 #ifdef CONFIG_CC_STACKPROTECTOR 1456 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1457 #endif 1458 1459 #endif /* CONFIG_X86_64 */ 1460 1461 /* 1462 * Clear all 6 debug registers: 1463 */ 1464 static void clear_all_debug_regs(void) 1465 { 1466 int i; 1467 1468 for (i = 0; i < 8; i++) { 1469 /* Ignore db4, db5 */ 1470 if ((i == 4) || (i == 5)) 1471 continue; 1472 1473 set_debugreg(0, i); 1474 } 1475 } 1476 1477 #ifdef CONFIG_KGDB 1478 /* 1479 * Restore debug regs if using kgdbwait and you have a kernel debugger 1480 * connection established. 1481 */ 1482 static void dbg_restore_debug_regs(void) 1483 { 1484 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1485 arch_kgdb_ops.correct_hw_break(); 1486 } 1487 #else /* ! CONFIG_KGDB */ 1488 #define dbg_restore_debug_regs() 1489 #endif /* ! CONFIG_KGDB */ 1490 1491 static void wait_for_master_cpu(int cpu) 1492 { 1493 #ifdef CONFIG_SMP 1494 /* 1495 * wait for ACK from master CPU before continuing 1496 * with AP initialization 1497 */ 1498 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1499 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1500 cpu_relax(); 1501 #endif 1502 } 1503 1504 /* 1505 * cpu_init() initializes state that is per-CPU. Some data is already 1506 * initialized (naturally) in the bootstrap process, such as the GDT 1507 * and IDT. We reload them nevertheless, this function acts as a 1508 * 'CPU state barrier', nothing should get across. 1509 * A lot of state is already set up in PDA init for 64 bit 1510 */ 1511 #ifdef CONFIG_X86_64 1512 1513 void cpu_init(void) 1514 { 1515 struct orig_ist *oist; 1516 struct task_struct *me; 1517 struct tss_struct *t; 1518 unsigned long v; 1519 int cpu = raw_smp_processor_id(); 1520 int i; 1521 1522 wait_for_master_cpu(cpu); 1523 1524 /* 1525 * Initialize the CR4 shadow before doing anything that could 1526 * try to read it. 1527 */ 1528 cr4_init_shadow(); 1529 1530 if (cpu) 1531 load_ucode_ap(); 1532 1533 t = &per_cpu(cpu_tss, cpu); 1534 oist = &per_cpu(orig_ist, cpu); 1535 1536 #ifdef CONFIG_NUMA 1537 if (this_cpu_read(numa_node) == 0 && 1538 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1539 set_numa_node(early_cpu_to_node(cpu)); 1540 #endif 1541 1542 me = current; 1543 1544 pr_debug("Initializing CPU#%d\n", cpu); 1545 1546 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1547 1548 /* 1549 * Initialize the per-CPU GDT with the boot GDT, 1550 * and set up the GDT descriptor: 1551 */ 1552 1553 switch_to_new_gdt(cpu); 1554 loadsegment(fs, 0); 1555 1556 load_current_idt(); 1557 1558 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1559 syscall_init(); 1560 1561 wrmsrl(MSR_FS_BASE, 0); 1562 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1563 barrier(); 1564 1565 x86_configure_nx(); 1566 x2apic_setup(); 1567 1568 /* 1569 * set up and load the per-CPU TSS 1570 */ 1571 if (!oist->ist[0]) { 1572 char *estacks = per_cpu(exception_stacks, cpu); 1573 1574 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1575 estacks += exception_stack_sizes[v]; 1576 oist->ist[v] = t->x86_tss.ist[v] = 1577 (unsigned long)estacks; 1578 if (v == DEBUG_STACK-1) 1579 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1580 } 1581 } 1582 1583 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1584 1585 /* 1586 * <= is required because the CPU will access up to 1587 * 8 bits beyond the end of the IO permission bitmap. 1588 */ 1589 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1590 t->io_bitmap[i] = ~0UL; 1591 1592 mmgrab(&init_mm); 1593 me->active_mm = &init_mm; 1594 BUG_ON(me->mm); 1595 initialize_tlbstate_and_flush(); 1596 enter_lazy_tlb(&init_mm, me); 1597 1598 /* 1599 * Initialize the TSS. Don't bother initializing sp0, as the initial 1600 * task never enters user mode. 1601 */ 1602 set_tss_desc(cpu, t); 1603 load_TR_desc(); 1604 1605 load_mm_ldt(&init_mm); 1606 1607 clear_all_debug_regs(); 1608 dbg_restore_debug_regs(); 1609 1610 fpu__init_cpu(); 1611 1612 if (is_uv_system()) 1613 uv_cpu_init(); 1614 1615 setup_fixmap_gdt(cpu); 1616 load_fixmap_gdt(cpu); 1617 } 1618 1619 #else 1620 1621 void cpu_init(void) 1622 { 1623 int cpu = smp_processor_id(); 1624 struct task_struct *curr = current; 1625 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1626 1627 wait_for_master_cpu(cpu); 1628 1629 /* 1630 * Initialize the CR4 shadow before doing anything that could 1631 * try to read it. 1632 */ 1633 cr4_init_shadow(); 1634 1635 show_ucode_info_early(); 1636 1637 pr_info("Initializing CPU#%d\n", cpu); 1638 1639 if (cpu_feature_enabled(X86_FEATURE_VME) || 1640 boot_cpu_has(X86_FEATURE_TSC) || 1641 boot_cpu_has(X86_FEATURE_DE)) 1642 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1643 1644 load_current_idt(); 1645 switch_to_new_gdt(cpu); 1646 1647 /* 1648 * Set up and load the per-CPU TSS and LDT 1649 */ 1650 mmgrab(&init_mm); 1651 curr->active_mm = &init_mm; 1652 BUG_ON(curr->mm); 1653 initialize_tlbstate_and_flush(); 1654 enter_lazy_tlb(&init_mm, curr); 1655 1656 /* 1657 * Initialize the TSS. Don't bother initializing sp0, as the initial 1658 * task never enters user mode. 1659 */ 1660 set_tss_desc(cpu, t); 1661 load_TR_desc(); 1662 1663 load_mm_ldt(&init_mm); 1664 1665 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1666 1667 #ifdef CONFIG_DOUBLEFAULT 1668 /* Set up doublefault TSS pointer in the GDT */ 1669 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1670 #endif 1671 1672 clear_all_debug_regs(); 1673 dbg_restore_debug_regs(); 1674 1675 fpu__init_cpu(); 1676 1677 setup_fixmap_gdt(cpu); 1678 load_fixmap_gdt(cpu); 1679 } 1680 #endif 1681 1682 static void bsp_resume(void) 1683 { 1684 if (this_cpu->c_bsp_resume) 1685 this_cpu->c_bsp_resume(&boot_cpu_data); 1686 } 1687 1688 static struct syscore_ops cpu_syscore_ops = { 1689 .resume = bsp_resume, 1690 }; 1691 1692 static int __init init_cpu_syscore(void) 1693 { 1694 register_syscore_ops(&cpu_syscore_ops); 1695 return 0; 1696 } 1697 core_initcall(init_cpu_syscore); 1698