1 #include <linux/init.h> 2 #include <linux/kernel.h> 3 #include <linux/sched.h> 4 #include <linux/string.h> 5 #include <linux/bootmem.h> 6 #include <linux/bitops.h> 7 #include <linux/module.h> 8 #include <linux/kgdb.h> 9 #include <linux/topology.h> 10 #include <linux/delay.h> 11 #include <linux/smp.h> 12 #include <linux/percpu.h> 13 #include <asm/i387.h> 14 #include <asm/msr.h> 15 #include <asm/io.h> 16 #include <asm/linkage.h> 17 #include <asm/mmu_context.h> 18 #include <asm/mtrr.h> 19 #include <asm/mce.h> 20 #include <asm/pat.h> 21 #include <asm/asm.h> 22 #include <asm/numa.h> 23 #include <asm/smp.h> 24 #include <asm/cpu.h> 25 #include <asm/cpumask.h> 26 #include <asm/apic.h> 27 28 #ifdef CONFIG_X86_LOCAL_APIC 29 #include <asm/uv/uv.h> 30 #endif 31 32 #include <asm/pgtable.h> 33 #include <asm/processor.h> 34 #include <asm/desc.h> 35 #include <asm/atomic.h> 36 #include <asm/proto.h> 37 #include <asm/sections.h> 38 #include <asm/setup.h> 39 #include <asm/hypervisor.h> 40 #include <asm/stackprotector.h> 41 42 #include "cpu.h" 43 44 #ifdef CONFIG_X86_64 45 46 /* all of these masks are initialized in setup_cpu_local_masks() */ 47 cpumask_var_t cpu_callin_mask; 48 cpumask_var_t cpu_callout_mask; 49 cpumask_var_t cpu_initialized_mask; 50 51 /* representing cpus for which sibling maps can be computed */ 52 cpumask_var_t cpu_sibling_setup_mask; 53 54 /* correctly size the local cpu masks */ 55 void __init setup_cpu_local_masks(void) 56 { 57 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 58 alloc_bootmem_cpumask_var(&cpu_callin_mask); 59 alloc_bootmem_cpumask_var(&cpu_callout_mask); 60 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 61 } 62 63 #else /* CONFIG_X86_32 */ 64 65 cpumask_t cpu_callin_map; 66 cpumask_t cpu_callout_map; 67 cpumask_t cpu_initialized; 68 cpumask_t cpu_sibling_setup_map; 69 70 #endif /* CONFIG_X86_32 */ 71 72 73 static struct cpu_dev *this_cpu __cpuinitdata; 74 75 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 76 #ifdef CONFIG_X86_64 77 /* 78 * We need valid kernel segments for data and code in long mode too 79 * IRET will check the segment types kkeil 2000/10/28 80 * Also sysret mandates a special GDT layout 81 * 82 * The TLS descriptors are currently at a different place compared to i386. 83 * Hopefully nobody expects them at a fixed place (Wine?) 84 */ 85 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, 86 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, 87 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, 88 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, 89 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, 90 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, 91 #else 92 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 93 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 94 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 95 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 96 /* 97 * Segments used for calling PnP BIOS have byte granularity. 98 * They code segments and data segments have fixed 64k limits, 99 * the transfer segment sizes are set at run time. 100 */ 101 /* 32-bit code */ 102 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 103 /* 16-bit code */ 104 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 105 /* 16-bit data */ 106 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 107 /* 16-bit data */ 108 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 109 /* 16-bit data */ 110 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 111 /* 112 * The APM segments have byte granularity and their bases 113 * are set at run time. All have 64k limits. 114 */ 115 /* 32-bit code */ 116 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 117 /* 16-bit code */ 118 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 119 /* data */ 120 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 121 122 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, 123 [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, 124 GDT_STACK_CANARY_INIT 125 #endif 126 } }; 127 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 128 129 #ifdef CONFIG_X86_32 130 static int cachesize_override __cpuinitdata = -1; 131 static int disable_x86_serial_nr __cpuinitdata = 1; 132 133 static int __init cachesize_setup(char *str) 134 { 135 get_option(&str, &cachesize_override); 136 return 1; 137 } 138 __setup("cachesize=", cachesize_setup); 139 140 static int __init x86_fxsr_setup(char *s) 141 { 142 setup_clear_cpu_cap(X86_FEATURE_FXSR); 143 setup_clear_cpu_cap(X86_FEATURE_XMM); 144 return 1; 145 } 146 __setup("nofxsr", x86_fxsr_setup); 147 148 static int __init x86_sep_setup(char *s) 149 { 150 setup_clear_cpu_cap(X86_FEATURE_SEP); 151 return 1; 152 } 153 __setup("nosep", x86_sep_setup); 154 155 /* Standard macro to see if a specific flag is changeable */ 156 static inline int flag_is_changeable_p(u32 flag) 157 { 158 u32 f1, f2; 159 160 /* 161 * Cyrix and IDT cpus allow disabling of CPUID 162 * so the code below may return different results 163 * when it is executed before and after enabling 164 * the CPUID. Add "volatile" to not allow gcc to 165 * optimize the subsequent calls to this function. 166 */ 167 asm volatile ("pushfl\n\t" 168 "pushfl\n\t" 169 "popl %0\n\t" 170 "movl %0,%1\n\t" 171 "xorl %2,%0\n\t" 172 "pushl %0\n\t" 173 "popfl\n\t" 174 "pushfl\n\t" 175 "popl %0\n\t" 176 "popfl\n\t" 177 : "=&r" (f1), "=&r" (f2) 178 : "ir" (flag)); 179 180 return ((f1^f2) & flag) != 0; 181 } 182 183 /* Probe for the CPUID instruction */ 184 static int __cpuinit have_cpuid_p(void) 185 { 186 return flag_is_changeable_p(X86_EFLAGS_ID); 187 } 188 189 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 190 { 191 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { 192 /* Disable processor serial number */ 193 unsigned long lo, hi; 194 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 195 lo |= 0x200000; 196 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 197 printk(KERN_NOTICE "CPU serial number disabled.\n"); 198 clear_cpu_cap(c, X86_FEATURE_PN); 199 200 /* Disabling the serial number may affect the cpuid level */ 201 c->cpuid_level = cpuid_eax(0); 202 } 203 } 204 205 static int __init x86_serial_nr_setup(char *s) 206 { 207 disable_x86_serial_nr = 0; 208 return 1; 209 } 210 __setup("serialnumber", x86_serial_nr_setup); 211 #else 212 static inline int flag_is_changeable_p(u32 flag) 213 { 214 return 1; 215 } 216 /* Probe for the CPUID instruction */ 217 static inline int have_cpuid_p(void) 218 { 219 return 1; 220 } 221 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 222 { 223 } 224 #endif 225 226 /* 227 * Some CPU features depend on higher CPUID levels, which may not always 228 * be available due to CPUID level capping or broken virtualization 229 * software. Add those features to this table to auto-disable them. 230 */ 231 struct cpuid_dependent_feature { 232 u32 feature; 233 u32 level; 234 }; 235 static const struct cpuid_dependent_feature __cpuinitconst 236 cpuid_dependent_features[] = { 237 { X86_FEATURE_MWAIT, 0x00000005 }, 238 { X86_FEATURE_DCA, 0x00000009 }, 239 { X86_FEATURE_XSAVE, 0x0000000d }, 240 { 0, 0 } 241 }; 242 243 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 244 { 245 const struct cpuid_dependent_feature *df; 246 for (df = cpuid_dependent_features; df->feature; df++) { 247 /* 248 * Note: cpuid_level is set to -1 if unavailable, but 249 * extended_extended_level is set to 0 if unavailable 250 * and the legitimate extended levels are all negative 251 * when signed; hence the weird messing around with 252 * signs here... 253 */ 254 if (cpu_has(c, df->feature) && 255 ((s32)df->level < 0 ? 256 (u32)df->level > (u32)c->extended_cpuid_level : 257 (s32)df->level > (s32)c->cpuid_level)) { 258 clear_cpu_cap(c, df->feature); 259 if (warn) 260 printk(KERN_WARNING 261 "CPU: CPU feature %s disabled " 262 "due to lack of CPUID level 0x%x\n", 263 x86_cap_flags[df->feature], 264 df->level); 265 } 266 } 267 } 268 269 /* 270 * Naming convention should be: <Name> [(<Codename>)] 271 * This table only is used unless init_<vendor>() below doesn't set it; 272 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used 273 * 274 */ 275 276 /* Look up CPU names by table lookup. */ 277 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) 278 { 279 struct cpu_model_info *info; 280 281 if (c->x86_model >= 16) 282 return NULL; /* Range check */ 283 284 if (!this_cpu) 285 return NULL; 286 287 info = this_cpu->c_models; 288 289 while (info && info->family) { 290 if (info->family == c->x86) 291 return info->model_names[c->x86_model]; 292 info++; 293 } 294 return NULL; /* Not found */ 295 } 296 297 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; 298 299 void load_percpu_segment(int cpu) 300 { 301 #ifdef CONFIG_X86_32 302 loadsegment(fs, __KERNEL_PERCPU); 303 #else 304 loadsegment(gs, 0); 305 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 306 #endif 307 load_stack_canary_segment(); 308 } 309 310 /* Current gdt points %fs at the "master" per-cpu area: after this, 311 * it's on the real one. */ 312 void switch_to_new_gdt(int cpu) 313 { 314 struct desc_ptr gdt_descr; 315 316 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 317 gdt_descr.size = GDT_SIZE - 1; 318 load_gdt(&gdt_descr); 319 /* Reload the per-cpu base */ 320 321 load_percpu_segment(cpu); 322 } 323 324 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 325 326 static void __cpuinit default_init(struct cpuinfo_x86 *c) 327 { 328 #ifdef CONFIG_X86_64 329 display_cacheinfo(c); 330 #else 331 /* Not much we can do here... */ 332 /* Check if at least it has cpuid */ 333 if (c->cpuid_level == -1) { 334 /* No cpuid. It must be an ancient CPU */ 335 if (c->x86 == 4) 336 strcpy(c->x86_model_id, "486"); 337 else if (c->x86 == 3) 338 strcpy(c->x86_model_id, "386"); 339 } 340 #endif 341 } 342 343 static struct cpu_dev __cpuinitdata default_cpu = { 344 .c_init = default_init, 345 .c_vendor = "Unknown", 346 .c_x86_vendor = X86_VENDOR_UNKNOWN, 347 }; 348 349 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 350 { 351 unsigned int *v; 352 char *p, *q; 353 354 if (c->extended_cpuid_level < 0x80000004) 355 return; 356 357 v = (unsigned int *) c->x86_model_id; 358 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 359 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 360 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 361 c->x86_model_id[48] = 0; 362 363 /* Intel chips right-justify this string for some dumb reason; 364 undo that brain damage */ 365 p = q = &c->x86_model_id[0]; 366 while (*p == ' ') 367 p++; 368 if (p != q) { 369 while (*p) 370 *q++ = *p++; 371 while (q <= &c->x86_model_id[48]) 372 *q++ = '\0'; /* Zero-pad the rest */ 373 } 374 } 375 376 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 377 { 378 unsigned int n, dummy, ebx, ecx, edx, l2size; 379 380 n = c->extended_cpuid_level; 381 382 if (n >= 0x80000005) { 383 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 384 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 385 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 386 c->x86_cache_size = (ecx>>24) + (edx>>24); 387 #ifdef CONFIG_X86_64 388 /* On K8 L1 TLB is inclusive, so don't count it */ 389 c->x86_tlbsize = 0; 390 #endif 391 } 392 393 if (n < 0x80000006) /* Some chips just has a large L1. */ 394 return; 395 396 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 397 l2size = ecx >> 16; 398 399 #ifdef CONFIG_X86_64 400 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 401 #else 402 /* do processor-specific cache resizing */ 403 if (this_cpu->c_size_cache) 404 l2size = this_cpu->c_size_cache(c, l2size); 405 406 /* Allow user to override all this if necessary. */ 407 if (cachesize_override != -1) 408 l2size = cachesize_override; 409 410 if (l2size == 0) 411 return; /* Again, no L2 cache is possible */ 412 #endif 413 414 c->x86_cache_size = l2size; 415 416 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 417 l2size, ecx & 0xFF); 418 } 419 420 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 421 { 422 #ifdef CONFIG_X86_HT 423 u32 eax, ebx, ecx, edx; 424 int index_msb, core_bits; 425 426 if (!cpu_has(c, X86_FEATURE_HT)) 427 return; 428 429 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 430 goto out; 431 432 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 433 return; 434 435 cpuid(1, &eax, &ebx, &ecx, &edx); 436 437 smp_num_siblings = (ebx & 0xff0000) >> 16; 438 439 if (smp_num_siblings == 1) { 440 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 441 } else if (smp_num_siblings > 1) { 442 443 if (smp_num_siblings > nr_cpu_ids) { 444 printk(KERN_WARNING "CPU: Unsupported number of siblings %d", 445 smp_num_siblings); 446 smp_num_siblings = 1; 447 return; 448 } 449 450 index_msb = get_count_order(smp_num_siblings); 451 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 452 453 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 454 455 index_msb = get_count_order(smp_num_siblings); 456 457 core_bits = get_count_order(c->x86_max_cores); 458 459 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 460 ((1 << core_bits) - 1); 461 } 462 463 out: 464 if ((c->x86_max_cores * smp_num_siblings) > 1) { 465 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 466 c->phys_proc_id); 467 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 468 c->cpu_core_id); 469 } 470 #endif 471 } 472 473 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 474 { 475 char *v = c->x86_vendor_id; 476 int i; 477 static int printed; 478 479 for (i = 0; i < X86_VENDOR_NUM; i++) { 480 if (!cpu_devs[i]) 481 break; 482 483 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 484 (cpu_devs[i]->c_ident[1] && 485 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 486 this_cpu = cpu_devs[i]; 487 c->x86_vendor = this_cpu->c_x86_vendor; 488 return; 489 } 490 } 491 492 if (!printed) { 493 printed++; 494 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); 495 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 496 } 497 498 c->x86_vendor = X86_VENDOR_UNKNOWN; 499 this_cpu = &default_cpu; 500 } 501 502 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 503 { 504 /* Get vendor name */ 505 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 506 (unsigned int *)&c->x86_vendor_id[0], 507 (unsigned int *)&c->x86_vendor_id[8], 508 (unsigned int *)&c->x86_vendor_id[4]); 509 510 c->x86 = 4; 511 /* Intel-defined flags: level 0x00000001 */ 512 if (c->cpuid_level >= 0x00000001) { 513 u32 junk, tfms, cap0, misc; 514 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 515 c->x86 = (tfms >> 8) & 0xf; 516 c->x86_model = (tfms >> 4) & 0xf; 517 c->x86_mask = tfms & 0xf; 518 if (c->x86 == 0xf) 519 c->x86 += (tfms >> 20) & 0xff; 520 if (c->x86 >= 0x6) 521 c->x86_model += ((tfms >> 16) & 0xf) << 4; 522 if (cap0 & (1<<19)) { 523 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 524 c->x86_cache_alignment = c->x86_clflush_size; 525 } 526 } 527 } 528 529 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 530 { 531 u32 tfms, xlvl; 532 u32 ebx; 533 534 /* Intel-defined flags: level 0x00000001 */ 535 if (c->cpuid_level >= 0x00000001) { 536 u32 capability, excap; 537 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 538 c->x86_capability[0] = capability; 539 c->x86_capability[4] = excap; 540 } 541 542 /* AMD-defined flags: level 0x80000001 */ 543 xlvl = cpuid_eax(0x80000000); 544 c->extended_cpuid_level = xlvl; 545 if ((xlvl & 0xffff0000) == 0x80000000) { 546 if (xlvl >= 0x80000001) { 547 c->x86_capability[1] = cpuid_edx(0x80000001); 548 c->x86_capability[6] = cpuid_ecx(0x80000001); 549 } 550 } 551 552 #ifdef CONFIG_X86_64 553 if (c->extended_cpuid_level >= 0x80000008) { 554 u32 eax = cpuid_eax(0x80000008); 555 556 c->x86_virt_bits = (eax >> 8) & 0xff; 557 c->x86_phys_bits = eax & 0xff; 558 } 559 #endif 560 561 if (c->extended_cpuid_level >= 0x80000007) 562 c->x86_power = cpuid_edx(0x80000007); 563 564 } 565 566 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 567 { 568 #ifdef CONFIG_X86_32 569 int i; 570 571 /* 572 * First of all, decide if this is a 486 or higher 573 * It's a 486 if we can modify the AC flag 574 */ 575 if (flag_is_changeable_p(X86_EFLAGS_AC)) 576 c->x86 = 4; 577 else 578 c->x86 = 3; 579 580 for (i = 0; i < X86_VENDOR_NUM; i++) 581 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 582 c->x86_vendor_id[0] = 0; 583 cpu_devs[i]->c_identify(c); 584 if (c->x86_vendor_id[0]) { 585 get_cpu_vendor(c); 586 break; 587 } 588 } 589 #endif 590 } 591 592 /* 593 * Do minimum CPU detection early. 594 * Fields really needed: vendor, cpuid_level, family, model, mask, 595 * cache alignment. 596 * The others are not touched to avoid unwanted side effects. 597 * 598 * WARNING: this function is only called on the BP. Don't add code here 599 * that is supposed to run on all CPUs. 600 */ 601 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 602 { 603 #ifdef CONFIG_X86_64 604 c->x86_clflush_size = 64; 605 #else 606 c->x86_clflush_size = 32; 607 #endif 608 c->x86_cache_alignment = c->x86_clflush_size; 609 610 memset(&c->x86_capability, 0, sizeof c->x86_capability); 611 c->extended_cpuid_level = 0; 612 613 if (!have_cpuid_p()) 614 identify_cpu_without_cpuid(c); 615 616 /* cyrix could have cpuid enabled via c_identify()*/ 617 if (!have_cpuid_p()) 618 return; 619 620 cpu_detect(c); 621 622 get_cpu_vendor(c); 623 624 get_cpu_cap(c); 625 626 if (this_cpu->c_early_init) 627 this_cpu->c_early_init(c); 628 629 #ifdef CONFIG_SMP 630 c->cpu_index = boot_cpu_id; 631 #endif 632 filter_cpuid_features(c, false); 633 } 634 635 void __init early_cpu_init(void) 636 { 637 struct cpu_dev **cdev; 638 int count = 0; 639 640 printk("KERNEL supported cpus:\n"); 641 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 642 struct cpu_dev *cpudev = *cdev; 643 unsigned int j; 644 645 if (count >= X86_VENDOR_NUM) 646 break; 647 cpu_devs[count] = cpudev; 648 count++; 649 650 for (j = 0; j < 2; j++) { 651 if (!cpudev->c_ident[j]) 652 continue; 653 printk(" %s %s\n", cpudev->c_vendor, 654 cpudev->c_ident[j]); 655 } 656 } 657 658 early_identify_cpu(&boot_cpu_data); 659 } 660 661 /* 662 * The NOPL instruction is supposed to exist on all CPUs with 663 * family >= 6; unfortunately, that's not true in practice because 664 * of early VIA chips and (more importantly) broken virtualizers that 665 * are not easy to detect. In the latter case it doesn't even *fail* 666 * reliably, so probing for it doesn't even work. Disable it completely 667 * unless we can find a reliable way to detect all the broken cases. 668 */ 669 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 670 { 671 clear_cpu_cap(c, X86_FEATURE_NOPL); 672 } 673 674 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 675 { 676 c->extended_cpuid_level = 0; 677 678 if (!have_cpuid_p()) 679 identify_cpu_without_cpuid(c); 680 681 /* cyrix could have cpuid enabled via c_identify()*/ 682 if (!have_cpuid_p()) 683 return; 684 685 cpu_detect(c); 686 687 get_cpu_vendor(c); 688 689 get_cpu_cap(c); 690 691 if (c->cpuid_level >= 0x00000001) { 692 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 693 #ifdef CONFIG_X86_32 694 # ifdef CONFIG_X86_HT 695 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 696 # else 697 c->apicid = c->initial_apicid; 698 # endif 699 #endif 700 701 #ifdef CONFIG_X86_HT 702 c->phys_proc_id = c->initial_apicid; 703 #endif 704 } 705 706 get_model_name(c); /* Default name */ 707 708 init_scattered_cpuid_features(c); 709 detect_nopl(c); 710 } 711 712 /* 713 * This does the hard work of actually picking apart the CPU stuff... 714 */ 715 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 716 { 717 int i; 718 719 c->loops_per_jiffy = loops_per_jiffy; 720 c->x86_cache_size = -1; 721 c->x86_vendor = X86_VENDOR_UNKNOWN; 722 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 723 c->x86_vendor_id[0] = '\0'; /* Unset */ 724 c->x86_model_id[0] = '\0'; /* Unset */ 725 c->x86_max_cores = 1; 726 c->x86_coreid_bits = 0; 727 #ifdef CONFIG_X86_64 728 c->x86_clflush_size = 64; 729 #else 730 c->cpuid_level = -1; /* CPUID not detected */ 731 c->x86_clflush_size = 32; 732 #endif 733 c->x86_cache_alignment = c->x86_clflush_size; 734 memset(&c->x86_capability, 0, sizeof c->x86_capability); 735 736 generic_identify(c); 737 738 if (this_cpu->c_identify) 739 this_cpu->c_identify(c); 740 741 #ifdef CONFIG_X86_64 742 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 743 #endif 744 745 /* 746 * Vendor-specific initialization. In this section we 747 * canonicalize the feature flags, meaning if there are 748 * features a certain CPU supports which CPUID doesn't 749 * tell us, CPUID claiming incorrect flags, or other bugs, 750 * we handle them here. 751 * 752 * At the end of this section, c->x86_capability better 753 * indicate the features this CPU genuinely supports! 754 */ 755 if (this_cpu->c_init) 756 this_cpu->c_init(c); 757 758 /* Disable the PN if appropriate */ 759 squash_the_stupid_serial_number(c); 760 761 /* 762 * The vendor-specific functions might have changed features. Now 763 * we do "generic changes." 764 */ 765 766 /* Filter out anything that depends on CPUID levels we don't have */ 767 filter_cpuid_features(c, true); 768 769 /* If the model name is still unset, do table lookup. */ 770 if (!c->x86_model_id[0]) { 771 char *p; 772 p = table_lookup_model(c); 773 if (p) 774 strcpy(c->x86_model_id, p); 775 else 776 /* Last resort... */ 777 sprintf(c->x86_model_id, "%02x/%02x", 778 c->x86, c->x86_model); 779 } 780 781 #ifdef CONFIG_X86_64 782 detect_ht(c); 783 #endif 784 785 init_hypervisor(c); 786 /* 787 * On SMP, boot_cpu_data holds the common feature set between 788 * all CPUs; so make sure that we indicate which features are 789 * common between the CPUs. The first time this routine gets 790 * executed, c == &boot_cpu_data. 791 */ 792 if (c != &boot_cpu_data) { 793 /* AND the already accumulated flags with these */ 794 for (i = 0; i < NCAPINTS; i++) 795 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 796 } 797 798 /* Clear all flags overriden by options */ 799 for (i = 0; i < NCAPINTS; i++) 800 c->x86_capability[i] &= ~cleared_cpu_caps[i]; 801 802 #ifdef CONFIG_X86_MCE 803 /* Init Machine Check Exception if available. */ 804 mcheck_init(c); 805 #endif 806 807 select_idle_routine(c); 808 809 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 810 numa_add_cpu(smp_processor_id()); 811 #endif 812 } 813 814 #ifdef CONFIG_X86_64 815 static void vgetcpu_set_mode(void) 816 { 817 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 818 vgetcpu_mode = VGETCPU_RDTSCP; 819 else 820 vgetcpu_mode = VGETCPU_LSL; 821 } 822 #endif 823 824 void __init identify_boot_cpu(void) 825 { 826 identify_cpu(&boot_cpu_data); 827 #ifdef CONFIG_X86_32 828 sysenter_setup(); 829 enable_sep_cpu(); 830 #else 831 vgetcpu_set_mode(); 832 #endif 833 } 834 835 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 836 { 837 BUG_ON(c == &boot_cpu_data); 838 identify_cpu(c); 839 #ifdef CONFIG_X86_32 840 enable_sep_cpu(); 841 #endif 842 mtrr_ap_init(); 843 } 844 845 struct msr_range { 846 unsigned min; 847 unsigned max; 848 }; 849 850 static struct msr_range msr_range_array[] __cpuinitdata = { 851 { 0x00000000, 0x00000418}, 852 { 0xc0000000, 0xc000040b}, 853 { 0xc0010000, 0xc0010142}, 854 { 0xc0011000, 0xc001103b}, 855 }; 856 857 static void __cpuinit print_cpu_msr(void) 858 { 859 unsigned index; 860 u64 val; 861 int i; 862 unsigned index_min, index_max; 863 864 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 865 index_min = msr_range_array[i].min; 866 index_max = msr_range_array[i].max; 867 for (index = index_min; index < index_max; index++) { 868 if (rdmsrl_amd_safe(index, &val)) 869 continue; 870 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 871 } 872 } 873 } 874 875 static int show_msr __cpuinitdata; 876 static __init int setup_show_msr(char *arg) 877 { 878 int num; 879 880 get_option(&arg, &num); 881 882 if (num > 0) 883 show_msr = num; 884 return 1; 885 } 886 __setup("show_msr=", setup_show_msr); 887 888 static __init int setup_noclflush(char *arg) 889 { 890 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 891 return 1; 892 } 893 __setup("noclflush", setup_noclflush); 894 895 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 896 { 897 char *vendor = NULL; 898 899 if (c->x86_vendor < X86_VENDOR_NUM) 900 vendor = this_cpu->c_vendor; 901 else if (c->cpuid_level >= 0) 902 vendor = c->x86_vendor_id; 903 904 if (vendor && !strstr(c->x86_model_id, vendor)) 905 printk(KERN_CONT "%s ", vendor); 906 907 if (c->x86_model_id[0]) 908 printk(KERN_CONT "%s", c->x86_model_id); 909 else 910 printk(KERN_CONT "%d86", c->x86); 911 912 if (c->x86_mask || c->cpuid_level >= 0) 913 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 914 else 915 printk(KERN_CONT "\n"); 916 917 #ifdef CONFIG_SMP 918 if (c->cpu_index < show_msr) 919 print_cpu_msr(); 920 #else 921 if (show_msr) 922 print_cpu_msr(); 923 #endif 924 } 925 926 static __init int setup_disablecpuid(char *arg) 927 { 928 int bit; 929 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 930 setup_clear_cpu_cap(bit); 931 else 932 return 0; 933 return 1; 934 } 935 __setup("clearcpuid=", setup_disablecpuid); 936 937 #ifdef CONFIG_X86_64 938 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; 939 940 DEFINE_PER_CPU_FIRST(union irq_stack_union, 941 irq_stack_union) __aligned(PAGE_SIZE); 942 DEFINE_PER_CPU(char *, irq_stack_ptr) = 943 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 944 945 DEFINE_PER_CPU(unsigned long, kernel_stack) = 946 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 947 EXPORT_PER_CPU_SYMBOL(kernel_stack); 948 949 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 950 951 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 952 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) 953 __aligned(PAGE_SIZE); 954 955 extern asmlinkage void ignore_sysret(void); 956 957 /* May not be marked __init: used by software suspend */ 958 void syscall_init(void) 959 { 960 /* 961 * LSTAR and STAR live in a bit strange symbiosis. 962 * They both write to the same internal register. STAR allows to 963 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 964 */ 965 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 966 wrmsrl(MSR_LSTAR, system_call); 967 wrmsrl(MSR_CSTAR, ignore_sysret); 968 969 #ifdef CONFIG_IA32_EMULATION 970 syscall32_cpu_init(); 971 #endif 972 973 /* Flags to clear on syscall */ 974 wrmsrl(MSR_SYSCALL_MASK, 975 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 976 } 977 978 unsigned long kernel_eflags; 979 980 /* 981 * Copies of the original ist values from the tss are only accessed during 982 * debugging, no special alignment required. 983 */ 984 DEFINE_PER_CPU(struct orig_ist, orig_ist); 985 986 #else /* x86_64 */ 987 988 #ifdef CONFIG_CC_STACKPROTECTOR 989 DEFINE_PER_CPU(unsigned long, stack_canary); 990 #endif 991 992 /* Make sure %fs and %gs are initialized properly in idle threads */ 993 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 994 { 995 memset(regs, 0, sizeof(struct pt_regs)); 996 regs->fs = __KERNEL_PERCPU; 997 regs->gs = __KERNEL_STACK_CANARY; 998 return regs; 999 } 1000 #endif /* x86_64 */ 1001 1002 /* 1003 * cpu_init() initializes state that is per-CPU. Some data is already 1004 * initialized (naturally) in the bootstrap process, such as the GDT 1005 * and IDT. We reload them nevertheless, this function acts as a 1006 * 'CPU state barrier', nothing should get across. 1007 * A lot of state is already set up in PDA init for 64 bit 1008 */ 1009 #ifdef CONFIG_X86_64 1010 void __cpuinit cpu_init(void) 1011 { 1012 int cpu = stack_smp_processor_id(); 1013 struct tss_struct *t = &per_cpu(init_tss, cpu); 1014 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); 1015 unsigned long v; 1016 struct task_struct *me; 1017 int i; 1018 1019 #ifdef CONFIG_NUMA 1020 if (cpu != 0 && percpu_read(node_number) == 0 && 1021 cpu_to_node(cpu) != NUMA_NO_NODE) 1022 percpu_write(node_number, cpu_to_node(cpu)); 1023 #endif 1024 1025 me = current; 1026 1027 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1028 panic("CPU#%d already initialized!\n", cpu); 1029 1030 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1031 1032 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1033 1034 /* 1035 * Initialize the per-CPU GDT with the boot GDT, 1036 * and set up the GDT descriptor: 1037 */ 1038 1039 switch_to_new_gdt(cpu); 1040 loadsegment(fs, 0); 1041 1042 load_idt((const struct desc_ptr *)&idt_descr); 1043 1044 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1045 syscall_init(); 1046 1047 wrmsrl(MSR_FS_BASE, 0); 1048 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1049 barrier(); 1050 1051 check_efer(); 1052 if (cpu != 0) 1053 enable_x2apic(); 1054 1055 /* 1056 * set up and load the per-CPU TSS 1057 */ 1058 if (!orig_ist->ist[0]) { 1059 static const unsigned int sizes[N_EXCEPTION_STACKS] = { 1060 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1061 [DEBUG_STACK - 1] = DEBUG_STKSZ 1062 }; 1063 char *estacks = per_cpu(exception_stacks, cpu); 1064 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1065 estacks += sizes[v]; 1066 orig_ist->ist[v] = t->x86_tss.ist[v] = 1067 (unsigned long)estacks; 1068 } 1069 } 1070 1071 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1072 /* 1073 * <= is required because the CPU will access up to 1074 * 8 bits beyond the end of the IO permission bitmap. 1075 */ 1076 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1077 t->io_bitmap[i] = ~0UL; 1078 1079 atomic_inc(&init_mm.mm_count); 1080 me->active_mm = &init_mm; 1081 if (me->mm) 1082 BUG(); 1083 enter_lazy_tlb(&init_mm, me); 1084 1085 load_sp0(t, ¤t->thread); 1086 set_tss_desc(cpu, t); 1087 load_TR_desc(); 1088 load_LDT(&init_mm.context); 1089 1090 #ifdef CONFIG_KGDB 1091 /* 1092 * If the kgdb is connected no debug regs should be altered. This 1093 * is only applicable when KGDB and a KGDB I/O module are built 1094 * into the kernel and you are using early debugging with 1095 * kgdbwait. KGDB will control the kernel HW breakpoint registers. 1096 */ 1097 if (kgdb_connected && arch_kgdb_ops.correct_hw_break) 1098 arch_kgdb_ops.correct_hw_break(); 1099 else 1100 #endif 1101 { 1102 /* 1103 * Clear all 6 debug registers: 1104 */ 1105 set_debugreg(0UL, 0); 1106 set_debugreg(0UL, 1); 1107 set_debugreg(0UL, 2); 1108 set_debugreg(0UL, 3); 1109 set_debugreg(0UL, 6); 1110 set_debugreg(0UL, 7); 1111 } 1112 1113 fpu_init(); 1114 1115 raw_local_save_flags(kernel_eflags); 1116 1117 if (is_uv_system()) 1118 uv_cpu_init(); 1119 } 1120 1121 #else 1122 1123 void __cpuinit cpu_init(void) 1124 { 1125 int cpu = smp_processor_id(); 1126 struct task_struct *curr = current; 1127 struct tss_struct *t = &per_cpu(init_tss, cpu); 1128 struct thread_struct *thread = &curr->thread; 1129 1130 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1131 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1132 for (;;) local_irq_enable(); 1133 } 1134 1135 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1136 1137 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1138 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1139 1140 load_idt(&idt_descr); 1141 switch_to_new_gdt(cpu); 1142 1143 /* 1144 * Set up and load the per-CPU TSS and LDT 1145 */ 1146 atomic_inc(&init_mm.mm_count); 1147 curr->active_mm = &init_mm; 1148 if (curr->mm) 1149 BUG(); 1150 enter_lazy_tlb(&init_mm, curr); 1151 1152 load_sp0(t, thread); 1153 set_tss_desc(cpu, t); 1154 load_TR_desc(); 1155 load_LDT(&init_mm.context); 1156 1157 #ifdef CONFIG_DOUBLEFAULT 1158 /* Set up doublefault TSS pointer in the GDT */ 1159 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1160 #endif 1161 1162 /* Clear all 6 debug registers: */ 1163 set_debugreg(0, 0); 1164 set_debugreg(0, 1); 1165 set_debugreg(0, 2); 1166 set_debugreg(0, 3); 1167 set_debugreg(0, 6); 1168 set_debugreg(0, 7); 1169 1170 /* 1171 * Force FPU initialization: 1172 */ 1173 if (cpu_has_xsave) 1174 current_thread_info()->status = TS_XSAVE; 1175 else 1176 current_thread_info()->status = 0; 1177 clear_used_math(); 1178 mxcsr_feature_mask_init(); 1179 1180 /* 1181 * Boot processor to setup the FP and extended state context info. 1182 */ 1183 if (smp_processor_id() == boot_cpu_id) 1184 init_thread_xstate(); 1185 1186 xsave_init(); 1187 } 1188 1189 1190 #endif 1191