1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/init.h> 18 #include <linux/kprobes.h> 19 #include <linux/kgdb.h> 20 #include <linux/smp.h> 21 #include <linux/io.h> 22 #include <linux/syscore_ops.h> 23 24 #include <asm/stackprotector.h> 25 #include <asm/perf_event.h> 26 #include <asm/mmu_context.h> 27 #include <asm/archrandom.h> 28 #include <asm/hypervisor.h> 29 #include <asm/processor.h> 30 #include <asm/tlbflush.h> 31 #include <asm/debugreg.h> 32 #include <asm/sections.h> 33 #include <asm/vsyscall.h> 34 #include <linux/topology.h> 35 #include <linux/cpumask.h> 36 #include <asm/pgtable.h> 37 #include <linux/atomic.h> 38 #include <asm/proto.h> 39 #include <asm/setup.h> 40 #include <asm/apic.h> 41 #include <asm/desc.h> 42 #include <asm/fpu/internal.h> 43 #include <asm/mtrr.h> 44 #include <asm/hwcap2.h> 45 #include <linux/numa.h> 46 #include <asm/asm.h> 47 #include <asm/bugs.h> 48 #include <asm/cpu.h> 49 #include <asm/mce.h> 50 #include <asm/msr.h> 51 #include <asm/pat.h> 52 #include <asm/microcode.h> 53 #include <asm/microcode_intel.h> 54 #include <asm/intel-family.h> 55 #include <asm/cpu_device_id.h> 56 57 #ifdef CONFIG_X86_LOCAL_APIC 58 #include <asm/uv/uv.h> 59 #endif 60 61 #include "cpu.h" 62 63 u32 elf_hwcap2 __read_mostly; 64 65 /* all of these masks are initialized in setup_cpu_local_masks() */ 66 cpumask_var_t cpu_initialized_mask; 67 cpumask_var_t cpu_callout_mask; 68 cpumask_var_t cpu_callin_mask; 69 70 /* representing cpus for which sibling maps can be computed */ 71 cpumask_var_t cpu_sibling_setup_mask; 72 73 /* Number of siblings per CPU package */ 74 int smp_num_siblings = 1; 75 EXPORT_SYMBOL(smp_num_siblings); 76 77 /* Last level cache ID of each logical CPU */ 78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 79 80 /* correctly size the local cpu masks */ 81 void __init setup_cpu_local_masks(void) 82 { 83 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 84 alloc_bootmem_cpumask_var(&cpu_callin_mask); 85 alloc_bootmem_cpumask_var(&cpu_callout_mask); 86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 87 } 88 89 static void default_init(struct cpuinfo_x86 *c) 90 { 91 #ifdef CONFIG_X86_64 92 cpu_detect_cache_sizes(c); 93 #else 94 /* Not much we can do here... */ 95 /* Check if at least it has cpuid */ 96 if (c->cpuid_level == -1) { 97 /* No cpuid. It must be an ancient CPU */ 98 if (c->x86 == 4) 99 strcpy(c->x86_model_id, "486"); 100 else if (c->x86 == 3) 101 strcpy(c->x86_model_id, "386"); 102 } 103 #endif 104 } 105 106 static const struct cpu_dev default_cpu = { 107 .c_init = default_init, 108 .c_vendor = "Unknown", 109 .c_x86_vendor = X86_VENDOR_UNKNOWN, 110 }; 111 112 static const struct cpu_dev *this_cpu = &default_cpu; 113 114 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 115 #ifdef CONFIG_X86_64 116 /* 117 * We need valid kernel segments for data and code in long mode too 118 * IRET will check the segment types kkeil 2000/10/28 119 * Also sysret mandates a special GDT layout 120 * 121 * TLS descriptors are currently at a different place compared to i386. 122 * Hopefully nobody expects them at a fixed place (Wine?) 123 */ 124 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 125 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 126 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 128 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 130 #else 131 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 132 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 133 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 134 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 135 /* 136 * Segments used for calling PnP BIOS have byte granularity. 137 * They code segments and data segments have fixed 64k limits, 138 * the transfer segment sizes are set at run time. 139 */ 140 /* 32-bit code */ 141 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 142 /* 16-bit code */ 143 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 144 /* 16-bit data */ 145 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 146 /* 16-bit data */ 147 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 148 /* 16-bit data */ 149 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 150 /* 151 * The APM segments have byte granularity and their bases 152 * are set at run time. All have 64k limits. 153 */ 154 /* 32-bit code */ 155 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 156 /* 16-bit code */ 157 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 158 /* data */ 159 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 160 161 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 162 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 163 GDT_STACK_CANARY_INIT 164 #endif 165 } }; 166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 167 168 static int __init x86_mpx_setup(char *s) 169 { 170 /* require an exact match without trailing characters */ 171 if (strlen(s)) 172 return 0; 173 174 /* do not emit a message if the feature is not present */ 175 if (!boot_cpu_has(X86_FEATURE_MPX)) 176 return 1; 177 178 setup_clear_cpu_cap(X86_FEATURE_MPX); 179 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 180 return 1; 181 } 182 __setup("nompx", x86_mpx_setup); 183 184 #ifdef CONFIG_X86_64 185 static int __init x86_nopcid_setup(char *s) 186 { 187 /* nopcid doesn't accept parameters */ 188 if (s) 189 return -EINVAL; 190 191 /* do not emit a message if the feature is not present */ 192 if (!boot_cpu_has(X86_FEATURE_PCID)) 193 return 0; 194 195 setup_clear_cpu_cap(X86_FEATURE_PCID); 196 pr_info("nopcid: PCID feature disabled\n"); 197 return 0; 198 } 199 early_param("nopcid", x86_nopcid_setup); 200 #endif 201 202 static int __init x86_noinvpcid_setup(char *s) 203 { 204 /* noinvpcid doesn't accept parameters */ 205 if (s) 206 return -EINVAL; 207 208 /* do not emit a message if the feature is not present */ 209 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 210 return 0; 211 212 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 213 pr_info("noinvpcid: INVPCID feature disabled\n"); 214 return 0; 215 } 216 early_param("noinvpcid", x86_noinvpcid_setup); 217 218 #ifdef CONFIG_X86_32 219 static int cachesize_override = -1; 220 static int disable_x86_serial_nr = 1; 221 222 static int __init cachesize_setup(char *str) 223 { 224 get_option(&str, &cachesize_override); 225 return 1; 226 } 227 __setup("cachesize=", cachesize_setup); 228 229 static int __init x86_sep_setup(char *s) 230 { 231 setup_clear_cpu_cap(X86_FEATURE_SEP); 232 return 1; 233 } 234 __setup("nosep", x86_sep_setup); 235 236 /* Standard macro to see if a specific flag is changeable */ 237 static inline int flag_is_changeable_p(u32 flag) 238 { 239 u32 f1, f2; 240 241 /* 242 * Cyrix and IDT cpus allow disabling of CPUID 243 * so the code below may return different results 244 * when it is executed before and after enabling 245 * the CPUID. Add "volatile" to not allow gcc to 246 * optimize the subsequent calls to this function. 247 */ 248 asm volatile ("pushfl \n\t" 249 "pushfl \n\t" 250 "popl %0 \n\t" 251 "movl %0, %1 \n\t" 252 "xorl %2, %0 \n\t" 253 "pushl %0 \n\t" 254 "popfl \n\t" 255 "pushfl \n\t" 256 "popl %0 \n\t" 257 "popfl \n\t" 258 259 : "=&r" (f1), "=&r" (f2) 260 : "ir" (flag)); 261 262 return ((f1^f2) & flag) != 0; 263 } 264 265 /* Probe for the CPUID instruction */ 266 int have_cpuid_p(void) 267 { 268 return flag_is_changeable_p(X86_EFLAGS_ID); 269 } 270 271 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 272 { 273 unsigned long lo, hi; 274 275 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 276 return; 277 278 /* Disable processor serial number: */ 279 280 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 281 lo |= 0x200000; 282 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 283 284 pr_notice("CPU serial number disabled.\n"); 285 clear_cpu_cap(c, X86_FEATURE_PN); 286 287 /* Disabling the serial number may affect the cpuid level */ 288 c->cpuid_level = cpuid_eax(0); 289 } 290 291 static int __init x86_serial_nr_setup(char *s) 292 { 293 disable_x86_serial_nr = 0; 294 return 1; 295 } 296 __setup("serialnumber", x86_serial_nr_setup); 297 #else 298 static inline int flag_is_changeable_p(u32 flag) 299 { 300 return 1; 301 } 302 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 303 { 304 } 305 #endif 306 307 static __init int setup_disable_smep(char *arg) 308 { 309 setup_clear_cpu_cap(X86_FEATURE_SMEP); 310 /* Check for things that depend on SMEP being enabled: */ 311 check_mpx_erratum(&boot_cpu_data); 312 return 1; 313 } 314 __setup("nosmep", setup_disable_smep); 315 316 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 317 { 318 if (cpu_has(c, X86_FEATURE_SMEP)) 319 cr4_set_bits(X86_CR4_SMEP); 320 } 321 322 static __init int setup_disable_smap(char *arg) 323 { 324 setup_clear_cpu_cap(X86_FEATURE_SMAP); 325 return 1; 326 } 327 __setup("nosmap", setup_disable_smap); 328 329 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 330 { 331 unsigned long eflags = native_save_fl(); 332 333 /* This should have been cleared long ago */ 334 BUG_ON(eflags & X86_EFLAGS_AC); 335 336 if (cpu_has(c, X86_FEATURE_SMAP)) { 337 #ifdef CONFIG_X86_SMAP 338 cr4_set_bits(X86_CR4_SMAP); 339 #else 340 cr4_clear_bits(X86_CR4_SMAP); 341 #endif 342 } 343 } 344 345 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 346 { 347 /* Check the boot processor, plus build option for UMIP. */ 348 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 349 goto out; 350 351 /* Check the current processor's cpuid bits. */ 352 if (!cpu_has(c, X86_FEATURE_UMIP)) 353 goto out; 354 355 cr4_set_bits(X86_CR4_UMIP); 356 357 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 358 359 return; 360 361 out: 362 /* 363 * Make sure UMIP is disabled in case it was enabled in a 364 * previous boot (e.g., via kexec). 365 */ 366 cr4_clear_bits(X86_CR4_UMIP); 367 } 368 369 DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 370 EXPORT_SYMBOL(cr_pinning); 371 unsigned long cr4_pinned_bits __ro_after_init; 372 EXPORT_SYMBOL(cr4_pinned_bits); 373 374 /* 375 * Once CPU feature detection is finished (and boot params have been 376 * parsed), record any of the sensitive CR bits that are set, and 377 * enable CR pinning. 378 */ 379 static void __init setup_cr_pinning(void) 380 { 381 unsigned long mask; 382 383 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); 384 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; 385 static_key_enable(&cr_pinning.key); 386 } 387 388 /* 389 * Protection Keys are not available in 32-bit mode. 390 */ 391 static bool pku_disabled; 392 393 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 394 { 395 struct pkru_state *pk; 396 397 /* check the boot processor, plus compile options for PKU: */ 398 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 399 return; 400 /* checks the actual processor's cpuid bits: */ 401 if (!cpu_has(c, X86_FEATURE_PKU)) 402 return; 403 if (pku_disabled) 404 return; 405 406 cr4_set_bits(X86_CR4_PKE); 407 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 408 if (pk) 409 pk->pkru = init_pkru_value; 410 /* 411 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 412 * cpuid bit to be set. We need to ensure that we 413 * update that bit in this CPU's "cpu_info". 414 */ 415 get_cpu_cap(c); 416 } 417 418 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 419 static __init int setup_disable_pku(char *arg) 420 { 421 /* 422 * Do not clear the X86_FEATURE_PKU bit. All of the 423 * runtime checks are against OSPKE so clearing the 424 * bit does nothing. 425 * 426 * This way, we will see "pku" in cpuinfo, but not 427 * "ospke", which is exactly what we want. It shows 428 * that the CPU has PKU, but the OS has not enabled it. 429 * This happens to be exactly how a system would look 430 * if we disabled the config option. 431 */ 432 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 433 pku_disabled = true; 434 return 1; 435 } 436 __setup("nopku", setup_disable_pku); 437 #endif /* CONFIG_X86_64 */ 438 439 /* 440 * Some CPU features depend on higher CPUID levels, which may not always 441 * be available due to CPUID level capping or broken virtualization 442 * software. Add those features to this table to auto-disable them. 443 */ 444 struct cpuid_dependent_feature { 445 u32 feature; 446 u32 level; 447 }; 448 449 static const struct cpuid_dependent_feature 450 cpuid_dependent_features[] = { 451 { X86_FEATURE_MWAIT, 0x00000005 }, 452 { X86_FEATURE_DCA, 0x00000009 }, 453 { X86_FEATURE_XSAVE, 0x0000000d }, 454 { 0, 0 } 455 }; 456 457 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 458 { 459 const struct cpuid_dependent_feature *df; 460 461 for (df = cpuid_dependent_features; df->feature; df++) { 462 463 if (!cpu_has(c, df->feature)) 464 continue; 465 /* 466 * Note: cpuid_level is set to -1 if unavailable, but 467 * extended_extended_level is set to 0 if unavailable 468 * and the legitimate extended levels are all negative 469 * when signed; hence the weird messing around with 470 * signs here... 471 */ 472 if (!((s32)df->level < 0 ? 473 (u32)df->level > (u32)c->extended_cpuid_level : 474 (s32)df->level > (s32)c->cpuid_level)) 475 continue; 476 477 clear_cpu_cap(c, df->feature); 478 if (!warn) 479 continue; 480 481 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 482 x86_cap_flag(df->feature), df->level); 483 } 484 } 485 486 /* 487 * Naming convention should be: <Name> [(<Codename>)] 488 * This table only is used unless init_<vendor>() below doesn't set it; 489 * in particular, if CPUID levels 0x80000002..4 are supported, this 490 * isn't used 491 */ 492 493 /* Look up CPU names by table lookup. */ 494 static const char *table_lookup_model(struct cpuinfo_x86 *c) 495 { 496 #ifdef CONFIG_X86_32 497 const struct legacy_cpu_model_info *info; 498 499 if (c->x86_model >= 16) 500 return NULL; /* Range check */ 501 502 if (!this_cpu) 503 return NULL; 504 505 info = this_cpu->legacy_models; 506 507 while (info->family) { 508 if (info->family == c->x86) 509 return info->model_names[c->x86_model]; 510 info++; 511 } 512 #endif 513 return NULL; /* Not found */ 514 } 515 516 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 517 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 518 519 void load_percpu_segment(int cpu) 520 { 521 #ifdef CONFIG_X86_32 522 loadsegment(fs, __KERNEL_PERCPU); 523 #else 524 __loadsegment_simple(gs, 0); 525 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 526 #endif 527 load_stack_canary_segment(); 528 } 529 530 #ifdef CONFIG_X86_32 531 /* The 32-bit entry code needs to find cpu_entry_area. */ 532 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 533 #endif 534 535 /* Load the original GDT from the per-cpu structure */ 536 void load_direct_gdt(int cpu) 537 { 538 struct desc_ptr gdt_descr; 539 540 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 541 gdt_descr.size = GDT_SIZE - 1; 542 load_gdt(&gdt_descr); 543 } 544 EXPORT_SYMBOL_GPL(load_direct_gdt); 545 546 /* Load a fixmap remapping of the per-cpu GDT */ 547 void load_fixmap_gdt(int cpu) 548 { 549 struct desc_ptr gdt_descr; 550 551 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 552 gdt_descr.size = GDT_SIZE - 1; 553 load_gdt(&gdt_descr); 554 } 555 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 556 557 /* 558 * Current gdt points %fs at the "master" per-cpu area: after this, 559 * it's on the real one. 560 */ 561 void switch_to_new_gdt(int cpu) 562 { 563 /* Load the original GDT */ 564 load_direct_gdt(cpu); 565 /* Reload the per-cpu base */ 566 load_percpu_segment(cpu); 567 } 568 569 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 570 571 static void get_model_name(struct cpuinfo_x86 *c) 572 { 573 unsigned int *v; 574 char *p, *q, *s; 575 576 if (c->extended_cpuid_level < 0x80000004) 577 return; 578 579 v = (unsigned int *)c->x86_model_id; 580 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 581 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 582 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 583 c->x86_model_id[48] = 0; 584 585 /* Trim whitespace */ 586 p = q = s = &c->x86_model_id[0]; 587 588 while (*p == ' ') 589 p++; 590 591 while (*p) { 592 /* Note the last non-whitespace index */ 593 if (!isspace(*p)) 594 s = q; 595 596 *q++ = *p++; 597 } 598 599 *(s + 1) = '\0'; 600 } 601 602 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 603 { 604 unsigned int eax, ebx, ecx, edx; 605 606 c->x86_max_cores = 1; 607 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 608 return; 609 610 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 611 if (eax & 0x1f) 612 c->x86_max_cores = (eax >> 26) + 1; 613 } 614 615 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 616 { 617 unsigned int n, dummy, ebx, ecx, edx, l2size; 618 619 n = c->extended_cpuid_level; 620 621 if (n >= 0x80000005) { 622 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 623 c->x86_cache_size = (ecx>>24) + (edx>>24); 624 #ifdef CONFIG_X86_64 625 /* On K8 L1 TLB is inclusive, so don't count it */ 626 c->x86_tlbsize = 0; 627 #endif 628 } 629 630 if (n < 0x80000006) /* Some chips just has a large L1. */ 631 return; 632 633 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 634 l2size = ecx >> 16; 635 636 #ifdef CONFIG_X86_64 637 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 638 #else 639 /* do processor-specific cache resizing */ 640 if (this_cpu->legacy_cache_size) 641 l2size = this_cpu->legacy_cache_size(c, l2size); 642 643 /* Allow user to override all this if necessary. */ 644 if (cachesize_override != -1) 645 l2size = cachesize_override; 646 647 if (l2size == 0) 648 return; /* Again, no L2 cache is possible */ 649 #endif 650 651 c->x86_cache_size = l2size; 652 } 653 654 u16 __read_mostly tlb_lli_4k[NR_INFO]; 655 u16 __read_mostly tlb_lli_2m[NR_INFO]; 656 u16 __read_mostly tlb_lli_4m[NR_INFO]; 657 u16 __read_mostly tlb_lld_4k[NR_INFO]; 658 u16 __read_mostly tlb_lld_2m[NR_INFO]; 659 u16 __read_mostly tlb_lld_4m[NR_INFO]; 660 u16 __read_mostly tlb_lld_1g[NR_INFO]; 661 662 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 663 { 664 if (this_cpu->c_detect_tlb) 665 this_cpu->c_detect_tlb(c); 666 667 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 668 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 669 tlb_lli_4m[ENTRIES]); 670 671 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 672 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 673 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 674 } 675 676 int detect_ht_early(struct cpuinfo_x86 *c) 677 { 678 #ifdef CONFIG_SMP 679 u32 eax, ebx, ecx, edx; 680 681 if (!cpu_has(c, X86_FEATURE_HT)) 682 return -1; 683 684 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 685 return -1; 686 687 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 688 return -1; 689 690 cpuid(1, &eax, &ebx, &ecx, &edx); 691 692 smp_num_siblings = (ebx & 0xff0000) >> 16; 693 if (smp_num_siblings == 1) 694 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 695 #endif 696 return 0; 697 } 698 699 void detect_ht(struct cpuinfo_x86 *c) 700 { 701 #ifdef CONFIG_SMP 702 int index_msb, core_bits; 703 704 if (detect_ht_early(c) < 0) 705 return; 706 707 index_msb = get_count_order(smp_num_siblings); 708 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 709 710 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 711 712 index_msb = get_count_order(smp_num_siblings); 713 714 core_bits = get_count_order(c->x86_max_cores); 715 716 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 717 ((1 << core_bits) - 1); 718 #endif 719 } 720 721 static void get_cpu_vendor(struct cpuinfo_x86 *c) 722 { 723 char *v = c->x86_vendor_id; 724 int i; 725 726 for (i = 0; i < X86_VENDOR_NUM; i++) { 727 if (!cpu_devs[i]) 728 break; 729 730 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 731 (cpu_devs[i]->c_ident[1] && 732 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 733 734 this_cpu = cpu_devs[i]; 735 c->x86_vendor = this_cpu->c_x86_vendor; 736 return; 737 } 738 } 739 740 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 741 "CPU: Your system may be unstable.\n", v); 742 743 c->x86_vendor = X86_VENDOR_UNKNOWN; 744 this_cpu = &default_cpu; 745 } 746 747 void cpu_detect(struct cpuinfo_x86 *c) 748 { 749 /* Get vendor name */ 750 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 751 (unsigned int *)&c->x86_vendor_id[0], 752 (unsigned int *)&c->x86_vendor_id[8], 753 (unsigned int *)&c->x86_vendor_id[4]); 754 755 c->x86 = 4; 756 /* Intel-defined flags: level 0x00000001 */ 757 if (c->cpuid_level >= 0x00000001) { 758 u32 junk, tfms, cap0, misc; 759 760 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 761 c->x86 = x86_family(tfms); 762 c->x86_model = x86_model(tfms); 763 c->x86_stepping = x86_stepping(tfms); 764 765 if (cap0 & (1<<19)) { 766 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 767 c->x86_cache_alignment = c->x86_clflush_size; 768 } 769 } 770 } 771 772 static void apply_forced_caps(struct cpuinfo_x86 *c) 773 { 774 int i; 775 776 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 777 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 778 c->x86_capability[i] |= cpu_caps_set[i]; 779 } 780 } 781 782 static void init_speculation_control(struct cpuinfo_x86 *c) 783 { 784 /* 785 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 786 * and they also have a different bit for STIBP support. Also, 787 * a hypervisor might have set the individual AMD bits even on 788 * Intel CPUs, for finer-grained selection of what's available. 789 */ 790 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 791 set_cpu_cap(c, X86_FEATURE_IBRS); 792 set_cpu_cap(c, X86_FEATURE_IBPB); 793 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 794 } 795 796 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 797 set_cpu_cap(c, X86_FEATURE_STIBP); 798 799 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 800 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 801 set_cpu_cap(c, X86_FEATURE_SSBD); 802 803 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 804 set_cpu_cap(c, X86_FEATURE_IBRS); 805 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 806 } 807 808 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 809 set_cpu_cap(c, X86_FEATURE_IBPB); 810 811 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 812 set_cpu_cap(c, X86_FEATURE_STIBP); 813 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 814 } 815 816 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 817 set_cpu_cap(c, X86_FEATURE_SSBD); 818 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 819 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 820 } 821 } 822 823 static void init_cqm(struct cpuinfo_x86 *c) 824 { 825 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 826 c->x86_cache_max_rmid = -1; 827 c->x86_cache_occ_scale = -1; 828 return; 829 } 830 831 /* will be overridden if occupancy monitoring exists */ 832 c->x86_cache_max_rmid = cpuid_ebx(0xf); 833 834 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 835 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 836 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 837 u32 eax, ebx, ecx, edx; 838 839 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 840 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 841 842 c->x86_cache_max_rmid = ecx; 843 c->x86_cache_occ_scale = ebx; 844 } 845 } 846 847 void get_cpu_cap(struct cpuinfo_x86 *c) 848 { 849 u32 eax, ebx, ecx, edx; 850 851 /* Intel-defined flags: level 0x00000001 */ 852 if (c->cpuid_level >= 0x00000001) { 853 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 854 855 c->x86_capability[CPUID_1_ECX] = ecx; 856 c->x86_capability[CPUID_1_EDX] = edx; 857 } 858 859 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 860 if (c->cpuid_level >= 0x00000006) 861 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 862 863 /* Additional Intel-defined flags: level 0x00000007 */ 864 if (c->cpuid_level >= 0x00000007) { 865 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 866 c->x86_capability[CPUID_7_0_EBX] = ebx; 867 c->x86_capability[CPUID_7_ECX] = ecx; 868 c->x86_capability[CPUID_7_EDX] = edx; 869 870 /* Check valid sub-leaf index before accessing it */ 871 if (eax >= 1) { 872 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 873 c->x86_capability[CPUID_7_1_EAX] = eax; 874 } 875 } 876 877 /* Extended state features: level 0x0000000d */ 878 if (c->cpuid_level >= 0x0000000d) { 879 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 880 881 c->x86_capability[CPUID_D_1_EAX] = eax; 882 } 883 884 /* AMD-defined flags: level 0x80000001 */ 885 eax = cpuid_eax(0x80000000); 886 c->extended_cpuid_level = eax; 887 888 if ((eax & 0xffff0000) == 0x80000000) { 889 if (eax >= 0x80000001) { 890 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 891 892 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 893 c->x86_capability[CPUID_8000_0001_EDX] = edx; 894 } 895 } 896 897 if (c->extended_cpuid_level >= 0x80000007) { 898 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 899 900 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 901 c->x86_power = edx; 902 } 903 904 if (c->extended_cpuid_level >= 0x80000008) { 905 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 906 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 907 } 908 909 if (c->extended_cpuid_level >= 0x8000000a) 910 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 911 912 init_scattered_cpuid_features(c); 913 init_speculation_control(c); 914 init_cqm(c); 915 916 /* 917 * Clear/Set all flags overridden by options, after probe. 918 * This needs to happen each time we re-probe, which may happen 919 * several times during CPU initialization. 920 */ 921 apply_forced_caps(c); 922 } 923 924 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 925 { 926 u32 eax, ebx, ecx, edx; 927 928 if (c->extended_cpuid_level >= 0x80000008) { 929 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 930 931 c->x86_virt_bits = (eax >> 8) & 0xff; 932 c->x86_phys_bits = eax & 0xff; 933 } 934 #ifdef CONFIG_X86_32 935 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 936 c->x86_phys_bits = 36; 937 #endif 938 c->x86_cache_bits = c->x86_phys_bits; 939 } 940 941 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 942 { 943 #ifdef CONFIG_X86_32 944 int i; 945 946 /* 947 * First of all, decide if this is a 486 or higher 948 * It's a 486 if we can modify the AC flag 949 */ 950 if (flag_is_changeable_p(X86_EFLAGS_AC)) 951 c->x86 = 4; 952 else 953 c->x86 = 3; 954 955 for (i = 0; i < X86_VENDOR_NUM; i++) 956 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 957 c->x86_vendor_id[0] = 0; 958 cpu_devs[i]->c_identify(c); 959 if (c->x86_vendor_id[0]) { 960 get_cpu_vendor(c); 961 break; 962 } 963 } 964 #endif 965 } 966 967 #define NO_SPECULATION BIT(0) 968 #define NO_MELTDOWN BIT(1) 969 #define NO_SSB BIT(2) 970 #define NO_L1TF BIT(3) 971 #define NO_MDS BIT(4) 972 #define MSBDS_ONLY BIT(5) 973 974 #define VULNWL(_vendor, _family, _model, _whitelist) \ 975 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } 976 977 #define VULNWL_INTEL(model, whitelist) \ 978 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 979 980 #define VULNWL_AMD(family, whitelist) \ 981 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 982 983 #define VULNWL_HYGON(family, whitelist) \ 984 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 985 986 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 987 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 988 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 989 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 990 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 991 992 /* Intel Family 6 */ 993 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION), 994 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION), 995 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION), 996 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), 997 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), 998 999 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), 1000 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY), 1001 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY), 1002 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), 1003 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY), 1004 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY), 1005 1006 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1007 1008 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY), 1009 1010 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF), 1011 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF), 1012 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF), 1013 1014 /* AMD Family 0xf - 0x12 */ 1015 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 1016 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 1017 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 1018 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 1019 1020 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1021 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), 1022 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), 1023 {} 1024 }; 1025 1026 static bool __init cpu_matches(unsigned long which) 1027 { 1028 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 1029 1030 return m && !!(m->driver_data & which); 1031 } 1032 1033 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1034 { 1035 u64 ia32_cap = 0; 1036 1037 if (cpu_matches(NO_SPECULATION)) 1038 return; 1039 1040 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1041 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1042 1043 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) 1044 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1045 1046 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 1047 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1048 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1049 1050 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1051 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1052 1053 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1054 setup_force_cpu_bug(X86_BUG_MDS); 1055 if (cpu_matches(MSBDS_ONLY)) 1056 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1057 } 1058 1059 if (cpu_matches(NO_MELTDOWN)) 1060 return; 1061 1062 /* Rogue Data Cache Load? No! */ 1063 if (ia32_cap & ARCH_CAP_RDCL_NO) 1064 return; 1065 1066 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1067 1068 if (cpu_matches(NO_L1TF)) 1069 return; 1070 1071 setup_force_cpu_bug(X86_BUG_L1TF); 1072 } 1073 1074 /* 1075 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1076 * unfortunately, that's not true in practice because of early VIA 1077 * chips and (more importantly) broken virtualizers that are not easy 1078 * to detect. In the latter case it doesn't even *fail* reliably, so 1079 * probing for it doesn't even work. Disable it completely on 32-bit 1080 * unless we can find a reliable way to detect all the broken cases. 1081 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1082 */ 1083 static void detect_nopl(void) 1084 { 1085 #ifdef CONFIG_X86_32 1086 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1087 #else 1088 setup_force_cpu_cap(X86_FEATURE_NOPL); 1089 #endif 1090 } 1091 1092 /* 1093 * Do minimum CPU detection early. 1094 * Fields really needed: vendor, cpuid_level, family, model, mask, 1095 * cache alignment. 1096 * The others are not touched to avoid unwanted side effects. 1097 * 1098 * WARNING: this function is only called on the boot CPU. Don't add code 1099 * here that is supposed to run on all CPUs. 1100 */ 1101 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1102 { 1103 #ifdef CONFIG_X86_64 1104 c->x86_clflush_size = 64; 1105 c->x86_phys_bits = 36; 1106 c->x86_virt_bits = 48; 1107 #else 1108 c->x86_clflush_size = 32; 1109 c->x86_phys_bits = 32; 1110 c->x86_virt_bits = 32; 1111 #endif 1112 c->x86_cache_alignment = c->x86_clflush_size; 1113 1114 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1115 c->extended_cpuid_level = 0; 1116 1117 if (!have_cpuid_p()) 1118 identify_cpu_without_cpuid(c); 1119 1120 /* cyrix could have cpuid enabled via c_identify()*/ 1121 if (have_cpuid_p()) { 1122 cpu_detect(c); 1123 get_cpu_vendor(c); 1124 get_cpu_cap(c); 1125 get_cpu_address_sizes(c); 1126 setup_force_cpu_cap(X86_FEATURE_CPUID); 1127 1128 if (this_cpu->c_early_init) 1129 this_cpu->c_early_init(c); 1130 1131 c->cpu_index = 0; 1132 filter_cpuid_features(c, false); 1133 1134 if (this_cpu->c_bsp_init) 1135 this_cpu->c_bsp_init(c); 1136 } else { 1137 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1138 } 1139 1140 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1141 1142 cpu_set_bug_bits(c); 1143 1144 fpu__init_system(c); 1145 1146 #ifdef CONFIG_X86_32 1147 /* 1148 * Regardless of whether PCID is enumerated, the SDM says 1149 * that it can't be enabled in 32-bit mode. 1150 */ 1151 setup_clear_cpu_cap(X86_FEATURE_PCID); 1152 #endif 1153 1154 /* 1155 * Later in the boot process pgtable_l5_enabled() relies on 1156 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1157 * enabled by this point we need to clear the feature bit to avoid 1158 * false-positives at the later stage. 1159 * 1160 * pgtable_l5_enabled() can be false here for several reasons: 1161 * - 5-level paging is disabled compile-time; 1162 * - it's 32-bit kernel; 1163 * - machine doesn't support 5-level paging; 1164 * - user specified 'no5lvl' in kernel command line. 1165 */ 1166 if (!pgtable_l5_enabled()) 1167 setup_clear_cpu_cap(X86_FEATURE_LA57); 1168 1169 detect_nopl(); 1170 } 1171 1172 void __init early_cpu_init(void) 1173 { 1174 const struct cpu_dev *const *cdev; 1175 int count = 0; 1176 1177 #ifdef CONFIG_PROCESSOR_SELECT 1178 pr_info("KERNEL supported cpus:\n"); 1179 #endif 1180 1181 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1182 const struct cpu_dev *cpudev = *cdev; 1183 1184 if (count >= X86_VENDOR_NUM) 1185 break; 1186 cpu_devs[count] = cpudev; 1187 count++; 1188 1189 #ifdef CONFIG_PROCESSOR_SELECT 1190 { 1191 unsigned int j; 1192 1193 for (j = 0; j < 2; j++) { 1194 if (!cpudev->c_ident[j]) 1195 continue; 1196 pr_info(" %s %s\n", cpudev->c_vendor, 1197 cpudev->c_ident[j]); 1198 } 1199 } 1200 #endif 1201 } 1202 early_identify_cpu(&boot_cpu_data); 1203 } 1204 1205 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1206 { 1207 #ifdef CONFIG_X86_64 1208 /* 1209 * Empirically, writing zero to a segment selector on AMD does 1210 * not clear the base, whereas writing zero to a segment 1211 * selector on Intel does clear the base. Intel's behavior 1212 * allows slightly faster context switches in the common case 1213 * where GS is unused by the prev and next threads. 1214 * 1215 * Since neither vendor documents this anywhere that I can see, 1216 * detect it directly instead of hardcoding the choice by 1217 * vendor. 1218 * 1219 * I've designated AMD's behavior as the "bug" because it's 1220 * counterintuitive and less friendly. 1221 */ 1222 1223 unsigned long old_base, tmp; 1224 rdmsrl(MSR_FS_BASE, old_base); 1225 wrmsrl(MSR_FS_BASE, 1); 1226 loadsegment(fs, 0); 1227 rdmsrl(MSR_FS_BASE, tmp); 1228 if (tmp != 0) 1229 set_cpu_bug(c, X86_BUG_NULL_SEG); 1230 wrmsrl(MSR_FS_BASE, old_base); 1231 #endif 1232 } 1233 1234 static void generic_identify(struct cpuinfo_x86 *c) 1235 { 1236 c->extended_cpuid_level = 0; 1237 1238 if (!have_cpuid_p()) 1239 identify_cpu_without_cpuid(c); 1240 1241 /* cyrix could have cpuid enabled via c_identify()*/ 1242 if (!have_cpuid_p()) 1243 return; 1244 1245 cpu_detect(c); 1246 1247 get_cpu_vendor(c); 1248 1249 get_cpu_cap(c); 1250 1251 get_cpu_address_sizes(c); 1252 1253 if (c->cpuid_level >= 0x00000001) { 1254 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1255 #ifdef CONFIG_X86_32 1256 # ifdef CONFIG_SMP 1257 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1258 # else 1259 c->apicid = c->initial_apicid; 1260 # endif 1261 #endif 1262 c->phys_proc_id = c->initial_apicid; 1263 } 1264 1265 get_model_name(c); /* Default name */ 1266 1267 detect_null_seg_behavior(c); 1268 1269 /* 1270 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1271 * systems that run Linux at CPL > 0 may or may not have the 1272 * issue, but, even if they have the issue, there's absolutely 1273 * nothing we can do about it because we can't use the real IRET 1274 * instruction. 1275 * 1276 * NB: For the time being, only 32-bit kernels support 1277 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1278 * whether to apply espfix using paravirt hooks. If any 1279 * non-paravirt system ever shows up that does *not* have the 1280 * ESPFIX issue, we can change this. 1281 */ 1282 #ifdef CONFIG_X86_32 1283 # ifdef CONFIG_PARAVIRT_XXL 1284 do { 1285 extern void native_iret(void); 1286 if (pv_ops.cpu.iret == native_iret) 1287 set_cpu_bug(c, X86_BUG_ESPFIX); 1288 } while (0); 1289 # else 1290 set_cpu_bug(c, X86_BUG_ESPFIX); 1291 # endif 1292 #endif 1293 } 1294 1295 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1296 { 1297 /* 1298 * The heavy lifting of max_rmid and cache_occ_scale are handled 1299 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1300 * in case CQM bits really aren't there in this CPU. 1301 */ 1302 if (c != &boot_cpu_data) { 1303 boot_cpu_data.x86_cache_max_rmid = 1304 min(boot_cpu_data.x86_cache_max_rmid, 1305 c->x86_cache_max_rmid); 1306 } 1307 } 1308 1309 /* 1310 * Validate that ACPI/mptables have the same information about the 1311 * effective APIC id and update the package map. 1312 */ 1313 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1314 { 1315 #ifdef CONFIG_SMP 1316 unsigned int apicid, cpu = smp_processor_id(); 1317 1318 apicid = apic->cpu_present_to_apicid(cpu); 1319 1320 if (apicid != c->apicid) { 1321 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1322 cpu, apicid, c->initial_apicid); 1323 } 1324 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1325 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1326 #else 1327 c->logical_proc_id = 0; 1328 #endif 1329 } 1330 1331 /* 1332 * This does the hard work of actually picking apart the CPU stuff... 1333 */ 1334 static void identify_cpu(struct cpuinfo_x86 *c) 1335 { 1336 int i; 1337 1338 c->loops_per_jiffy = loops_per_jiffy; 1339 c->x86_cache_size = 0; 1340 c->x86_vendor = X86_VENDOR_UNKNOWN; 1341 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1342 c->x86_vendor_id[0] = '\0'; /* Unset */ 1343 c->x86_model_id[0] = '\0'; /* Unset */ 1344 c->x86_max_cores = 1; 1345 c->x86_coreid_bits = 0; 1346 c->cu_id = 0xff; 1347 #ifdef CONFIG_X86_64 1348 c->x86_clflush_size = 64; 1349 c->x86_phys_bits = 36; 1350 c->x86_virt_bits = 48; 1351 #else 1352 c->cpuid_level = -1; /* CPUID not detected */ 1353 c->x86_clflush_size = 32; 1354 c->x86_phys_bits = 32; 1355 c->x86_virt_bits = 32; 1356 #endif 1357 c->x86_cache_alignment = c->x86_clflush_size; 1358 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1359 1360 generic_identify(c); 1361 1362 if (this_cpu->c_identify) 1363 this_cpu->c_identify(c); 1364 1365 /* Clear/Set all flags overridden by options, after probe */ 1366 apply_forced_caps(c); 1367 1368 #ifdef CONFIG_X86_64 1369 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1370 #endif 1371 1372 /* 1373 * Vendor-specific initialization. In this section we 1374 * canonicalize the feature flags, meaning if there are 1375 * features a certain CPU supports which CPUID doesn't 1376 * tell us, CPUID claiming incorrect flags, or other bugs, 1377 * we handle them here. 1378 * 1379 * At the end of this section, c->x86_capability better 1380 * indicate the features this CPU genuinely supports! 1381 */ 1382 if (this_cpu->c_init) 1383 this_cpu->c_init(c); 1384 1385 /* Disable the PN if appropriate */ 1386 squash_the_stupid_serial_number(c); 1387 1388 /* Set up SMEP/SMAP/UMIP */ 1389 setup_smep(c); 1390 setup_smap(c); 1391 setup_umip(c); 1392 1393 /* 1394 * The vendor-specific functions might have changed features. 1395 * Now we do "generic changes." 1396 */ 1397 1398 /* Filter out anything that depends on CPUID levels we don't have */ 1399 filter_cpuid_features(c, true); 1400 1401 /* If the model name is still unset, do table lookup. */ 1402 if (!c->x86_model_id[0]) { 1403 const char *p; 1404 p = table_lookup_model(c); 1405 if (p) 1406 strcpy(c->x86_model_id, p); 1407 else 1408 /* Last resort... */ 1409 sprintf(c->x86_model_id, "%02x/%02x", 1410 c->x86, c->x86_model); 1411 } 1412 1413 #ifdef CONFIG_X86_64 1414 detect_ht(c); 1415 #endif 1416 1417 x86_init_rdrand(c); 1418 x86_init_cache_qos(c); 1419 setup_pku(c); 1420 1421 /* 1422 * Clear/Set all flags overridden by options, need do it 1423 * before following smp all cpus cap AND. 1424 */ 1425 apply_forced_caps(c); 1426 1427 /* 1428 * On SMP, boot_cpu_data holds the common feature set between 1429 * all CPUs; so make sure that we indicate which features are 1430 * common between the CPUs. The first time this routine gets 1431 * executed, c == &boot_cpu_data. 1432 */ 1433 if (c != &boot_cpu_data) { 1434 /* AND the already accumulated flags with these */ 1435 for (i = 0; i < NCAPINTS; i++) 1436 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1437 1438 /* OR, i.e. replicate the bug flags */ 1439 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1440 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1441 } 1442 1443 /* Init Machine Check Exception if available. */ 1444 mcheck_cpu_init(c); 1445 1446 select_idle_routine(c); 1447 1448 #ifdef CONFIG_NUMA 1449 numa_add_cpu(smp_processor_id()); 1450 #endif 1451 } 1452 1453 /* 1454 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1455 * on 32-bit kernels: 1456 */ 1457 #ifdef CONFIG_X86_32 1458 void enable_sep_cpu(void) 1459 { 1460 struct tss_struct *tss; 1461 int cpu; 1462 1463 if (!boot_cpu_has(X86_FEATURE_SEP)) 1464 return; 1465 1466 cpu = get_cpu(); 1467 tss = &per_cpu(cpu_tss_rw, cpu); 1468 1469 /* 1470 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1471 * see the big comment in struct x86_hw_tss's definition. 1472 */ 1473 1474 tss->x86_tss.ss1 = __KERNEL_CS; 1475 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1476 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1477 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1478 1479 put_cpu(); 1480 } 1481 #endif 1482 1483 void __init identify_boot_cpu(void) 1484 { 1485 identify_cpu(&boot_cpu_data); 1486 #ifdef CONFIG_X86_32 1487 sysenter_setup(); 1488 enable_sep_cpu(); 1489 #endif 1490 cpu_detect_tlb(&boot_cpu_data); 1491 setup_cr_pinning(); 1492 } 1493 1494 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1495 { 1496 BUG_ON(c == &boot_cpu_data); 1497 identify_cpu(c); 1498 #ifdef CONFIG_X86_32 1499 enable_sep_cpu(); 1500 #endif 1501 mtrr_ap_init(); 1502 validate_apic_and_package_id(c); 1503 x86_spec_ctrl_setup_ap(); 1504 } 1505 1506 static __init int setup_noclflush(char *arg) 1507 { 1508 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1509 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1510 return 1; 1511 } 1512 __setup("noclflush", setup_noclflush); 1513 1514 void print_cpu_info(struct cpuinfo_x86 *c) 1515 { 1516 const char *vendor = NULL; 1517 1518 if (c->x86_vendor < X86_VENDOR_NUM) { 1519 vendor = this_cpu->c_vendor; 1520 } else { 1521 if (c->cpuid_level >= 0) 1522 vendor = c->x86_vendor_id; 1523 } 1524 1525 if (vendor && !strstr(c->x86_model_id, vendor)) 1526 pr_cont("%s ", vendor); 1527 1528 if (c->x86_model_id[0]) 1529 pr_cont("%s", c->x86_model_id); 1530 else 1531 pr_cont("%d86", c->x86); 1532 1533 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1534 1535 if (c->x86_stepping || c->cpuid_level >= 0) 1536 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1537 else 1538 pr_cont(")\n"); 1539 } 1540 1541 /* 1542 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1543 * But we need to keep a dummy __setup around otherwise it would 1544 * show up as an environment variable for init. 1545 */ 1546 static __init int setup_clearcpuid(char *arg) 1547 { 1548 return 1; 1549 } 1550 __setup("clearcpuid=", setup_clearcpuid); 1551 1552 #ifdef CONFIG_X86_64 1553 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1554 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1555 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1556 1557 /* 1558 * The following percpu variables are hot. Align current_task to 1559 * cacheline size such that they fall in the same cacheline. 1560 */ 1561 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1562 &init_task; 1563 EXPORT_PER_CPU_SYMBOL(current_task); 1564 1565 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1566 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1567 1568 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1569 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1570 1571 /* May not be marked __init: used by software suspend */ 1572 void syscall_init(void) 1573 { 1574 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1575 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1576 1577 #ifdef CONFIG_IA32_EMULATION 1578 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1579 /* 1580 * This only works on Intel CPUs. 1581 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1582 * This does not cause SYSENTER to jump to the wrong location, because 1583 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1584 */ 1585 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1586 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1587 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1588 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1589 #else 1590 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1591 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1592 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1593 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1594 #endif 1595 1596 /* Flags to clear on syscall */ 1597 wrmsrl(MSR_SYSCALL_MASK, 1598 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1599 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1600 } 1601 1602 DEFINE_PER_CPU(int, debug_stack_usage); 1603 DEFINE_PER_CPU(u32, debug_idt_ctr); 1604 1605 void debug_stack_set_zero(void) 1606 { 1607 this_cpu_inc(debug_idt_ctr); 1608 load_current_idt(); 1609 } 1610 NOKPROBE_SYMBOL(debug_stack_set_zero); 1611 1612 void debug_stack_reset(void) 1613 { 1614 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1615 return; 1616 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1617 load_current_idt(); 1618 } 1619 NOKPROBE_SYMBOL(debug_stack_reset); 1620 1621 #else /* CONFIG_X86_64 */ 1622 1623 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1624 EXPORT_PER_CPU_SYMBOL(current_task); 1625 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1626 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1627 1628 /* 1629 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1630 * the top of the kernel stack. Use an extra percpu variable to track the 1631 * top of the kernel stack directly. 1632 */ 1633 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1634 (unsigned long)&init_thread_union + THREAD_SIZE; 1635 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1636 1637 #ifdef CONFIG_STACKPROTECTOR 1638 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1639 #endif 1640 1641 #endif /* CONFIG_X86_64 */ 1642 1643 /* 1644 * Clear all 6 debug registers: 1645 */ 1646 static void clear_all_debug_regs(void) 1647 { 1648 int i; 1649 1650 for (i = 0; i < 8; i++) { 1651 /* Ignore db4, db5 */ 1652 if ((i == 4) || (i == 5)) 1653 continue; 1654 1655 set_debugreg(0, i); 1656 } 1657 } 1658 1659 #ifdef CONFIG_KGDB 1660 /* 1661 * Restore debug regs if using kgdbwait and you have a kernel debugger 1662 * connection established. 1663 */ 1664 static void dbg_restore_debug_regs(void) 1665 { 1666 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1667 arch_kgdb_ops.correct_hw_break(); 1668 } 1669 #else /* ! CONFIG_KGDB */ 1670 #define dbg_restore_debug_regs() 1671 #endif /* ! CONFIG_KGDB */ 1672 1673 static void wait_for_master_cpu(int cpu) 1674 { 1675 #ifdef CONFIG_SMP 1676 /* 1677 * wait for ACK from master CPU before continuing 1678 * with AP initialization 1679 */ 1680 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1681 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1682 cpu_relax(); 1683 #endif 1684 } 1685 1686 #ifdef CONFIG_X86_64 1687 static void setup_getcpu(int cpu) 1688 { 1689 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1690 struct desc_struct d = { }; 1691 1692 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1693 write_rdtscp_aux(cpudata); 1694 1695 /* Store CPU and node number in limit. */ 1696 d.limit0 = cpudata; 1697 d.limit1 = cpudata >> 16; 1698 1699 d.type = 5; /* RO data, expand down, accessed */ 1700 d.dpl = 3; /* Visible to user code */ 1701 d.s = 1; /* Not a system segment */ 1702 d.p = 1; /* Present */ 1703 d.d = 1; /* 32-bit */ 1704 1705 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1706 } 1707 #endif 1708 1709 /* 1710 * cpu_init() initializes state that is per-CPU. Some data is already 1711 * initialized (naturally) in the bootstrap process, such as the GDT 1712 * and IDT. We reload them nevertheless, this function acts as a 1713 * 'CPU state barrier', nothing should get across. 1714 */ 1715 #ifdef CONFIG_X86_64 1716 1717 void cpu_init(void) 1718 { 1719 int cpu = raw_smp_processor_id(); 1720 struct task_struct *me; 1721 struct tss_struct *t; 1722 int i; 1723 1724 wait_for_master_cpu(cpu); 1725 1726 /* 1727 * Initialize the CR4 shadow before doing anything that could 1728 * try to read it. 1729 */ 1730 cr4_init_shadow(); 1731 1732 if (cpu) 1733 load_ucode_ap(); 1734 1735 t = &per_cpu(cpu_tss_rw, cpu); 1736 1737 #ifdef CONFIG_NUMA 1738 if (this_cpu_read(numa_node) == 0 && 1739 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1740 set_numa_node(early_cpu_to_node(cpu)); 1741 #endif 1742 setup_getcpu(cpu); 1743 1744 me = current; 1745 1746 pr_debug("Initializing CPU#%d\n", cpu); 1747 1748 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1749 1750 /* 1751 * Initialize the per-CPU GDT with the boot GDT, 1752 * and set up the GDT descriptor: 1753 */ 1754 1755 switch_to_new_gdt(cpu); 1756 loadsegment(fs, 0); 1757 1758 load_current_idt(); 1759 1760 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1761 syscall_init(); 1762 1763 wrmsrl(MSR_FS_BASE, 0); 1764 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1765 barrier(); 1766 1767 x86_configure_nx(); 1768 x2apic_setup(); 1769 1770 /* 1771 * set up and load the per-CPU TSS 1772 */ 1773 if (!t->x86_tss.ist[0]) { 1774 t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1775 t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1776 t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1777 t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1778 } 1779 1780 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1781 1782 /* 1783 * <= is required because the CPU will access up to 1784 * 8 bits beyond the end of the IO permission bitmap. 1785 */ 1786 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1787 t->io_bitmap[i] = ~0UL; 1788 1789 mmgrab(&init_mm); 1790 me->active_mm = &init_mm; 1791 BUG_ON(me->mm); 1792 initialize_tlbstate_and_flush(); 1793 enter_lazy_tlb(&init_mm, me); 1794 1795 /* 1796 * Initialize the TSS. sp0 points to the entry trampoline stack 1797 * regardless of what task is running. 1798 */ 1799 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1800 load_TR_desc(); 1801 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1802 1803 load_mm_ldt(&init_mm); 1804 1805 clear_all_debug_regs(); 1806 dbg_restore_debug_regs(); 1807 1808 fpu__init_cpu(); 1809 1810 if (is_uv_system()) 1811 uv_cpu_init(); 1812 1813 load_fixmap_gdt(cpu); 1814 } 1815 1816 #else 1817 1818 void cpu_init(void) 1819 { 1820 int cpu = smp_processor_id(); 1821 struct task_struct *curr = current; 1822 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1823 1824 wait_for_master_cpu(cpu); 1825 1826 /* 1827 * Initialize the CR4 shadow before doing anything that could 1828 * try to read it. 1829 */ 1830 cr4_init_shadow(); 1831 1832 show_ucode_info_early(); 1833 1834 pr_info("Initializing CPU#%d\n", cpu); 1835 1836 if (cpu_feature_enabled(X86_FEATURE_VME) || 1837 boot_cpu_has(X86_FEATURE_TSC) || 1838 boot_cpu_has(X86_FEATURE_DE)) 1839 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1840 1841 load_current_idt(); 1842 switch_to_new_gdt(cpu); 1843 1844 /* 1845 * Set up and load the per-CPU TSS and LDT 1846 */ 1847 mmgrab(&init_mm); 1848 curr->active_mm = &init_mm; 1849 BUG_ON(curr->mm); 1850 initialize_tlbstate_and_flush(); 1851 enter_lazy_tlb(&init_mm, curr); 1852 1853 /* 1854 * Initialize the TSS. sp0 points to the entry trampoline stack 1855 * regardless of what task is running. 1856 */ 1857 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1858 load_TR_desc(); 1859 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1860 1861 load_mm_ldt(&init_mm); 1862 1863 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1864 1865 #ifdef CONFIG_DOUBLEFAULT 1866 /* Set up doublefault TSS pointer in the GDT */ 1867 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1868 #endif 1869 1870 clear_all_debug_regs(); 1871 dbg_restore_debug_regs(); 1872 1873 fpu__init_cpu(); 1874 1875 load_fixmap_gdt(cpu); 1876 } 1877 #endif 1878 1879 /* 1880 * The microcode loader calls this upon late microcode load to recheck features, 1881 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1882 * hotplug lock. 1883 */ 1884 void microcode_check(void) 1885 { 1886 struct cpuinfo_x86 info; 1887 1888 perf_check_microcode(); 1889 1890 /* Reload CPUID max function as it might've changed. */ 1891 info.cpuid_level = cpuid_eax(0); 1892 1893 /* 1894 * Copy all capability leafs to pick up the synthetic ones so that 1895 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1896 * get overwritten in get_cpu_cap(). 1897 */ 1898 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1899 1900 get_cpu_cap(&info); 1901 1902 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1903 return; 1904 1905 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1906 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1907 } 1908