1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_counter.h> 17 #include <asm/mmu_context.h> 18 #include <asm/hypervisor.h> 19 #include <asm/processor.h> 20 #include <asm/sections.h> 21 #include <asm/topology.h> 22 #include <asm/cpumask.h> 23 #include <asm/pgtable.h> 24 #include <asm/atomic.h> 25 #include <asm/proto.h> 26 #include <asm/setup.h> 27 #include <asm/apic.h> 28 #include <asm/desc.h> 29 #include <asm/i387.h> 30 #include <asm/mtrr.h> 31 #include <asm/numa.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/mce.h> 35 #include <asm/msr.h> 36 #include <asm/pat.h> 37 #include <asm/smp.h> 38 39 #ifdef CONFIG_X86_LOCAL_APIC 40 #include <asm/uv/uv.h> 41 #endif 42 43 #include "cpu.h" 44 45 /* all of these masks are initialized in setup_cpu_local_masks() */ 46 cpumask_var_t cpu_initialized_mask; 47 cpumask_var_t cpu_callout_mask; 48 cpumask_var_t cpu_callin_mask; 49 50 /* representing cpus for which sibling maps can be computed */ 51 cpumask_var_t cpu_sibling_setup_mask; 52 53 /* correctly size the local cpu masks */ 54 void __init setup_cpu_local_masks(void) 55 { 56 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 57 alloc_bootmem_cpumask_var(&cpu_callin_mask); 58 alloc_bootmem_cpumask_var(&cpu_callout_mask); 59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 60 } 61 62 static const struct cpu_dev *this_cpu __cpuinitdata; 63 64 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 65 #ifdef CONFIG_X86_64 66 /* 67 * We need valid kernel segments for data and code in long mode too 68 * IRET will check the segment types kkeil 2000/10/28 69 * Also sysret mandates a special GDT layout 70 * 71 * TLS descriptors are currently at a different place compared to i386. 72 * Hopefully nobody expects them at a fixed place (Wine?) 73 */ 74 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, 75 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, 76 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, 77 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, 78 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, 79 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, 80 #else 81 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 82 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 83 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 84 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 85 /* 86 * Segments used for calling PnP BIOS have byte granularity. 87 * They code segments and data segments have fixed 64k limits, 88 * the transfer segment sizes are set at run time. 89 */ 90 /* 32-bit code */ 91 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 92 /* 16-bit code */ 93 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 94 /* 16-bit data */ 95 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 96 /* 16-bit data */ 97 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 98 /* 16-bit data */ 99 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 100 /* 101 * The APM segments have byte granularity and their bases 102 * are set at run time. All have 64k limits. 103 */ 104 /* 32-bit code */ 105 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 106 /* 16-bit code */ 107 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 108 /* data */ 109 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 110 111 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, 112 [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, 113 GDT_STACK_CANARY_INIT 114 #endif 115 } }; 116 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 117 118 static int __init x86_xsave_setup(char *s) 119 { 120 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 121 return 1; 122 } 123 __setup("noxsave", x86_xsave_setup); 124 125 #ifdef CONFIG_X86_32 126 static int cachesize_override __cpuinitdata = -1; 127 static int disable_x86_serial_nr __cpuinitdata = 1; 128 129 static int __init cachesize_setup(char *str) 130 { 131 get_option(&str, &cachesize_override); 132 return 1; 133 } 134 __setup("cachesize=", cachesize_setup); 135 136 static int __init x86_fxsr_setup(char *s) 137 { 138 setup_clear_cpu_cap(X86_FEATURE_FXSR); 139 setup_clear_cpu_cap(X86_FEATURE_XMM); 140 return 1; 141 } 142 __setup("nofxsr", x86_fxsr_setup); 143 144 static int __init x86_sep_setup(char *s) 145 { 146 setup_clear_cpu_cap(X86_FEATURE_SEP); 147 return 1; 148 } 149 __setup("nosep", x86_sep_setup); 150 151 /* Standard macro to see if a specific flag is changeable */ 152 static inline int flag_is_changeable_p(u32 flag) 153 { 154 u32 f1, f2; 155 156 /* 157 * Cyrix and IDT cpus allow disabling of CPUID 158 * so the code below may return different results 159 * when it is executed before and after enabling 160 * the CPUID. Add "volatile" to not allow gcc to 161 * optimize the subsequent calls to this function. 162 */ 163 asm volatile ("pushfl \n\t" 164 "pushfl \n\t" 165 "popl %0 \n\t" 166 "movl %0, %1 \n\t" 167 "xorl %2, %0 \n\t" 168 "pushl %0 \n\t" 169 "popfl \n\t" 170 "pushfl \n\t" 171 "popl %0 \n\t" 172 "popfl \n\t" 173 174 : "=&r" (f1), "=&r" (f2) 175 : "ir" (flag)); 176 177 return ((f1^f2) & flag) != 0; 178 } 179 180 /* Probe for the CPUID instruction */ 181 static int __cpuinit have_cpuid_p(void) 182 { 183 return flag_is_changeable_p(X86_EFLAGS_ID); 184 } 185 186 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 187 { 188 unsigned long lo, hi; 189 190 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 191 return; 192 193 /* Disable processor serial number: */ 194 195 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 196 lo |= 0x200000; 197 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 198 199 printk(KERN_NOTICE "CPU serial number disabled.\n"); 200 clear_cpu_cap(c, X86_FEATURE_PN); 201 202 /* Disabling the serial number may affect the cpuid level */ 203 c->cpuid_level = cpuid_eax(0); 204 } 205 206 static int __init x86_serial_nr_setup(char *s) 207 { 208 disable_x86_serial_nr = 0; 209 return 1; 210 } 211 __setup("serialnumber", x86_serial_nr_setup); 212 #else 213 static inline int flag_is_changeable_p(u32 flag) 214 { 215 return 1; 216 } 217 /* Probe for the CPUID instruction */ 218 static inline int have_cpuid_p(void) 219 { 220 return 1; 221 } 222 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 223 { 224 } 225 #endif 226 227 /* 228 * Some CPU features depend on higher CPUID levels, which may not always 229 * be available due to CPUID level capping or broken virtualization 230 * software. Add those features to this table to auto-disable them. 231 */ 232 struct cpuid_dependent_feature { 233 u32 feature; 234 u32 level; 235 }; 236 237 static const struct cpuid_dependent_feature __cpuinitconst 238 cpuid_dependent_features[] = { 239 { X86_FEATURE_MWAIT, 0x00000005 }, 240 { X86_FEATURE_DCA, 0x00000009 }, 241 { X86_FEATURE_XSAVE, 0x0000000d }, 242 { 0, 0 } 243 }; 244 245 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 246 { 247 const struct cpuid_dependent_feature *df; 248 249 for (df = cpuid_dependent_features; df->feature; df++) { 250 251 if (!cpu_has(c, df->feature)) 252 continue; 253 /* 254 * Note: cpuid_level is set to -1 if unavailable, but 255 * extended_extended_level is set to 0 if unavailable 256 * and the legitimate extended levels are all negative 257 * when signed; hence the weird messing around with 258 * signs here... 259 */ 260 if (!((s32)df->level < 0 ? 261 (u32)df->level > (u32)c->extended_cpuid_level : 262 (s32)df->level > (s32)c->cpuid_level)) 263 continue; 264 265 clear_cpu_cap(c, df->feature); 266 if (!warn) 267 continue; 268 269 printk(KERN_WARNING 270 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 271 x86_cap_flags[df->feature], df->level); 272 } 273 } 274 275 /* 276 * Naming convention should be: <Name> [(<Codename>)] 277 * This table only is used unless init_<vendor>() below doesn't set it; 278 * in particular, if CPUID levels 0x80000002..4 are supported, this 279 * isn't used 280 */ 281 282 /* Look up CPU names by table lookup. */ 283 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 284 { 285 const struct cpu_model_info *info; 286 287 if (c->x86_model >= 16) 288 return NULL; /* Range check */ 289 290 if (!this_cpu) 291 return NULL; 292 293 info = this_cpu->c_models; 294 295 while (info && info->family) { 296 if (info->family == c->x86) 297 return info->model_names[c->x86_model]; 298 info++; 299 } 300 return NULL; /* Not found */ 301 } 302 303 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; 304 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; 305 306 void load_percpu_segment(int cpu) 307 { 308 #ifdef CONFIG_X86_32 309 loadsegment(fs, __KERNEL_PERCPU); 310 #else 311 loadsegment(gs, 0); 312 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 313 #endif 314 load_stack_canary_segment(); 315 } 316 317 /* 318 * Current gdt points %fs at the "master" per-cpu area: after this, 319 * it's on the real one. 320 */ 321 void switch_to_new_gdt(int cpu) 322 { 323 struct desc_ptr gdt_descr; 324 325 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 326 gdt_descr.size = GDT_SIZE - 1; 327 load_gdt(&gdt_descr); 328 /* Reload the per-cpu base */ 329 330 load_percpu_segment(cpu); 331 } 332 333 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 334 335 static void __cpuinit default_init(struct cpuinfo_x86 *c) 336 { 337 #ifdef CONFIG_X86_64 338 display_cacheinfo(c); 339 #else 340 /* Not much we can do here... */ 341 /* Check if at least it has cpuid */ 342 if (c->cpuid_level == -1) { 343 /* No cpuid. It must be an ancient CPU */ 344 if (c->x86 == 4) 345 strcpy(c->x86_model_id, "486"); 346 else if (c->x86 == 3) 347 strcpy(c->x86_model_id, "386"); 348 } 349 #endif 350 } 351 352 static const struct cpu_dev __cpuinitconst default_cpu = { 353 .c_init = default_init, 354 .c_vendor = "Unknown", 355 .c_x86_vendor = X86_VENDOR_UNKNOWN, 356 }; 357 358 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 359 { 360 unsigned int *v; 361 char *p, *q; 362 363 if (c->extended_cpuid_level < 0x80000004) 364 return; 365 366 v = (unsigned int *)c->x86_model_id; 367 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 368 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 369 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 370 c->x86_model_id[48] = 0; 371 372 /* 373 * Intel chips right-justify this string for some dumb reason; 374 * undo that brain damage: 375 */ 376 p = q = &c->x86_model_id[0]; 377 while (*p == ' ') 378 p++; 379 if (p != q) { 380 while (*p) 381 *q++ = *p++; 382 while (q <= &c->x86_model_id[48]) 383 *q++ = '\0'; /* Zero-pad the rest */ 384 } 385 } 386 387 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 388 { 389 unsigned int n, dummy, ebx, ecx, edx, l2size; 390 391 n = c->extended_cpuid_level; 392 393 if (n >= 0x80000005) { 394 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 395 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 396 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 397 c->x86_cache_size = (ecx>>24) + (edx>>24); 398 #ifdef CONFIG_X86_64 399 /* On K8 L1 TLB is inclusive, so don't count it */ 400 c->x86_tlbsize = 0; 401 #endif 402 } 403 404 if (n < 0x80000006) /* Some chips just has a large L1. */ 405 return; 406 407 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 408 l2size = ecx >> 16; 409 410 #ifdef CONFIG_X86_64 411 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 412 #else 413 /* do processor-specific cache resizing */ 414 if (this_cpu->c_size_cache) 415 l2size = this_cpu->c_size_cache(c, l2size); 416 417 /* Allow user to override all this if necessary. */ 418 if (cachesize_override != -1) 419 l2size = cachesize_override; 420 421 if (l2size == 0) 422 return; /* Again, no L2 cache is possible */ 423 #endif 424 425 c->x86_cache_size = l2size; 426 427 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 428 l2size, ecx & 0xFF); 429 } 430 431 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 432 { 433 #ifdef CONFIG_X86_HT 434 u32 eax, ebx, ecx, edx; 435 int index_msb, core_bits; 436 437 if (!cpu_has(c, X86_FEATURE_HT)) 438 return; 439 440 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 441 goto out; 442 443 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 444 return; 445 446 cpuid(1, &eax, &ebx, &ecx, &edx); 447 448 smp_num_siblings = (ebx & 0xff0000) >> 16; 449 450 if (smp_num_siblings == 1) { 451 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 452 goto out; 453 } 454 455 if (smp_num_siblings <= 1) 456 goto out; 457 458 if (smp_num_siblings > nr_cpu_ids) { 459 pr_warning("CPU: Unsupported number of siblings %d", 460 smp_num_siblings); 461 smp_num_siblings = 1; 462 return; 463 } 464 465 index_msb = get_count_order(smp_num_siblings); 466 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 467 468 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 469 470 index_msb = get_count_order(smp_num_siblings); 471 472 core_bits = get_count_order(c->x86_max_cores); 473 474 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 475 ((1 << core_bits) - 1); 476 477 out: 478 if ((c->x86_max_cores * smp_num_siblings) > 1) { 479 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 480 c->phys_proc_id); 481 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 482 c->cpu_core_id); 483 } 484 #endif 485 } 486 487 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 488 { 489 char *v = c->x86_vendor_id; 490 static int printed; 491 int i; 492 493 for (i = 0; i < X86_VENDOR_NUM; i++) { 494 if (!cpu_devs[i]) 495 break; 496 497 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 498 (cpu_devs[i]->c_ident[1] && 499 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 500 501 this_cpu = cpu_devs[i]; 502 c->x86_vendor = this_cpu->c_x86_vendor; 503 return; 504 } 505 } 506 507 if (!printed) { 508 printed++; 509 printk(KERN_ERR 510 "CPU: vendor_id '%s' unknown, using generic init.\n", v); 511 512 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 513 } 514 515 c->x86_vendor = X86_VENDOR_UNKNOWN; 516 this_cpu = &default_cpu; 517 } 518 519 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 520 { 521 /* Get vendor name */ 522 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 523 (unsigned int *)&c->x86_vendor_id[0], 524 (unsigned int *)&c->x86_vendor_id[8], 525 (unsigned int *)&c->x86_vendor_id[4]); 526 527 c->x86 = 4; 528 /* Intel-defined flags: level 0x00000001 */ 529 if (c->cpuid_level >= 0x00000001) { 530 u32 junk, tfms, cap0, misc; 531 532 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 533 c->x86 = (tfms >> 8) & 0xf; 534 c->x86_model = (tfms >> 4) & 0xf; 535 c->x86_mask = tfms & 0xf; 536 537 if (c->x86 == 0xf) 538 c->x86 += (tfms >> 20) & 0xff; 539 if (c->x86 >= 0x6) 540 c->x86_model += ((tfms >> 16) & 0xf) << 4; 541 542 if (cap0 & (1<<19)) { 543 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 544 c->x86_cache_alignment = c->x86_clflush_size; 545 } 546 } 547 } 548 549 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 550 { 551 u32 tfms, xlvl; 552 u32 ebx; 553 554 /* Intel-defined flags: level 0x00000001 */ 555 if (c->cpuid_level >= 0x00000001) { 556 u32 capability, excap; 557 558 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 559 c->x86_capability[0] = capability; 560 c->x86_capability[4] = excap; 561 } 562 563 /* AMD-defined flags: level 0x80000001 */ 564 xlvl = cpuid_eax(0x80000000); 565 c->extended_cpuid_level = xlvl; 566 567 if ((xlvl & 0xffff0000) == 0x80000000) { 568 if (xlvl >= 0x80000001) { 569 c->x86_capability[1] = cpuid_edx(0x80000001); 570 c->x86_capability[6] = cpuid_ecx(0x80000001); 571 } 572 } 573 574 if (c->extended_cpuid_level >= 0x80000008) { 575 u32 eax = cpuid_eax(0x80000008); 576 577 c->x86_virt_bits = (eax >> 8) & 0xff; 578 c->x86_phys_bits = eax & 0xff; 579 } 580 #ifdef CONFIG_X86_32 581 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 582 c->x86_phys_bits = 36; 583 #endif 584 585 if (c->extended_cpuid_level >= 0x80000007) 586 c->x86_power = cpuid_edx(0x80000007); 587 588 } 589 590 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 591 { 592 #ifdef CONFIG_X86_32 593 int i; 594 595 /* 596 * First of all, decide if this is a 486 or higher 597 * It's a 486 if we can modify the AC flag 598 */ 599 if (flag_is_changeable_p(X86_EFLAGS_AC)) 600 c->x86 = 4; 601 else 602 c->x86 = 3; 603 604 for (i = 0; i < X86_VENDOR_NUM; i++) 605 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 606 c->x86_vendor_id[0] = 0; 607 cpu_devs[i]->c_identify(c); 608 if (c->x86_vendor_id[0]) { 609 get_cpu_vendor(c); 610 break; 611 } 612 } 613 #endif 614 } 615 616 /* 617 * Do minimum CPU detection early. 618 * Fields really needed: vendor, cpuid_level, family, model, mask, 619 * cache alignment. 620 * The others are not touched to avoid unwanted side effects. 621 * 622 * WARNING: this function is only called on the BP. Don't add code here 623 * that is supposed to run on all CPUs. 624 */ 625 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 626 { 627 #ifdef CONFIG_X86_64 628 c->x86_clflush_size = 64; 629 c->x86_phys_bits = 36; 630 c->x86_virt_bits = 48; 631 #else 632 c->x86_clflush_size = 32; 633 c->x86_phys_bits = 32; 634 c->x86_virt_bits = 32; 635 #endif 636 c->x86_cache_alignment = c->x86_clflush_size; 637 638 memset(&c->x86_capability, 0, sizeof c->x86_capability); 639 c->extended_cpuid_level = 0; 640 641 if (!have_cpuid_p()) 642 identify_cpu_without_cpuid(c); 643 644 /* cyrix could have cpuid enabled via c_identify()*/ 645 if (!have_cpuid_p()) 646 return; 647 648 cpu_detect(c); 649 650 get_cpu_vendor(c); 651 652 get_cpu_cap(c); 653 654 if (this_cpu->c_early_init) 655 this_cpu->c_early_init(c); 656 657 #ifdef CONFIG_SMP 658 c->cpu_index = boot_cpu_id; 659 #endif 660 filter_cpuid_features(c, false); 661 } 662 663 void __init early_cpu_init(void) 664 { 665 const struct cpu_dev *const *cdev; 666 int count = 0; 667 668 printk(KERN_INFO "KERNEL supported cpus:\n"); 669 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 670 const struct cpu_dev *cpudev = *cdev; 671 unsigned int j; 672 673 if (count >= X86_VENDOR_NUM) 674 break; 675 cpu_devs[count] = cpudev; 676 count++; 677 678 for (j = 0; j < 2; j++) { 679 if (!cpudev->c_ident[j]) 680 continue; 681 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 682 cpudev->c_ident[j]); 683 } 684 } 685 686 early_identify_cpu(&boot_cpu_data); 687 } 688 689 /* 690 * The NOPL instruction is supposed to exist on all CPUs with 691 * family >= 6; unfortunately, that's not true in practice because 692 * of early VIA chips and (more importantly) broken virtualizers that 693 * are not easy to detect. In the latter case it doesn't even *fail* 694 * reliably, so probing for it doesn't even work. Disable it completely 695 * unless we can find a reliable way to detect all the broken cases. 696 */ 697 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 698 { 699 clear_cpu_cap(c, X86_FEATURE_NOPL); 700 } 701 702 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 703 { 704 c->extended_cpuid_level = 0; 705 706 if (!have_cpuid_p()) 707 identify_cpu_without_cpuid(c); 708 709 /* cyrix could have cpuid enabled via c_identify()*/ 710 if (!have_cpuid_p()) 711 return; 712 713 cpu_detect(c); 714 715 get_cpu_vendor(c); 716 717 get_cpu_cap(c); 718 719 if (c->cpuid_level >= 0x00000001) { 720 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 721 #ifdef CONFIG_X86_32 722 # ifdef CONFIG_X86_HT 723 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 724 # else 725 c->apicid = c->initial_apicid; 726 # endif 727 #endif 728 729 #ifdef CONFIG_X86_HT 730 c->phys_proc_id = c->initial_apicid; 731 #endif 732 } 733 734 get_model_name(c); /* Default name */ 735 736 init_scattered_cpuid_features(c); 737 detect_nopl(c); 738 } 739 740 /* 741 * This does the hard work of actually picking apart the CPU stuff... 742 */ 743 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 744 { 745 int i; 746 747 c->loops_per_jiffy = loops_per_jiffy; 748 c->x86_cache_size = -1; 749 c->x86_vendor = X86_VENDOR_UNKNOWN; 750 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 751 c->x86_vendor_id[0] = '\0'; /* Unset */ 752 c->x86_model_id[0] = '\0'; /* Unset */ 753 c->x86_max_cores = 1; 754 c->x86_coreid_bits = 0; 755 #ifdef CONFIG_X86_64 756 c->x86_clflush_size = 64; 757 c->x86_phys_bits = 36; 758 c->x86_virt_bits = 48; 759 #else 760 c->cpuid_level = -1; /* CPUID not detected */ 761 c->x86_clflush_size = 32; 762 c->x86_phys_bits = 32; 763 c->x86_virt_bits = 32; 764 #endif 765 c->x86_cache_alignment = c->x86_clflush_size; 766 memset(&c->x86_capability, 0, sizeof c->x86_capability); 767 768 generic_identify(c); 769 770 if (this_cpu->c_identify) 771 this_cpu->c_identify(c); 772 773 /* Clear/Set all flags overriden by options, after probe */ 774 for (i = 0; i < NCAPINTS; i++) { 775 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 776 c->x86_capability[i] |= cpu_caps_set[i]; 777 } 778 779 #ifdef CONFIG_X86_64 780 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 781 #endif 782 783 /* 784 * Vendor-specific initialization. In this section we 785 * canonicalize the feature flags, meaning if there are 786 * features a certain CPU supports which CPUID doesn't 787 * tell us, CPUID claiming incorrect flags, or other bugs, 788 * we handle them here. 789 * 790 * At the end of this section, c->x86_capability better 791 * indicate the features this CPU genuinely supports! 792 */ 793 if (this_cpu->c_init) 794 this_cpu->c_init(c); 795 796 /* Disable the PN if appropriate */ 797 squash_the_stupid_serial_number(c); 798 799 /* 800 * The vendor-specific functions might have changed features. 801 * Now we do "generic changes." 802 */ 803 804 /* Filter out anything that depends on CPUID levels we don't have */ 805 filter_cpuid_features(c, true); 806 807 /* If the model name is still unset, do table lookup. */ 808 if (!c->x86_model_id[0]) { 809 const char *p; 810 p = table_lookup_model(c); 811 if (p) 812 strcpy(c->x86_model_id, p); 813 else 814 /* Last resort... */ 815 sprintf(c->x86_model_id, "%02x/%02x", 816 c->x86, c->x86_model); 817 } 818 819 #ifdef CONFIG_X86_64 820 detect_ht(c); 821 #endif 822 823 init_hypervisor(c); 824 825 /* 826 * Clear/Set all flags overriden by options, need do it 827 * before following smp all cpus cap AND. 828 */ 829 for (i = 0; i < NCAPINTS; i++) { 830 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 831 c->x86_capability[i] |= cpu_caps_set[i]; 832 } 833 834 /* 835 * On SMP, boot_cpu_data holds the common feature set between 836 * all CPUs; so make sure that we indicate which features are 837 * common between the CPUs. The first time this routine gets 838 * executed, c == &boot_cpu_data. 839 */ 840 if (c != &boot_cpu_data) { 841 /* AND the already accumulated flags with these */ 842 for (i = 0; i < NCAPINTS; i++) 843 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 844 } 845 846 #ifdef CONFIG_X86_MCE 847 /* Init Machine Check Exception if available. */ 848 mcheck_init(c); 849 #endif 850 851 select_idle_routine(c); 852 853 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 854 numa_add_cpu(smp_processor_id()); 855 #endif 856 } 857 858 #ifdef CONFIG_X86_64 859 static void vgetcpu_set_mode(void) 860 { 861 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 862 vgetcpu_mode = VGETCPU_RDTSCP; 863 else 864 vgetcpu_mode = VGETCPU_LSL; 865 } 866 #endif 867 868 void __init identify_boot_cpu(void) 869 { 870 identify_cpu(&boot_cpu_data); 871 init_c1e_mask(); 872 #ifdef CONFIG_X86_32 873 sysenter_setup(); 874 enable_sep_cpu(); 875 #else 876 vgetcpu_set_mode(); 877 #endif 878 init_hw_perf_counters(); 879 } 880 881 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 882 { 883 BUG_ON(c == &boot_cpu_data); 884 identify_cpu(c); 885 #ifdef CONFIG_X86_32 886 enable_sep_cpu(); 887 #endif 888 mtrr_ap_init(); 889 } 890 891 struct msr_range { 892 unsigned min; 893 unsigned max; 894 }; 895 896 static const struct msr_range msr_range_array[] __cpuinitconst = { 897 { 0x00000000, 0x00000418}, 898 { 0xc0000000, 0xc000040b}, 899 { 0xc0010000, 0xc0010142}, 900 { 0xc0011000, 0xc001103b}, 901 }; 902 903 static void __cpuinit print_cpu_msr(void) 904 { 905 unsigned index_min, index_max; 906 unsigned index; 907 u64 val; 908 int i; 909 910 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 911 index_min = msr_range_array[i].min; 912 index_max = msr_range_array[i].max; 913 914 for (index = index_min; index < index_max; index++) { 915 if (rdmsrl_amd_safe(index, &val)) 916 continue; 917 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 918 } 919 } 920 } 921 922 static int show_msr __cpuinitdata; 923 924 static __init int setup_show_msr(char *arg) 925 { 926 int num; 927 928 get_option(&arg, &num); 929 930 if (num > 0) 931 show_msr = num; 932 return 1; 933 } 934 __setup("show_msr=", setup_show_msr); 935 936 static __init int setup_noclflush(char *arg) 937 { 938 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 939 return 1; 940 } 941 __setup("noclflush", setup_noclflush); 942 943 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 944 { 945 const char *vendor = NULL; 946 947 if (c->x86_vendor < X86_VENDOR_NUM) { 948 vendor = this_cpu->c_vendor; 949 } else { 950 if (c->cpuid_level >= 0) 951 vendor = c->x86_vendor_id; 952 } 953 954 if (vendor && !strstr(c->x86_model_id, vendor)) 955 printk(KERN_CONT "%s ", vendor); 956 957 if (c->x86_model_id[0]) 958 printk(KERN_CONT "%s", c->x86_model_id); 959 else 960 printk(KERN_CONT "%d86", c->x86); 961 962 if (c->x86_mask || c->cpuid_level >= 0) 963 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 964 else 965 printk(KERN_CONT "\n"); 966 967 #ifdef CONFIG_SMP 968 if (c->cpu_index < show_msr) 969 print_cpu_msr(); 970 #else 971 if (show_msr) 972 print_cpu_msr(); 973 #endif 974 } 975 976 static __init int setup_disablecpuid(char *arg) 977 { 978 int bit; 979 980 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 981 setup_clear_cpu_cap(bit); 982 else 983 return 0; 984 985 return 1; 986 } 987 __setup("clearcpuid=", setup_disablecpuid); 988 989 #ifdef CONFIG_X86_64 990 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; 991 992 DEFINE_PER_CPU_FIRST(union irq_stack_union, 993 irq_stack_union) __aligned(PAGE_SIZE); 994 995 DEFINE_PER_CPU(char *, irq_stack_ptr) = 996 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 997 998 DEFINE_PER_CPU(unsigned long, kernel_stack) = 999 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1000 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1001 1002 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 1003 1004 /* 1005 * Special IST stacks which the CPU switches to when it calls 1006 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1007 * limit), all of them are 4K, except the debug stack which 1008 * is 8K. 1009 */ 1010 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1011 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1012 [DEBUG_STACK - 1] = DEBUG_STKSZ 1013 }; 1014 1015 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1016 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) 1017 __aligned(PAGE_SIZE); 1018 1019 /* May not be marked __init: used by software suspend */ 1020 void syscall_init(void) 1021 { 1022 /* 1023 * LSTAR and STAR live in a bit strange symbiosis. 1024 * They both write to the same internal register. STAR allows to 1025 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1026 */ 1027 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1028 wrmsrl(MSR_LSTAR, system_call); 1029 wrmsrl(MSR_CSTAR, ignore_sysret); 1030 1031 #ifdef CONFIG_IA32_EMULATION 1032 syscall32_cpu_init(); 1033 #endif 1034 1035 /* Flags to clear on syscall */ 1036 wrmsrl(MSR_SYSCALL_MASK, 1037 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 1038 } 1039 1040 unsigned long kernel_eflags; 1041 1042 /* 1043 * Copies of the original ist values from the tss are only accessed during 1044 * debugging, no special alignment required. 1045 */ 1046 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1047 1048 #else /* CONFIG_X86_64 */ 1049 1050 #ifdef CONFIG_CC_STACKPROTECTOR 1051 DEFINE_PER_CPU(unsigned long, stack_canary); 1052 #endif 1053 1054 /* Make sure %fs and %gs are initialized properly in idle threads */ 1055 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 1056 { 1057 memset(regs, 0, sizeof(struct pt_regs)); 1058 regs->fs = __KERNEL_PERCPU; 1059 regs->gs = __KERNEL_STACK_CANARY; 1060 1061 return regs; 1062 } 1063 #endif /* CONFIG_X86_64 */ 1064 1065 /* 1066 * Clear all 6 debug registers: 1067 */ 1068 static void clear_all_debug_regs(void) 1069 { 1070 int i; 1071 1072 for (i = 0; i < 8; i++) { 1073 /* Ignore db4, db5 */ 1074 if ((i == 4) || (i == 5)) 1075 continue; 1076 1077 set_debugreg(0, i); 1078 } 1079 } 1080 1081 /* 1082 * cpu_init() initializes state that is per-CPU. Some data is already 1083 * initialized (naturally) in the bootstrap process, such as the GDT 1084 * and IDT. We reload them nevertheless, this function acts as a 1085 * 'CPU state barrier', nothing should get across. 1086 * A lot of state is already set up in PDA init for 64 bit 1087 */ 1088 #ifdef CONFIG_X86_64 1089 1090 void __cpuinit cpu_init(void) 1091 { 1092 struct orig_ist *orig_ist; 1093 struct task_struct *me; 1094 struct tss_struct *t; 1095 unsigned long v; 1096 int cpu; 1097 int i; 1098 1099 cpu = stack_smp_processor_id(); 1100 t = &per_cpu(init_tss, cpu); 1101 orig_ist = &per_cpu(orig_ist, cpu); 1102 1103 #ifdef CONFIG_NUMA 1104 if (cpu != 0 && percpu_read(node_number) == 0 && 1105 cpu_to_node(cpu) != NUMA_NO_NODE) 1106 percpu_write(node_number, cpu_to_node(cpu)); 1107 #endif 1108 1109 me = current; 1110 1111 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1112 panic("CPU#%d already initialized!\n", cpu); 1113 1114 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1115 1116 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1117 1118 /* 1119 * Initialize the per-CPU GDT with the boot GDT, 1120 * and set up the GDT descriptor: 1121 */ 1122 1123 switch_to_new_gdt(cpu); 1124 loadsegment(fs, 0); 1125 1126 load_idt((const struct desc_ptr *)&idt_descr); 1127 1128 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1129 syscall_init(); 1130 1131 wrmsrl(MSR_FS_BASE, 0); 1132 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1133 barrier(); 1134 1135 check_efer(); 1136 if (cpu != 0) 1137 enable_x2apic(); 1138 1139 /* 1140 * set up and load the per-CPU TSS 1141 */ 1142 if (!orig_ist->ist[0]) { 1143 char *estacks = per_cpu(exception_stacks, cpu); 1144 1145 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1146 estacks += exception_stack_sizes[v]; 1147 orig_ist->ist[v] = t->x86_tss.ist[v] = 1148 (unsigned long)estacks; 1149 } 1150 } 1151 1152 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1153 1154 /* 1155 * <= is required because the CPU will access up to 1156 * 8 bits beyond the end of the IO permission bitmap. 1157 */ 1158 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1159 t->io_bitmap[i] = ~0UL; 1160 1161 atomic_inc(&init_mm.mm_count); 1162 me->active_mm = &init_mm; 1163 BUG_ON(me->mm); 1164 enter_lazy_tlb(&init_mm, me); 1165 1166 load_sp0(t, ¤t->thread); 1167 set_tss_desc(cpu, t); 1168 load_TR_desc(); 1169 load_LDT(&init_mm.context); 1170 1171 #ifdef CONFIG_KGDB 1172 /* 1173 * If the kgdb is connected no debug regs should be altered. This 1174 * is only applicable when KGDB and a KGDB I/O module are built 1175 * into the kernel and you are using early debugging with 1176 * kgdbwait. KGDB will control the kernel HW breakpoint registers. 1177 */ 1178 if (kgdb_connected && arch_kgdb_ops.correct_hw_break) 1179 arch_kgdb_ops.correct_hw_break(); 1180 else 1181 #endif 1182 clear_all_debug_regs(); 1183 1184 fpu_init(); 1185 1186 raw_local_save_flags(kernel_eflags); 1187 1188 if (is_uv_system()) 1189 uv_cpu_init(); 1190 } 1191 1192 #else 1193 1194 void __cpuinit cpu_init(void) 1195 { 1196 int cpu = smp_processor_id(); 1197 struct task_struct *curr = current; 1198 struct tss_struct *t = &per_cpu(init_tss, cpu); 1199 struct thread_struct *thread = &curr->thread; 1200 1201 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1202 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1203 for (;;) 1204 local_irq_enable(); 1205 } 1206 1207 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1208 1209 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1210 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1211 1212 load_idt(&idt_descr); 1213 switch_to_new_gdt(cpu); 1214 1215 /* 1216 * Set up and load the per-CPU TSS and LDT 1217 */ 1218 atomic_inc(&init_mm.mm_count); 1219 curr->active_mm = &init_mm; 1220 BUG_ON(curr->mm); 1221 enter_lazy_tlb(&init_mm, curr); 1222 1223 load_sp0(t, thread); 1224 set_tss_desc(cpu, t); 1225 load_TR_desc(); 1226 load_LDT(&init_mm.context); 1227 1228 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1229 1230 #ifdef CONFIG_DOUBLEFAULT 1231 /* Set up doublefault TSS pointer in the GDT */ 1232 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1233 #endif 1234 1235 clear_all_debug_regs(); 1236 1237 /* 1238 * Force FPU initialization: 1239 */ 1240 if (cpu_has_xsave) 1241 current_thread_info()->status = TS_XSAVE; 1242 else 1243 current_thread_info()->status = 0; 1244 clear_used_math(); 1245 mxcsr_feature_mask_init(); 1246 1247 /* 1248 * Boot processor to setup the FP and extended state context info. 1249 */ 1250 if (smp_processor_id() == boot_cpu_id) 1251 init_thread_xstate(); 1252 1253 xsave_init(); 1254 } 1255 #endif 1256