1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_event.h> 17 #include <asm/mmu_context.h> 18 #include <asm/archrandom.h> 19 #include <asm/hypervisor.h> 20 #include <asm/processor.h> 21 #include <asm/debugreg.h> 22 #include <asm/sections.h> 23 #include <linux/topology.h> 24 #include <linux/cpumask.h> 25 #include <asm/pgtable.h> 26 #include <linux/atomic.h> 27 #include <asm/proto.h> 28 #include <asm/setup.h> 29 #include <asm/apic.h> 30 #include <asm/desc.h> 31 #include <asm/i387.h> 32 #include <asm/fpu-internal.h> 33 #include <asm/mtrr.h> 34 #include <linux/numa.h> 35 #include <asm/asm.h> 36 #include <asm/cpu.h> 37 #include <asm/mce.h> 38 #include <asm/msr.h> 39 #include <asm/pat.h> 40 41 #ifdef CONFIG_X86_LOCAL_APIC 42 #include <asm/uv/uv.h> 43 #endif 44 45 #include "cpu.h" 46 47 /* all of these masks are initialized in setup_cpu_local_masks() */ 48 cpumask_var_t cpu_initialized_mask; 49 cpumask_var_t cpu_callout_mask; 50 cpumask_var_t cpu_callin_mask; 51 52 /* representing cpus for which sibling maps can be computed */ 53 cpumask_var_t cpu_sibling_setup_mask; 54 55 /* correctly size the local cpu masks */ 56 void __init setup_cpu_local_masks(void) 57 { 58 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 59 alloc_bootmem_cpumask_var(&cpu_callin_mask); 60 alloc_bootmem_cpumask_var(&cpu_callout_mask); 61 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 62 } 63 64 static void __cpuinit default_init(struct cpuinfo_x86 *c) 65 { 66 #ifdef CONFIG_X86_64 67 cpu_detect_cache_sizes(c); 68 #else 69 /* Not much we can do here... */ 70 /* Check if at least it has cpuid */ 71 if (c->cpuid_level == -1) { 72 /* No cpuid. It must be an ancient CPU */ 73 if (c->x86 == 4) 74 strcpy(c->x86_model_id, "486"); 75 else if (c->x86 == 3) 76 strcpy(c->x86_model_id, "386"); 77 } 78 #endif 79 } 80 81 static const struct cpu_dev __cpuinitconst default_cpu = { 82 .c_init = default_init, 83 .c_vendor = "Unknown", 84 .c_x86_vendor = X86_VENDOR_UNKNOWN, 85 }; 86 87 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; 88 89 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 90 #ifdef CONFIG_X86_64 91 /* 92 * We need valid kernel segments for data and code in long mode too 93 * IRET will check the segment types kkeil 2000/10/28 94 * Also sysret mandates a special GDT layout 95 * 96 * TLS descriptors are currently at a different place compared to i386. 97 * Hopefully nobody expects them at a fixed place (Wine?) 98 */ 99 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 100 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 101 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 102 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 103 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 104 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 105 #else 106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 110 /* 111 * Segments used for calling PnP BIOS have byte granularity. 112 * They code segments and data segments have fixed 64k limits, 113 * the transfer segment sizes are set at run time. 114 */ 115 /* 32-bit code */ 116 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 117 /* 16-bit code */ 118 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 119 /* 16-bit data */ 120 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 121 /* 16-bit data */ 122 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 123 /* 16-bit data */ 124 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 125 /* 126 * The APM segments have byte granularity and their bases 127 * are set at run time. All have 64k limits. 128 */ 129 /* 32-bit code */ 130 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 131 /* 16-bit code */ 132 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 133 /* data */ 134 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 135 136 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 137 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 138 GDT_STACK_CANARY_INIT 139 #endif 140 } }; 141 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 142 143 static int __init x86_xsave_setup(char *s) 144 { 145 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 146 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 147 return 1; 148 } 149 __setup("noxsave", x86_xsave_setup); 150 151 static int __init x86_xsaveopt_setup(char *s) 152 { 153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 154 return 1; 155 } 156 __setup("noxsaveopt", x86_xsaveopt_setup); 157 158 #ifdef CONFIG_X86_32 159 static int cachesize_override __cpuinitdata = -1; 160 static int disable_x86_serial_nr __cpuinitdata = 1; 161 162 static int __init cachesize_setup(char *str) 163 { 164 get_option(&str, &cachesize_override); 165 return 1; 166 } 167 __setup("cachesize=", cachesize_setup); 168 169 static int __init x86_fxsr_setup(char *s) 170 { 171 setup_clear_cpu_cap(X86_FEATURE_FXSR); 172 setup_clear_cpu_cap(X86_FEATURE_XMM); 173 return 1; 174 } 175 __setup("nofxsr", x86_fxsr_setup); 176 177 static int __init x86_sep_setup(char *s) 178 { 179 setup_clear_cpu_cap(X86_FEATURE_SEP); 180 return 1; 181 } 182 __setup("nosep", x86_sep_setup); 183 184 /* Standard macro to see if a specific flag is changeable */ 185 static inline int flag_is_changeable_p(u32 flag) 186 { 187 u32 f1, f2; 188 189 /* 190 * Cyrix and IDT cpus allow disabling of CPUID 191 * so the code below may return different results 192 * when it is executed before and after enabling 193 * the CPUID. Add "volatile" to not allow gcc to 194 * optimize the subsequent calls to this function. 195 */ 196 asm volatile ("pushfl \n\t" 197 "pushfl \n\t" 198 "popl %0 \n\t" 199 "movl %0, %1 \n\t" 200 "xorl %2, %0 \n\t" 201 "pushl %0 \n\t" 202 "popfl \n\t" 203 "pushfl \n\t" 204 "popl %0 \n\t" 205 "popfl \n\t" 206 207 : "=&r" (f1), "=&r" (f2) 208 : "ir" (flag)); 209 210 return ((f1^f2) & flag) != 0; 211 } 212 213 /* Probe for the CPUID instruction */ 214 static int __cpuinit have_cpuid_p(void) 215 { 216 return flag_is_changeable_p(X86_EFLAGS_ID); 217 } 218 219 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 220 { 221 unsigned long lo, hi; 222 223 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 224 return; 225 226 /* Disable processor serial number: */ 227 228 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 229 lo |= 0x200000; 230 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 231 232 printk(KERN_NOTICE "CPU serial number disabled.\n"); 233 clear_cpu_cap(c, X86_FEATURE_PN); 234 235 /* Disabling the serial number may affect the cpuid level */ 236 c->cpuid_level = cpuid_eax(0); 237 } 238 239 static int __init x86_serial_nr_setup(char *s) 240 { 241 disable_x86_serial_nr = 0; 242 return 1; 243 } 244 __setup("serialnumber", x86_serial_nr_setup); 245 #else 246 static inline int flag_is_changeable_p(u32 flag) 247 { 248 return 1; 249 } 250 /* Probe for the CPUID instruction */ 251 static inline int have_cpuid_p(void) 252 { 253 return 1; 254 } 255 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 256 { 257 } 258 #endif 259 260 static int disable_smep __cpuinitdata; 261 static __init int setup_disable_smep(char *arg) 262 { 263 disable_smep = 1; 264 return 1; 265 } 266 __setup("nosmep", setup_disable_smep); 267 268 static __cpuinit void setup_smep(struct cpuinfo_x86 *c) 269 { 270 if (cpu_has(c, X86_FEATURE_SMEP)) { 271 if (unlikely(disable_smep)) { 272 setup_clear_cpu_cap(X86_FEATURE_SMEP); 273 clear_in_cr4(X86_CR4_SMEP); 274 } else 275 set_in_cr4(X86_CR4_SMEP); 276 } 277 } 278 279 /* 280 * Some CPU features depend on higher CPUID levels, which may not always 281 * be available due to CPUID level capping or broken virtualization 282 * software. Add those features to this table to auto-disable them. 283 */ 284 struct cpuid_dependent_feature { 285 u32 feature; 286 u32 level; 287 }; 288 289 static const struct cpuid_dependent_feature __cpuinitconst 290 cpuid_dependent_features[] = { 291 { X86_FEATURE_MWAIT, 0x00000005 }, 292 { X86_FEATURE_DCA, 0x00000009 }, 293 { X86_FEATURE_XSAVE, 0x0000000d }, 294 { 0, 0 } 295 }; 296 297 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 298 { 299 const struct cpuid_dependent_feature *df; 300 301 for (df = cpuid_dependent_features; df->feature; df++) { 302 303 if (!cpu_has(c, df->feature)) 304 continue; 305 /* 306 * Note: cpuid_level is set to -1 if unavailable, but 307 * extended_extended_level is set to 0 if unavailable 308 * and the legitimate extended levels are all negative 309 * when signed; hence the weird messing around with 310 * signs here... 311 */ 312 if (!((s32)df->level < 0 ? 313 (u32)df->level > (u32)c->extended_cpuid_level : 314 (s32)df->level > (s32)c->cpuid_level)) 315 continue; 316 317 clear_cpu_cap(c, df->feature); 318 if (!warn) 319 continue; 320 321 printk(KERN_WARNING 322 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 323 x86_cap_flags[df->feature], df->level); 324 } 325 } 326 327 /* 328 * Naming convention should be: <Name> [(<Codename>)] 329 * This table only is used unless init_<vendor>() below doesn't set it; 330 * in particular, if CPUID levels 0x80000002..4 are supported, this 331 * isn't used 332 */ 333 334 /* Look up CPU names by table lookup. */ 335 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 336 { 337 const struct cpu_model_info *info; 338 339 if (c->x86_model >= 16) 340 return NULL; /* Range check */ 341 342 if (!this_cpu) 343 return NULL; 344 345 info = this_cpu->c_models; 346 347 while (info && info->family) { 348 if (info->family == c->x86) 349 return info->model_names[c->x86_model]; 350 info++; 351 } 352 return NULL; /* Not found */ 353 } 354 355 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; 356 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; 357 358 void load_percpu_segment(int cpu) 359 { 360 #ifdef CONFIG_X86_32 361 loadsegment(fs, __KERNEL_PERCPU); 362 #else 363 loadsegment(gs, 0); 364 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 365 #endif 366 load_stack_canary_segment(); 367 } 368 369 /* 370 * Current gdt points %fs at the "master" per-cpu area: after this, 371 * it's on the real one. 372 */ 373 void switch_to_new_gdt(int cpu) 374 { 375 struct desc_ptr gdt_descr; 376 377 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 378 gdt_descr.size = GDT_SIZE - 1; 379 load_gdt(&gdt_descr); 380 /* Reload the per-cpu base */ 381 382 load_percpu_segment(cpu); 383 } 384 385 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 386 387 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 388 { 389 unsigned int *v; 390 char *p, *q; 391 392 if (c->extended_cpuid_level < 0x80000004) 393 return; 394 395 v = (unsigned int *)c->x86_model_id; 396 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 397 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 398 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 399 c->x86_model_id[48] = 0; 400 401 /* 402 * Intel chips right-justify this string for some dumb reason; 403 * undo that brain damage: 404 */ 405 p = q = &c->x86_model_id[0]; 406 while (*p == ' ') 407 p++; 408 if (p != q) { 409 while (*p) 410 *q++ = *p++; 411 while (q <= &c->x86_model_id[48]) 412 *q++ = '\0'; /* Zero-pad the rest */ 413 } 414 } 415 416 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 417 { 418 unsigned int n, dummy, ebx, ecx, edx, l2size; 419 420 n = c->extended_cpuid_level; 421 422 if (n >= 0x80000005) { 423 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 424 c->x86_cache_size = (ecx>>24) + (edx>>24); 425 #ifdef CONFIG_X86_64 426 /* On K8 L1 TLB is inclusive, so don't count it */ 427 c->x86_tlbsize = 0; 428 #endif 429 } 430 431 if (n < 0x80000006) /* Some chips just has a large L1. */ 432 return; 433 434 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 435 l2size = ecx >> 16; 436 437 #ifdef CONFIG_X86_64 438 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 439 #else 440 /* do processor-specific cache resizing */ 441 if (this_cpu->c_size_cache) 442 l2size = this_cpu->c_size_cache(c, l2size); 443 444 /* Allow user to override all this if necessary. */ 445 if (cachesize_override != -1) 446 l2size = cachesize_override; 447 448 if (l2size == 0) 449 return; /* Again, no L2 cache is possible */ 450 #endif 451 452 c->x86_cache_size = l2size; 453 } 454 455 u16 __read_mostly tlb_lli_4k[NR_INFO]; 456 u16 __read_mostly tlb_lli_2m[NR_INFO]; 457 u16 __read_mostly tlb_lli_4m[NR_INFO]; 458 u16 __read_mostly tlb_lld_4k[NR_INFO]; 459 u16 __read_mostly tlb_lld_2m[NR_INFO]; 460 u16 __read_mostly tlb_lld_4m[NR_INFO]; 461 462 /* 463 * tlb_flushall_shift shows the balance point in replacing cr3 write 464 * with multiple 'invlpg'. It will do this replacement when 465 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. 466 * If tlb_flushall_shift is -1, means the replacement will be disabled. 467 */ 468 s8 __read_mostly tlb_flushall_shift = -1; 469 470 void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c) 471 { 472 if (this_cpu->c_detect_tlb) 473 this_cpu->c_detect_tlb(c); 474 475 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 476 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 477 "tlb_flushall_shift is 0x%x\n", 478 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 479 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], 480 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], 481 tlb_flushall_shift); 482 } 483 484 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 485 { 486 #ifdef CONFIG_X86_HT 487 u32 eax, ebx, ecx, edx; 488 int index_msb, core_bits; 489 static bool printed; 490 491 if (!cpu_has(c, X86_FEATURE_HT)) 492 return; 493 494 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 495 goto out; 496 497 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 498 return; 499 500 cpuid(1, &eax, &ebx, &ecx, &edx); 501 502 smp_num_siblings = (ebx & 0xff0000) >> 16; 503 504 if (smp_num_siblings == 1) { 505 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 506 goto out; 507 } 508 509 if (smp_num_siblings <= 1) 510 goto out; 511 512 index_msb = get_count_order(smp_num_siblings); 513 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 514 515 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 516 517 index_msb = get_count_order(smp_num_siblings); 518 519 core_bits = get_count_order(c->x86_max_cores); 520 521 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 522 ((1 << core_bits) - 1); 523 524 out: 525 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 526 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 527 c->phys_proc_id); 528 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 529 c->cpu_core_id); 530 printed = 1; 531 } 532 #endif 533 } 534 535 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 536 { 537 char *v = c->x86_vendor_id; 538 int i; 539 540 for (i = 0; i < X86_VENDOR_NUM; i++) { 541 if (!cpu_devs[i]) 542 break; 543 544 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 545 (cpu_devs[i]->c_ident[1] && 546 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 547 548 this_cpu = cpu_devs[i]; 549 c->x86_vendor = this_cpu->c_x86_vendor; 550 return; 551 } 552 } 553 554 printk_once(KERN_ERR 555 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 556 "CPU: Your system may be unstable.\n", v); 557 558 c->x86_vendor = X86_VENDOR_UNKNOWN; 559 this_cpu = &default_cpu; 560 } 561 562 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 563 { 564 /* Get vendor name */ 565 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 566 (unsigned int *)&c->x86_vendor_id[0], 567 (unsigned int *)&c->x86_vendor_id[8], 568 (unsigned int *)&c->x86_vendor_id[4]); 569 570 c->x86 = 4; 571 /* Intel-defined flags: level 0x00000001 */ 572 if (c->cpuid_level >= 0x00000001) { 573 u32 junk, tfms, cap0, misc; 574 575 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 576 c->x86 = (tfms >> 8) & 0xf; 577 c->x86_model = (tfms >> 4) & 0xf; 578 c->x86_mask = tfms & 0xf; 579 580 if (c->x86 == 0xf) 581 c->x86 += (tfms >> 20) & 0xff; 582 if (c->x86 >= 0x6) 583 c->x86_model += ((tfms >> 16) & 0xf) << 4; 584 585 if (cap0 & (1<<19)) { 586 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 587 c->x86_cache_alignment = c->x86_clflush_size; 588 } 589 } 590 } 591 592 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 593 { 594 u32 tfms, xlvl; 595 u32 ebx; 596 597 /* Intel-defined flags: level 0x00000001 */ 598 if (c->cpuid_level >= 0x00000001) { 599 u32 capability, excap; 600 601 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 602 c->x86_capability[0] = capability; 603 c->x86_capability[4] = excap; 604 } 605 606 /* Additional Intel-defined flags: level 0x00000007 */ 607 if (c->cpuid_level >= 0x00000007) { 608 u32 eax, ebx, ecx, edx; 609 610 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 611 612 c->x86_capability[9] = ebx; 613 } 614 615 /* AMD-defined flags: level 0x80000001 */ 616 xlvl = cpuid_eax(0x80000000); 617 c->extended_cpuid_level = xlvl; 618 619 if ((xlvl & 0xffff0000) == 0x80000000) { 620 if (xlvl >= 0x80000001) { 621 c->x86_capability[1] = cpuid_edx(0x80000001); 622 c->x86_capability[6] = cpuid_ecx(0x80000001); 623 } 624 } 625 626 if (c->extended_cpuid_level >= 0x80000008) { 627 u32 eax = cpuid_eax(0x80000008); 628 629 c->x86_virt_bits = (eax >> 8) & 0xff; 630 c->x86_phys_bits = eax & 0xff; 631 } 632 #ifdef CONFIG_X86_32 633 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 634 c->x86_phys_bits = 36; 635 #endif 636 637 if (c->extended_cpuid_level >= 0x80000007) 638 c->x86_power = cpuid_edx(0x80000007); 639 640 init_scattered_cpuid_features(c); 641 } 642 643 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 644 { 645 #ifdef CONFIG_X86_32 646 int i; 647 648 /* 649 * First of all, decide if this is a 486 or higher 650 * It's a 486 if we can modify the AC flag 651 */ 652 if (flag_is_changeable_p(X86_EFLAGS_AC)) 653 c->x86 = 4; 654 else 655 c->x86 = 3; 656 657 for (i = 0; i < X86_VENDOR_NUM; i++) 658 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 659 c->x86_vendor_id[0] = 0; 660 cpu_devs[i]->c_identify(c); 661 if (c->x86_vendor_id[0]) { 662 get_cpu_vendor(c); 663 break; 664 } 665 } 666 #endif 667 } 668 669 /* 670 * Do minimum CPU detection early. 671 * Fields really needed: vendor, cpuid_level, family, model, mask, 672 * cache alignment. 673 * The others are not touched to avoid unwanted side effects. 674 * 675 * WARNING: this function is only called on the BP. Don't add code here 676 * that is supposed to run on all CPUs. 677 */ 678 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 679 { 680 #ifdef CONFIG_X86_64 681 c->x86_clflush_size = 64; 682 c->x86_phys_bits = 36; 683 c->x86_virt_bits = 48; 684 #else 685 c->x86_clflush_size = 32; 686 c->x86_phys_bits = 32; 687 c->x86_virt_bits = 32; 688 #endif 689 c->x86_cache_alignment = c->x86_clflush_size; 690 691 memset(&c->x86_capability, 0, sizeof c->x86_capability); 692 c->extended_cpuid_level = 0; 693 694 if (!have_cpuid_p()) 695 identify_cpu_without_cpuid(c); 696 697 /* cyrix could have cpuid enabled via c_identify()*/ 698 if (!have_cpuid_p()) 699 return; 700 701 cpu_detect(c); 702 703 get_cpu_vendor(c); 704 705 get_cpu_cap(c); 706 707 if (this_cpu->c_early_init) 708 this_cpu->c_early_init(c); 709 710 c->cpu_index = 0; 711 filter_cpuid_features(c, false); 712 713 setup_smep(c); 714 715 if (this_cpu->c_bsp_init) 716 this_cpu->c_bsp_init(c); 717 } 718 719 void __init early_cpu_init(void) 720 { 721 const struct cpu_dev *const *cdev; 722 int count = 0; 723 724 #ifdef CONFIG_PROCESSOR_SELECT 725 printk(KERN_INFO "KERNEL supported cpus:\n"); 726 #endif 727 728 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 729 const struct cpu_dev *cpudev = *cdev; 730 731 if (count >= X86_VENDOR_NUM) 732 break; 733 cpu_devs[count] = cpudev; 734 count++; 735 736 #ifdef CONFIG_PROCESSOR_SELECT 737 { 738 unsigned int j; 739 740 for (j = 0; j < 2; j++) { 741 if (!cpudev->c_ident[j]) 742 continue; 743 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 744 cpudev->c_ident[j]); 745 } 746 } 747 #endif 748 } 749 early_identify_cpu(&boot_cpu_data); 750 } 751 752 /* 753 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 754 * unfortunately, that's not true in practice because of early VIA 755 * chips and (more importantly) broken virtualizers that are not easy 756 * to detect. In the latter case it doesn't even *fail* reliably, so 757 * probing for it doesn't even work. Disable it completely on 32-bit 758 * unless we can find a reliable way to detect all the broken cases. 759 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 760 */ 761 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 762 { 763 #ifdef CONFIG_X86_32 764 clear_cpu_cap(c, X86_FEATURE_NOPL); 765 #else 766 set_cpu_cap(c, X86_FEATURE_NOPL); 767 #endif 768 } 769 770 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 771 { 772 c->extended_cpuid_level = 0; 773 774 if (!have_cpuid_p()) 775 identify_cpu_without_cpuid(c); 776 777 /* cyrix could have cpuid enabled via c_identify()*/ 778 if (!have_cpuid_p()) 779 return; 780 781 cpu_detect(c); 782 783 get_cpu_vendor(c); 784 785 get_cpu_cap(c); 786 787 if (c->cpuid_level >= 0x00000001) { 788 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 789 #ifdef CONFIG_X86_32 790 # ifdef CONFIG_X86_HT 791 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 792 # else 793 c->apicid = c->initial_apicid; 794 # endif 795 #endif 796 c->phys_proc_id = c->initial_apicid; 797 } 798 799 setup_smep(c); 800 801 get_model_name(c); /* Default name */ 802 803 detect_nopl(c); 804 } 805 806 /* 807 * This does the hard work of actually picking apart the CPU stuff... 808 */ 809 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 810 { 811 int i; 812 813 c->loops_per_jiffy = loops_per_jiffy; 814 c->x86_cache_size = -1; 815 c->x86_vendor = X86_VENDOR_UNKNOWN; 816 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 817 c->x86_vendor_id[0] = '\0'; /* Unset */ 818 c->x86_model_id[0] = '\0'; /* Unset */ 819 c->x86_max_cores = 1; 820 c->x86_coreid_bits = 0; 821 #ifdef CONFIG_X86_64 822 c->x86_clflush_size = 64; 823 c->x86_phys_bits = 36; 824 c->x86_virt_bits = 48; 825 #else 826 c->cpuid_level = -1; /* CPUID not detected */ 827 c->x86_clflush_size = 32; 828 c->x86_phys_bits = 32; 829 c->x86_virt_bits = 32; 830 #endif 831 c->x86_cache_alignment = c->x86_clflush_size; 832 memset(&c->x86_capability, 0, sizeof c->x86_capability); 833 834 generic_identify(c); 835 836 if (this_cpu->c_identify) 837 this_cpu->c_identify(c); 838 839 /* Clear/Set all flags overriden by options, after probe */ 840 for (i = 0; i < NCAPINTS; i++) { 841 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 842 c->x86_capability[i] |= cpu_caps_set[i]; 843 } 844 845 #ifdef CONFIG_X86_64 846 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 847 #endif 848 849 /* 850 * Vendor-specific initialization. In this section we 851 * canonicalize the feature flags, meaning if there are 852 * features a certain CPU supports which CPUID doesn't 853 * tell us, CPUID claiming incorrect flags, or other bugs, 854 * we handle them here. 855 * 856 * At the end of this section, c->x86_capability better 857 * indicate the features this CPU genuinely supports! 858 */ 859 if (this_cpu->c_init) 860 this_cpu->c_init(c); 861 862 /* Disable the PN if appropriate */ 863 squash_the_stupid_serial_number(c); 864 865 /* 866 * The vendor-specific functions might have changed features. 867 * Now we do "generic changes." 868 */ 869 870 /* Filter out anything that depends on CPUID levels we don't have */ 871 filter_cpuid_features(c, true); 872 873 /* If the model name is still unset, do table lookup. */ 874 if (!c->x86_model_id[0]) { 875 const char *p; 876 p = table_lookup_model(c); 877 if (p) 878 strcpy(c->x86_model_id, p); 879 else 880 /* Last resort... */ 881 sprintf(c->x86_model_id, "%02x/%02x", 882 c->x86, c->x86_model); 883 } 884 885 #ifdef CONFIG_X86_64 886 detect_ht(c); 887 #endif 888 889 init_hypervisor(c); 890 x86_init_rdrand(c); 891 892 /* 893 * Clear/Set all flags overriden by options, need do it 894 * before following smp all cpus cap AND. 895 */ 896 for (i = 0; i < NCAPINTS; i++) { 897 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 898 c->x86_capability[i] |= cpu_caps_set[i]; 899 } 900 901 /* 902 * On SMP, boot_cpu_data holds the common feature set between 903 * all CPUs; so make sure that we indicate which features are 904 * common between the CPUs. The first time this routine gets 905 * executed, c == &boot_cpu_data. 906 */ 907 if (c != &boot_cpu_data) { 908 /* AND the already accumulated flags with these */ 909 for (i = 0; i < NCAPINTS; i++) 910 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 911 } 912 913 /* Init Machine Check Exception if available. */ 914 mcheck_cpu_init(c); 915 916 select_idle_routine(c); 917 918 #ifdef CONFIG_NUMA 919 numa_add_cpu(smp_processor_id()); 920 #endif 921 } 922 923 #ifdef CONFIG_X86_64 924 static void vgetcpu_set_mode(void) 925 { 926 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 927 vgetcpu_mode = VGETCPU_RDTSCP; 928 else 929 vgetcpu_mode = VGETCPU_LSL; 930 } 931 #endif 932 933 void __init identify_boot_cpu(void) 934 { 935 identify_cpu(&boot_cpu_data); 936 init_amd_e400_c1e_mask(); 937 #ifdef CONFIG_X86_32 938 sysenter_setup(); 939 enable_sep_cpu(); 940 #else 941 vgetcpu_set_mode(); 942 #endif 943 if (boot_cpu_data.cpuid_level >= 2) 944 cpu_detect_tlb(&boot_cpu_data); 945 } 946 947 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 948 { 949 BUG_ON(c == &boot_cpu_data); 950 identify_cpu(c); 951 #ifdef CONFIG_X86_32 952 enable_sep_cpu(); 953 #endif 954 mtrr_ap_init(); 955 } 956 957 struct msr_range { 958 unsigned min; 959 unsigned max; 960 }; 961 962 static const struct msr_range msr_range_array[] __cpuinitconst = { 963 { 0x00000000, 0x00000418}, 964 { 0xc0000000, 0xc000040b}, 965 { 0xc0010000, 0xc0010142}, 966 { 0xc0011000, 0xc001103b}, 967 }; 968 969 static void __cpuinit __print_cpu_msr(void) 970 { 971 unsigned index_min, index_max; 972 unsigned index; 973 u64 val; 974 int i; 975 976 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 977 index_min = msr_range_array[i].min; 978 index_max = msr_range_array[i].max; 979 980 for (index = index_min; index < index_max; index++) { 981 if (rdmsrl_safe(index, &val)) 982 continue; 983 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 984 } 985 } 986 } 987 988 static int show_msr __cpuinitdata; 989 990 static __init int setup_show_msr(char *arg) 991 { 992 int num; 993 994 get_option(&arg, &num); 995 996 if (num > 0) 997 show_msr = num; 998 return 1; 999 } 1000 __setup("show_msr=", setup_show_msr); 1001 1002 static __init int setup_noclflush(char *arg) 1003 { 1004 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 1005 return 1; 1006 } 1007 __setup("noclflush", setup_noclflush); 1008 1009 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 1010 { 1011 const char *vendor = NULL; 1012 1013 if (c->x86_vendor < X86_VENDOR_NUM) { 1014 vendor = this_cpu->c_vendor; 1015 } else { 1016 if (c->cpuid_level >= 0) 1017 vendor = c->x86_vendor_id; 1018 } 1019 1020 if (vendor && !strstr(c->x86_model_id, vendor)) 1021 printk(KERN_CONT "%s ", vendor); 1022 1023 if (c->x86_model_id[0]) 1024 printk(KERN_CONT "%s", c->x86_model_id); 1025 else 1026 printk(KERN_CONT "%d86", c->x86); 1027 1028 if (c->x86_mask || c->cpuid_level >= 0) 1029 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 1030 else 1031 printk(KERN_CONT "\n"); 1032 1033 print_cpu_msr(c); 1034 } 1035 1036 void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c) 1037 { 1038 if (c->cpu_index < show_msr) 1039 __print_cpu_msr(); 1040 } 1041 1042 static __init int setup_disablecpuid(char *arg) 1043 { 1044 int bit; 1045 1046 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1047 setup_clear_cpu_cap(bit); 1048 else 1049 return 0; 1050 1051 return 1; 1052 } 1053 __setup("clearcpuid=", setup_disablecpuid); 1054 1055 #ifdef CONFIG_X86_64 1056 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1057 struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1, 1058 (unsigned long) nmi_idt_table }; 1059 1060 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1061 irq_stack_union) __aligned(PAGE_SIZE); 1062 1063 /* 1064 * The following four percpu variables are hot. Align current_task to 1065 * cacheline size such that all four fall in the same cacheline. 1066 */ 1067 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1068 &init_task; 1069 EXPORT_PER_CPU_SYMBOL(current_task); 1070 1071 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1072 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1073 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1074 1075 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1076 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1077 1078 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 1079 1080 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1081 1082 /* 1083 * Special IST stacks which the CPU switches to when it calls 1084 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1085 * limit), all of them are 4K, except the debug stack which 1086 * is 8K. 1087 */ 1088 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1089 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1090 [DEBUG_STACK - 1] = DEBUG_STKSZ 1091 }; 1092 1093 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1094 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1095 1096 /* May not be marked __init: used by software suspend */ 1097 void syscall_init(void) 1098 { 1099 /* 1100 * LSTAR and STAR live in a bit strange symbiosis. 1101 * They both write to the same internal register. STAR allows to 1102 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1103 */ 1104 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1105 wrmsrl(MSR_LSTAR, system_call); 1106 wrmsrl(MSR_CSTAR, ignore_sysret); 1107 1108 #ifdef CONFIG_IA32_EMULATION 1109 syscall32_cpu_init(); 1110 #endif 1111 1112 /* Flags to clear on syscall */ 1113 wrmsrl(MSR_SYSCALL_MASK, 1114 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 1115 } 1116 1117 unsigned long kernel_eflags; 1118 1119 /* 1120 * Copies of the original ist values from the tss are only accessed during 1121 * debugging, no special alignment required. 1122 */ 1123 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1124 1125 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1126 DEFINE_PER_CPU(int, debug_stack_usage); 1127 1128 int is_debug_stack(unsigned long addr) 1129 { 1130 return __get_cpu_var(debug_stack_usage) || 1131 (addr <= __get_cpu_var(debug_stack_addr) && 1132 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); 1133 } 1134 1135 static DEFINE_PER_CPU(u32, debug_stack_use_ctr); 1136 1137 void debug_stack_set_zero(void) 1138 { 1139 this_cpu_inc(debug_stack_use_ctr); 1140 load_idt((const struct desc_ptr *)&nmi_idt_descr); 1141 } 1142 1143 void debug_stack_reset(void) 1144 { 1145 if (WARN_ON(!this_cpu_read(debug_stack_use_ctr))) 1146 return; 1147 if (this_cpu_dec_return(debug_stack_use_ctr) == 0) 1148 load_idt((const struct desc_ptr *)&idt_descr); 1149 } 1150 1151 #else /* CONFIG_X86_64 */ 1152 1153 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1154 EXPORT_PER_CPU_SYMBOL(current_task); 1155 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1156 1157 #ifdef CONFIG_CC_STACKPROTECTOR 1158 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1159 #endif 1160 1161 /* Make sure %fs and %gs are initialized properly in idle threads */ 1162 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 1163 { 1164 memset(regs, 0, sizeof(struct pt_regs)); 1165 regs->fs = __KERNEL_PERCPU; 1166 regs->gs = __KERNEL_STACK_CANARY; 1167 1168 return regs; 1169 } 1170 #endif /* CONFIG_X86_64 */ 1171 1172 /* 1173 * Clear all 6 debug registers: 1174 */ 1175 static void clear_all_debug_regs(void) 1176 { 1177 int i; 1178 1179 for (i = 0; i < 8; i++) { 1180 /* Ignore db4, db5 */ 1181 if ((i == 4) || (i == 5)) 1182 continue; 1183 1184 set_debugreg(0, i); 1185 } 1186 } 1187 1188 #ifdef CONFIG_KGDB 1189 /* 1190 * Restore debug regs if using kgdbwait and you have a kernel debugger 1191 * connection established. 1192 */ 1193 static void dbg_restore_debug_regs(void) 1194 { 1195 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1196 arch_kgdb_ops.correct_hw_break(); 1197 } 1198 #else /* ! CONFIG_KGDB */ 1199 #define dbg_restore_debug_regs() 1200 #endif /* ! CONFIG_KGDB */ 1201 1202 /* 1203 * cpu_init() initializes state that is per-CPU. Some data is already 1204 * initialized (naturally) in the bootstrap process, such as the GDT 1205 * and IDT. We reload them nevertheless, this function acts as a 1206 * 'CPU state barrier', nothing should get across. 1207 * A lot of state is already set up in PDA init for 64 bit 1208 */ 1209 #ifdef CONFIG_X86_64 1210 1211 void __cpuinit cpu_init(void) 1212 { 1213 struct orig_ist *oist; 1214 struct task_struct *me; 1215 struct tss_struct *t; 1216 unsigned long v; 1217 int cpu; 1218 int i; 1219 1220 cpu = stack_smp_processor_id(); 1221 t = &per_cpu(init_tss, cpu); 1222 oist = &per_cpu(orig_ist, cpu); 1223 1224 #ifdef CONFIG_NUMA 1225 if (cpu != 0 && this_cpu_read(numa_node) == 0 && 1226 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1227 set_numa_node(early_cpu_to_node(cpu)); 1228 #endif 1229 1230 me = current; 1231 1232 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1233 panic("CPU#%d already initialized!\n", cpu); 1234 1235 pr_debug("Initializing CPU#%d\n", cpu); 1236 1237 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1238 1239 /* 1240 * Initialize the per-CPU GDT with the boot GDT, 1241 * and set up the GDT descriptor: 1242 */ 1243 1244 switch_to_new_gdt(cpu); 1245 loadsegment(fs, 0); 1246 1247 load_idt((const struct desc_ptr *)&idt_descr); 1248 1249 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1250 syscall_init(); 1251 1252 wrmsrl(MSR_FS_BASE, 0); 1253 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1254 barrier(); 1255 1256 x86_configure_nx(); 1257 if (cpu != 0) 1258 enable_x2apic(); 1259 1260 /* 1261 * set up and load the per-CPU TSS 1262 */ 1263 if (!oist->ist[0]) { 1264 char *estacks = per_cpu(exception_stacks, cpu); 1265 1266 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1267 estacks += exception_stack_sizes[v]; 1268 oist->ist[v] = t->x86_tss.ist[v] = 1269 (unsigned long)estacks; 1270 if (v == DEBUG_STACK-1) 1271 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1272 } 1273 } 1274 1275 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1276 1277 /* 1278 * <= is required because the CPU will access up to 1279 * 8 bits beyond the end of the IO permission bitmap. 1280 */ 1281 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1282 t->io_bitmap[i] = ~0UL; 1283 1284 atomic_inc(&init_mm.mm_count); 1285 me->active_mm = &init_mm; 1286 BUG_ON(me->mm); 1287 enter_lazy_tlb(&init_mm, me); 1288 1289 load_sp0(t, ¤t->thread); 1290 set_tss_desc(cpu, t); 1291 load_TR_desc(); 1292 load_LDT(&init_mm.context); 1293 1294 clear_all_debug_regs(); 1295 dbg_restore_debug_regs(); 1296 1297 fpu_init(); 1298 xsave_init(); 1299 1300 raw_local_save_flags(kernel_eflags); 1301 1302 if (is_uv_system()) 1303 uv_cpu_init(); 1304 } 1305 1306 #else 1307 1308 void __cpuinit cpu_init(void) 1309 { 1310 int cpu = smp_processor_id(); 1311 struct task_struct *curr = current; 1312 struct tss_struct *t = &per_cpu(init_tss, cpu); 1313 struct thread_struct *thread = &curr->thread; 1314 1315 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1316 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1317 for (;;) 1318 local_irq_enable(); 1319 } 1320 1321 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1322 1323 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1324 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1325 1326 load_idt(&idt_descr); 1327 switch_to_new_gdt(cpu); 1328 1329 /* 1330 * Set up and load the per-CPU TSS and LDT 1331 */ 1332 atomic_inc(&init_mm.mm_count); 1333 curr->active_mm = &init_mm; 1334 BUG_ON(curr->mm); 1335 enter_lazy_tlb(&init_mm, curr); 1336 1337 load_sp0(t, thread); 1338 set_tss_desc(cpu, t); 1339 load_TR_desc(); 1340 load_LDT(&init_mm.context); 1341 1342 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1343 1344 #ifdef CONFIG_DOUBLEFAULT 1345 /* Set up doublefault TSS pointer in the GDT */ 1346 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1347 #endif 1348 1349 clear_all_debug_regs(); 1350 dbg_restore_debug_regs(); 1351 1352 fpu_init(); 1353 xsave_init(); 1354 } 1355 #endif 1356