1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 25 #include <asm/stackprotector.h> 26 #include <asm/perf_event.h> 27 #include <asm/mmu_context.h> 28 #include <asm/doublefault.h> 29 #include <asm/archrandom.h> 30 #include <asm/hypervisor.h> 31 #include <asm/processor.h> 32 #include <asm/tlbflush.h> 33 #include <asm/debugreg.h> 34 #include <asm/sections.h> 35 #include <asm/vsyscall.h> 36 #include <linux/topology.h> 37 #include <linux/cpumask.h> 38 #include <asm/pgtable.h> 39 #include <linux/atomic.h> 40 #include <asm/proto.h> 41 #include <asm/setup.h> 42 #include <asm/apic.h> 43 #include <asm/desc.h> 44 #include <asm/fpu/internal.h> 45 #include <asm/mtrr.h> 46 #include <asm/hwcap2.h> 47 #include <linux/numa.h> 48 #include <asm/asm.h> 49 #include <asm/bugs.h> 50 #include <asm/cpu.h> 51 #include <asm/mce.h> 52 #include <asm/msr.h> 53 #include <asm/memtype.h> 54 #include <asm/microcode.h> 55 #include <asm/microcode_intel.h> 56 #include <asm/intel-family.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/uv/uv.h> 59 60 #include "cpu.h" 61 62 u32 elf_hwcap2 __read_mostly; 63 64 /* all of these masks are initialized in setup_cpu_local_masks() */ 65 cpumask_var_t cpu_initialized_mask; 66 cpumask_var_t cpu_callout_mask; 67 cpumask_var_t cpu_callin_mask; 68 69 /* representing cpus for which sibling maps can be computed */ 70 cpumask_var_t cpu_sibling_setup_mask; 71 72 /* Number of siblings per CPU package */ 73 int smp_num_siblings = 1; 74 EXPORT_SYMBOL(smp_num_siblings); 75 76 /* Last level cache ID of each logical CPU */ 77 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 78 79 /* correctly size the local cpu masks */ 80 void __init setup_cpu_local_masks(void) 81 { 82 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 83 alloc_bootmem_cpumask_var(&cpu_callin_mask); 84 alloc_bootmem_cpumask_var(&cpu_callout_mask); 85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 86 } 87 88 static void default_init(struct cpuinfo_x86 *c) 89 { 90 #ifdef CONFIG_X86_64 91 cpu_detect_cache_sizes(c); 92 #else 93 /* Not much we can do here... */ 94 /* Check if at least it has cpuid */ 95 if (c->cpuid_level == -1) { 96 /* No cpuid. It must be an ancient CPU */ 97 if (c->x86 == 4) 98 strcpy(c->x86_model_id, "486"); 99 else if (c->x86 == 3) 100 strcpy(c->x86_model_id, "386"); 101 } 102 #endif 103 } 104 105 static const struct cpu_dev default_cpu = { 106 .c_init = default_init, 107 .c_vendor = "Unknown", 108 .c_x86_vendor = X86_VENDOR_UNKNOWN, 109 }; 110 111 static const struct cpu_dev *this_cpu = &default_cpu; 112 113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 114 #ifdef CONFIG_X86_64 115 /* 116 * We need valid kernel segments for data and code in long mode too 117 * IRET will check the segment types kkeil 2000/10/28 118 * Also sysret mandates a special GDT layout 119 * 120 * TLS descriptors are currently at a different place compared to i386. 121 * Hopefully nobody expects them at a fixed place (Wine?) 122 */ 123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 129 #else 130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 134 /* 135 * Segments used for calling PnP BIOS have byte granularity. 136 * They code segments and data segments have fixed 64k limits, 137 * the transfer segment sizes are set at run time. 138 */ 139 /* 32-bit code */ 140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 141 /* 16-bit code */ 142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 143 /* 16-bit data */ 144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 145 /* 16-bit data */ 146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 147 /* 16-bit data */ 148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 149 /* 150 * The APM segments have byte granularity and their bases 151 * are set at run time. All have 64k limits. 152 */ 153 /* 32-bit code */ 154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 155 /* 16-bit code */ 156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 157 /* data */ 158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 159 160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 162 GDT_STACK_CANARY_INIT 163 #endif 164 } }; 165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 166 167 static int __init x86_mpx_setup(char *s) 168 { 169 /* require an exact match without trailing characters */ 170 if (strlen(s)) 171 return 0; 172 173 /* do not emit a message if the feature is not present */ 174 if (!boot_cpu_has(X86_FEATURE_MPX)) 175 return 1; 176 177 setup_clear_cpu_cap(X86_FEATURE_MPX); 178 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 179 return 1; 180 } 181 __setup("nompx", x86_mpx_setup); 182 183 #ifdef CONFIG_X86_64 184 static int __init x86_nopcid_setup(char *s) 185 { 186 /* nopcid doesn't accept parameters */ 187 if (s) 188 return -EINVAL; 189 190 /* do not emit a message if the feature is not present */ 191 if (!boot_cpu_has(X86_FEATURE_PCID)) 192 return 0; 193 194 setup_clear_cpu_cap(X86_FEATURE_PCID); 195 pr_info("nopcid: PCID feature disabled\n"); 196 return 0; 197 } 198 early_param("nopcid", x86_nopcid_setup); 199 #endif 200 201 static int __init x86_noinvpcid_setup(char *s) 202 { 203 /* noinvpcid doesn't accept parameters */ 204 if (s) 205 return -EINVAL; 206 207 /* do not emit a message if the feature is not present */ 208 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 209 return 0; 210 211 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 212 pr_info("noinvpcid: INVPCID feature disabled\n"); 213 return 0; 214 } 215 early_param("noinvpcid", x86_noinvpcid_setup); 216 217 #ifdef CONFIG_X86_32 218 static int cachesize_override = -1; 219 static int disable_x86_serial_nr = 1; 220 221 static int __init cachesize_setup(char *str) 222 { 223 get_option(&str, &cachesize_override); 224 return 1; 225 } 226 __setup("cachesize=", cachesize_setup); 227 228 static int __init x86_sep_setup(char *s) 229 { 230 setup_clear_cpu_cap(X86_FEATURE_SEP); 231 return 1; 232 } 233 __setup("nosep", x86_sep_setup); 234 235 /* Standard macro to see if a specific flag is changeable */ 236 static inline int flag_is_changeable_p(u32 flag) 237 { 238 u32 f1, f2; 239 240 /* 241 * Cyrix and IDT cpus allow disabling of CPUID 242 * so the code below may return different results 243 * when it is executed before and after enabling 244 * the CPUID. Add "volatile" to not allow gcc to 245 * optimize the subsequent calls to this function. 246 */ 247 asm volatile ("pushfl \n\t" 248 "pushfl \n\t" 249 "popl %0 \n\t" 250 "movl %0, %1 \n\t" 251 "xorl %2, %0 \n\t" 252 "pushl %0 \n\t" 253 "popfl \n\t" 254 "pushfl \n\t" 255 "popl %0 \n\t" 256 "popfl \n\t" 257 258 : "=&r" (f1), "=&r" (f2) 259 : "ir" (flag)); 260 261 return ((f1^f2) & flag) != 0; 262 } 263 264 /* Probe for the CPUID instruction */ 265 int have_cpuid_p(void) 266 { 267 return flag_is_changeable_p(X86_EFLAGS_ID); 268 } 269 270 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 271 { 272 unsigned long lo, hi; 273 274 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 275 return; 276 277 /* Disable processor serial number: */ 278 279 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 280 lo |= 0x200000; 281 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 282 283 pr_notice("CPU serial number disabled.\n"); 284 clear_cpu_cap(c, X86_FEATURE_PN); 285 286 /* Disabling the serial number may affect the cpuid level */ 287 c->cpuid_level = cpuid_eax(0); 288 } 289 290 static int __init x86_serial_nr_setup(char *s) 291 { 292 disable_x86_serial_nr = 0; 293 return 1; 294 } 295 __setup("serialnumber", x86_serial_nr_setup); 296 #else 297 static inline int flag_is_changeable_p(u32 flag) 298 { 299 return 1; 300 } 301 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 302 { 303 } 304 #endif 305 306 static __init int setup_disable_smep(char *arg) 307 { 308 setup_clear_cpu_cap(X86_FEATURE_SMEP); 309 /* Check for things that depend on SMEP being enabled: */ 310 check_mpx_erratum(&boot_cpu_data); 311 return 1; 312 } 313 __setup("nosmep", setup_disable_smep); 314 315 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 316 { 317 if (cpu_has(c, X86_FEATURE_SMEP)) 318 cr4_set_bits(X86_CR4_SMEP); 319 } 320 321 static __init int setup_disable_smap(char *arg) 322 { 323 setup_clear_cpu_cap(X86_FEATURE_SMAP); 324 return 1; 325 } 326 __setup("nosmap", setup_disable_smap); 327 328 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 329 { 330 unsigned long eflags = native_save_fl(); 331 332 /* This should have been cleared long ago */ 333 BUG_ON(eflags & X86_EFLAGS_AC); 334 335 if (cpu_has(c, X86_FEATURE_SMAP)) { 336 #ifdef CONFIG_X86_SMAP 337 cr4_set_bits(X86_CR4_SMAP); 338 #else 339 cr4_clear_bits(X86_CR4_SMAP); 340 #endif 341 } 342 } 343 344 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 345 { 346 /* Check the boot processor, plus build option for UMIP. */ 347 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 348 goto out; 349 350 /* Check the current processor's cpuid bits. */ 351 if (!cpu_has(c, X86_FEATURE_UMIP)) 352 goto out; 353 354 cr4_set_bits(X86_CR4_UMIP); 355 356 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 357 358 return; 359 360 out: 361 /* 362 * Make sure UMIP is disabled in case it was enabled in a 363 * previous boot (e.g., via kexec). 364 */ 365 cr4_clear_bits(X86_CR4_UMIP); 366 } 367 368 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 369 static unsigned long cr4_pinned_bits __ro_after_init; 370 371 void native_write_cr0(unsigned long val) 372 { 373 unsigned long bits_missing = 0; 374 375 set_register: 376 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); 377 378 if (static_branch_likely(&cr_pinning)) { 379 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 380 bits_missing = X86_CR0_WP; 381 val |= bits_missing; 382 goto set_register; 383 } 384 /* Warn after we've set the missing bits. */ 385 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 386 } 387 } 388 EXPORT_SYMBOL(native_write_cr0); 389 390 void native_write_cr4(unsigned long val) 391 { 392 unsigned long bits_missing = 0; 393 394 set_register: 395 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); 396 397 if (static_branch_likely(&cr_pinning)) { 398 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { 399 bits_missing = ~val & cr4_pinned_bits; 400 val |= bits_missing; 401 goto set_register; 402 } 403 /* Warn after we've set the missing bits. */ 404 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n", 405 bits_missing); 406 } 407 } 408 EXPORT_SYMBOL(native_write_cr4); 409 410 void cr4_init(void) 411 { 412 unsigned long cr4 = __read_cr4(); 413 414 if (boot_cpu_has(X86_FEATURE_PCID)) 415 cr4 |= X86_CR4_PCIDE; 416 if (static_branch_likely(&cr_pinning)) 417 cr4 |= cr4_pinned_bits; 418 419 __write_cr4(cr4); 420 421 /* Initialize cr4 shadow for this CPU. */ 422 this_cpu_write(cpu_tlbstate.cr4, cr4); 423 } 424 425 /* 426 * Once CPU feature detection is finished (and boot params have been 427 * parsed), record any of the sensitive CR bits that are set, and 428 * enable CR pinning. 429 */ 430 static void __init setup_cr_pinning(void) 431 { 432 unsigned long mask; 433 434 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); 435 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; 436 static_key_enable(&cr_pinning.key); 437 } 438 439 /* 440 * Protection Keys are not available in 32-bit mode. 441 */ 442 static bool pku_disabled; 443 444 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 445 { 446 struct pkru_state *pk; 447 448 /* check the boot processor, plus compile options for PKU: */ 449 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 450 return; 451 /* checks the actual processor's cpuid bits: */ 452 if (!cpu_has(c, X86_FEATURE_PKU)) 453 return; 454 if (pku_disabled) 455 return; 456 457 cr4_set_bits(X86_CR4_PKE); 458 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 459 if (pk) 460 pk->pkru = init_pkru_value; 461 /* 462 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 463 * cpuid bit to be set. We need to ensure that we 464 * update that bit in this CPU's "cpu_info". 465 */ 466 get_cpu_cap(c); 467 } 468 469 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 470 static __init int setup_disable_pku(char *arg) 471 { 472 /* 473 * Do not clear the X86_FEATURE_PKU bit. All of the 474 * runtime checks are against OSPKE so clearing the 475 * bit does nothing. 476 * 477 * This way, we will see "pku" in cpuinfo, but not 478 * "ospke", which is exactly what we want. It shows 479 * that the CPU has PKU, but the OS has not enabled it. 480 * This happens to be exactly how a system would look 481 * if we disabled the config option. 482 */ 483 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 484 pku_disabled = true; 485 return 1; 486 } 487 __setup("nopku", setup_disable_pku); 488 #endif /* CONFIG_X86_64 */ 489 490 /* 491 * Some CPU features depend on higher CPUID levels, which may not always 492 * be available due to CPUID level capping or broken virtualization 493 * software. Add those features to this table to auto-disable them. 494 */ 495 struct cpuid_dependent_feature { 496 u32 feature; 497 u32 level; 498 }; 499 500 static const struct cpuid_dependent_feature 501 cpuid_dependent_features[] = { 502 { X86_FEATURE_MWAIT, 0x00000005 }, 503 { X86_FEATURE_DCA, 0x00000009 }, 504 { X86_FEATURE_XSAVE, 0x0000000d }, 505 { 0, 0 } 506 }; 507 508 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 509 { 510 const struct cpuid_dependent_feature *df; 511 512 for (df = cpuid_dependent_features; df->feature; df++) { 513 514 if (!cpu_has(c, df->feature)) 515 continue; 516 /* 517 * Note: cpuid_level is set to -1 if unavailable, but 518 * extended_extended_level is set to 0 if unavailable 519 * and the legitimate extended levels are all negative 520 * when signed; hence the weird messing around with 521 * signs here... 522 */ 523 if (!((s32)df->level < 0 ? 524 (u32)df->level > (u32)c->extended_cpuid_level : 525 (s32)df->level > (s32)c->cpuid_level)) 526 continue; 527 528 clear_cpu_cap(c, df->feature); 529 if (!warn) 530 continue; 531 532 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 533 x86_cap_flag(df->feature), df->level); 534 } 535 } 536 537 /* 538 * Naming convention should be: <Name> [(<Codename>)] 539 * This table only is used unless init_<vendor>() below doesn't set it; 540 * in particular, if CPUID levels 0x80000002..4 are supported, this 541 * isn't used 542 */ 543 544 /* Look up CPU names by table lookup. */ 545 static const char *table_lookup_model(struct cpuinfo_x86 *c) 546 { 547 #ifdef CONFIG_X86_32 548 const struct legacy_cpu_model_info *info; 549 550 if (c->x86_model >= 16) 551 return NULL; /* Range check */ 552 553 if (!this_cpu) 554 return NULL; 555 556 info = this_cpu->legacy_models; 557 558 while (info->family) { 559 if (info->family == c->x86) 560 return info->model_names[c->x86_model]; 561 info++; 562 } 563 #endif 564 return NULL; /* Not found */ 565 } 566 567 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 568 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 569 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 570 571 void load_percpu_segment(int cpu) 572 { 573 #ifdef CONFIG_X86_32 574 loadsegment(fs, __KERNEL_PERCPU); 575 #else 576 __loadsegment_simple(gs, 0); 577 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 578 #endif 579 load_stack_canary_segment(); 580 } 581 582 #ifdef CONFIG_X86_32 583 /* The 32-bit entry code needs to find cpu_entry_area. */ 584 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 585 #endif 586 587 /* Load the original GDT from the per-cpu structure */ 588 void load_direct_gdt(int cpu) 589 { 590 struct desc_ptr gdt_descr; 591 592 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 593 gdt_descr.size = GDT_SIZE - 1; 594 load_gdt(&gdt_descr); 595 } 596 EXPORT_SYMBOL_GPL(load_direct_gdt); 597 598 /* Load a fixmap remapping of the per-cpu GDT */ 599 void load_fixmap_gdt(int cpu) 600 { 601 struct desc_ptr gdt_descr; 602 603 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 604 gdt_descr.size = GDT_SIZE - 1; 605 load_gdt(&gdt_descr); 606 } 607 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 608 609 /* 610 * Current gdt points %fs at the "master" per-cpu area: after this, 611 * it's on the real one. 612 */ 613 void switch_to_new_gdt(int cpu) 614 { 615 /* Load the original GDT */ 616 load_direct_gdt(cpu); 617 /* Reload the per-cpu base */ 618 load_percpu_segment(cpu); 619 } 620 621 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 622 623 static void get_model_name(struct cpuinfo_x86 *c) 624 { 625 unsigned int *v; 626 char *p, *q, *s; 627 628 if (c->extended_cpuid_level < 0x80000004) 629 return; 630 631 v = (unsigned int *)c->x86_model_id; 632 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 633 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 634 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 635 c->x86_model_id[48] = 0; 636 637 /* Trim whitespace */ 638 p = q = s = &c->x86_model_id[0]; 639 640 while (*p == ' ') 641 p++; 642 643 while (*p) { 644 /* Note the last non-whitespace index */ 645 if (!isspace(*p)) 646 s = q; 647 648 *q++ = *p++; 649 } 650 651 *(s + 1) = '\0'; 652 } 653 654 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 655 { 656 unsigned int eax, ebx, ecx, edx; 657 658 c->x86_max_cores = 1; 659 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 660 return; 661 662 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 663 if (eax & 0x1f) 664 c->x86_max_cores = (eax >> 26) + 1; 665 } 666 667 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 668 { 669 unsigned int n, dummy, ebx, ecx, edx, l2size; 670 671 n = c->extended_cpuid_level; 672 673 if (n >= 0x80000005) { 674 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 675 c->x86_cache_size = (ecx>>24) + (edx>>24); 676 #ifdef CONFIG_X86_64 677 /* On K8 L1 TLB is inclusive, so don't count it */ 678 c->x86_tlbsize = 0; 679 #endif 680 } 681 682 if (n < 0x80000006) /* Some chips just has a large L1. */ 683 return; 684 685 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 686 l2size = ecx >> 16; 687 688 #ifdef CONFIG_X86_64 689 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 690 #else 691 /* do processor-specific cache resizing */ 692 if (this_cpu->legacy_cache_size) 693 l2size = this_cpu->legacy_cache_size(c, l2size); 694 695 /* Allow user to override all this if necessary. */ 696 if (cachesize_override != -1) 697 l2size = cachesize_override; 698 699 if (l2size == 0) 700 return; /* Again, no L2 cache is possible */ 701 #endif 702 703 c->x86_cache_size = l2size; 704 } 705 706 u16 __read_mostly tlb_lli_4k[NR_INFO]; 707 u16 __read_mostly tlb_lli_2m[NR_INFO]; 708 u16 __read_mostly tlb_lli_4m[NR_INFO]; 709 u16 __read_mostly tlb_lld_4k[NR_INFO]; 710 u16 __read_mostly tlb_lld_2m[NR_INFO]; 711 u16 __read_mostly tlb_lld_4m[NR_INFO]; 712 u16 __read_mostly tlb_lld_1g[NR_INFO]; 713 714 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 715 { 716 if (this_cpu->c_detect_tlb) 717 this_cpu->c_detect_tlb(c); 718 719 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 720 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 721 tlb_lli_4m[ENTRIES]); 722 723 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 724 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 725 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 726 } 727 728 int detect_ht_early(struct cpuinfo_x86 *c) 729 { 730 #ifdef CONFIG_SMP 731 u32 eax, ebx, ecx, edx; 732 733 if (!cpu_has(c, X86_FEATURE_HT)) 734 return -1; 735 736 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 737 return -1; 738 739 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 740 return -1; 741 742 cpuid(1, &eax, &ebx, &ecx, &edx); 743 744 smp_num_siblings = (ebx & 0xff0000) >> 16; 745 if (smp_num_siblings == 1) 746 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 747 #endif 748 return 0; 749 } 750 751 void detect_ht(struct cpuinfo_x86 *c) 752 { 753 #ifdef CONFIG_SMP 754 int index_msb, core_bits; 755 756 if (detect_ht_early(c) < 0) 757 return; 758 759 index_msb = get_count_order(smp_num_siblings); 760 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 761 762 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 763 764 index_msb = get_count_order(smp_num_siblings); 765 766 core_bits = get_count_order(c->x86_max_cores); 767 768 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 769 ((1 << core_bits) - 1); 770 #endif 771 } 772 773 static void get_cpu_vendor(struct cpuinfo_x86 *c) 774 { 775 char *v = c->x86_vendor_id; 776 int i; 777 778 for (i = 0; i < X86_VENDOR_NUM; i++) { 779 if (!cpu_devs[i]) 780 break; 781 782 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 783 (cpu_devs[i]->c_ident[1] && 784 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 785 786 this_cpu = cpu_devs[i]; 787 c->x86_vendor = this_cpu->c_x86_vendor; 788 return; 789 } 790 } 791 792 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 793 "CPU: Your system may be unstable.\n", v); 794 795 c->x86_vendor = X86_VENDOR_UNKNOWN; 796 this_cpu = &default_cpu; 797 } 798 799 void cpu_detect(struct cpuinfo_x86 *c) 800 { 801 /* Get vendor name */ 802 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 803 (unsigned int *)&c->x86_vendor_id[0], 804 (unsigned int *)&c->x86_vendor_id[8], 805 (unsigned int *)&c->x86_vendor_id[4]); 806 807 c->x86 = 4; 808 /* Intel-defined flags: level 0x00000001 */ 809 if (c->cpuid_level >= 0x00000001) { 810 u32 junk, tfms, cap0, misc; 811 812 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 813 c->x86 = x86_family(tfms); 814 c->x86_model = x86_model(tfms); 815 c->x86_stepping = x86_stepping(tfms); 816 817 if (cap0 & (1<<19)) { 818 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 819 c->x86_cache_alignment = c->x86_clflush_size; 820 } 821 } 822 } 823 824 static void apply_forced_caps(struct cpuinfo_x86 *c) 825 { 826 int i; 827 828 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 829 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 830 c->x86_capability[i] |= cpu_caps_set[i]; 831 } 832 } 833 834 static void init_speculation_control(struct cpuinfo_x86 *c) 835 { 836 /* 837 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 838 * and they also have a different bit for STIBP support. Also, 839 * a hypervisor might have set the individual AMD bits even on 840 * Intel CPUs, for finer-grained selection of what's available. 841 */ 842 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 843 set_cpu_cap(c, X86_FEATURE_IBRS); 844 set_cpu_cap(c, X86_FEATURE_IBPB); 845 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 846 } 847 848 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 849 set_cpu_cap(c, X86_FEATURE_STIBP); 850 851 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 852 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 853 set_cpu_cap(c, X86_FEATURE_SSBD); 854 855 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 856 set_cpu_cap(c, X86_FEATURE_IBRS); 857 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 858 } 859 860 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 861 set_cpu_cap(c, X86_FEATURE_IBPB); 862 863 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 864 set_cpu_cap(c, X86_FEATURE_STIBP); 865 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 866 } 867 868 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 869 set_cpu_cap(c, X86_FEATURE_SSBD); 870 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 871 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 872 } 873 } 874 875 static void init_cqm(struct cpuinfo_x86 *c) 876 { 877 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 878 c->x86_cache_max_rmid = -1; 879 c->x86_cache_occ_scale = -1; 880 return; 881 } 882 883 /* will be overridden if occupancy monitoring exists */ 884 c->x86_cache_max_rmid = cpuid_ebx(0xf); 885 886 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 887 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 888 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 889 u32 eax, ebx, ecx, edx; 890 891 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 892 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 893 894 c->x86_cache_max_rmid = ecx; 895 c->x86_cache_occ_scale = ebx; 896 } 897 } 898 899 void get_cpu_cap(struct cpuinfo_x86 *c) 900 { 901 u32 eax, ebx, ecx, edx; 902 903 /* Intel-defined flags: level 0x00000001 */ 904 if (c->cpuid_level >= 0x00000001) { 905 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 906 907 c->x86_capability[CPUID_1_ECX] = ecx; 908 c->x86_capability[CPUID_1_EDX] = edx; 909 } 910 911 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 912 if (c->cpuid_level >= 0x00000006) 913 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 914 915 /* Additional Intel-defined flags: level 0x00000007 */ 916 if (c->cpuid_level >= 0x00000007) { 917 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 918 c->x86_capability[CPUID_7_0_EBX] = ebx; 919 c->x86_capability[CPUID_7_ECX] = ecx; 920 c->x86_capability[CPUID_7_EDX] = edx; 921 922 /* Check valid sub-leaf index before accessing it */ 923 if (eax >= 1) { 924 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 925 c->x86_capability[CPUID_7_1_EAX] = eax; 926 } 927 } 928 929 /* Extended state features: level 0x0000000d */ 930 if (c->cpuid_level >= 0x0000000d) { 931 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 932 933 c->x86_capability[CPUID_D_1_EAX] = eax; 934 } 935 936 /* AMD-defined flags: level 0x80000001 */ 937 eax = cpuid_eax(0x80000000); 938 c->extended_cpuid_level = eax; 939 940 if ((eax & 0xffff0000) == 0x80000000) { 941 if (eax >= 0x80000001) { 942 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 943 944 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 945 c->x86_capability[CPUID_8000_0001_EDX] = edx; 946 } 947 } 948 949 if (c->extended_cpuid_level >= 0x80000007) { 950 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 951 952 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 953 c->x86_power = edx; 954 } 955 956 if (c->extended_cpuid_level >= 0x80000008) { 957 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 958 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 959 } 960 961 if (c->extended_cpuid_level >= 0x8000000a) 962 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 963 964 init_scattered_cpuid_features(c); 965 init_speculation_control(c); 966 init_cqm(c); 967 968 /* 969 * Clear/Set all flags overridden by options, after probe. 970 * This needs to happen each time we re-probe, which may happen 971 * several times during CPU initialization. 972 */ 973 apply_forced_caps(c); 974 } 975 976 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 977 { 978 u32 eax, ebx, ecx, edx; 979 980 if (c->extended_cpuid_level >= 0x80000008) { 981 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 982 983 c->x86_virt_bits = (eax >> 8) & 0xff; 984 c->x86_phys_bits = eax & 0xff; 985 } 986 #ifdef CONFIG_X86_32 987 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 988 c->x86_phys_bits = 36; 989 #endif 990 c->x86_cache_bits = c->x86_phys_bits; 991 } 992 993 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 994 { 995 #ifdef CONFIG_X86_32 996 int i; 997 998 /* 999 * First of all, decide if this is a 486 or higher 1000 * It's a 486 if we can modify the AC flag 1001 */ 1002 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1003 c->x86 = 4; 1004 else 1005 c->x86 = 3; 1006 1007 for (i = 0; i < X86_VENDOR_NUM; i++) 1008 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1009 c->x86_vendor_id[0] = 0; 1010 cpu_devs[i]->c_identify(c); 1011 if (c->x86_vendor_id[0]) { 1012 get_cpu_vendor(c); 1013 break; 1014 } 1015 } 1016 #endif 1017 } 1018 1019 #define NO_SPECULATION BIT(0) 1020 #define NO_MELTDOWN BIT(1) 1021 #define NO_SSB BIT(2) 1022 #define NO_L1TF BIT(3) 1023 #define NO_MDS BIT(4) 1024 #define MSBDS_ONLY BIT(5) 1025 #define NO_SWAPGS BIT(6) 1026 #define NO_ITLB_MULTIHIT BIT(7) 1027 #define NO_SPECTRE_V2 BIT(8) 1028 1029 #define VULNWL(_vendor, _family, _model, _whitelist) \ 1030 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } 1031 1032 #define VULNWL_INTEL(model, whitelist) \ 1033 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1034 1035 #define VULNWL_AMD(family, whitelist) \ 1036 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1037 1038 #define VULNWL_HYGON(family, whitelist) \ 1039 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1040 1041 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1042 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1043 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1044 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1045 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1046 1047 /* Intel Family 6 */ 1048 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1049 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1050 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1051 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1052 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1053 1054 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1055 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1056 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1057 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1058 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1059 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1060 1061 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1062 1063 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1064 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1065 1066 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1067 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1068 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1069 1070 /* 1071 * Technically, swapgs isn't serializing on AMD (despite it previously 1072 * being documented as such in the APM). But according to AMD, %gs is 1073 * updated non-speculatively, and the issuing of %gs-relative memory 1074 * operands will be blocked until the %gs update completes, which is 1075 * good enough for our purposes. 1076 */ 1077 1078 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1079 1080 /* AMD Family 0xf - 0x12 */ 1081 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1082 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1083 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1084 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1085 1086 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1087 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1088 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1089 1090 /* Zhaoxin Family 7 */ 1091 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1092 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), 1093 {} 1094 }; 1095 1096 static bool __init cpu_matches(unsigned long which) 1097 { 1098 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 1099 1100 return m && !!(m->driver_data & which); 1101 } 1102 1103 u64 x86_read_arch_cap_msr(void) 1104 { 1105 u64 ia32_cap = 0; 1106 1107 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1108 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1109 1110 return ia32_cap; 1111 } 1112 1113 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1114 { 1115 u64 ia32_cap = x86_read_arch_cap_msr(); 1116 1117 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1118 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1119 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1120 1121 if (cpu_matches(NO_SPECULATION)) 1122 return; 1123 1124 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1125 1126 if (!cpu_matches(NO_SPECTRE_V2)) 1127 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1128 1129 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 1130 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1131 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1132 1133 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1134 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1135 1136 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1137 setup_force_cpu_bug(X86_BUG_MDS); 1138 if (cpu_matches(MSBDS_ONLY)) 1139 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1140 } 1141 1142 if (!cpu_matches(NO_SWAPGS)) 1143 setup_force_cpu_bug(X86_BUG_SWAPGS); 1144 1145 /* 1146 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1147 * - TSX is supported or 1148 * - TSX_CTRL is present 1149 * 1150 * TSX_CTRL check is needed for cases when TSX could be disabled before 1151 * the kernel boot e.g. kexec. 1152 * TSX_CTRL check alone is not sufficient for cases when the microcode 1153 * update is not present or running as guest that don't get TSX_CTRL. 1154 */ 1155 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1156 (cpu_has(c, X86_FEATURE_RTM) || 1157 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1158 setup_force_cpu_bug(X86_BUG_TAA); 1159 1160 if (cpu_matches(NO_MELTDOWN)) 1161 return; 1162 1163 /* Rogue Data Cache Load? No! */ 1164 if (ia32_cap & ARCH_CAP_RDCL_NO) 1165 return; 1166 1167 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1168 1169 if (cpu_matches(NO_L1TF)) 1170 return; 1171 1172 setup_force_cpu_bug(X86_BUG_L1TF); 1173 } 1174 1175 /* 1176 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1177 * unfortunately, that's not true in practice because of early VIA 1178 * chips and (more importantly) broken virtualizers that are not easy 1179 * to detect. In the latter case it doesn't even *fail* reliably, so 1180 * probing for it doesn't even work. Disable it completely on 32-bit 1181 * unless we can find a reliable way to detect all the broken cases. 1182 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1183 */ 1184 static void detect_nopl(void) 1185 { 1186 #ifdef CONFIG_X86_32 1187 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1188 #else 1189 setup_force_cpu_cap(X86_FEATURE_NOPL); 1190 #endif 1191 } 1192 1193 /* 1194 * Do minimum CPU detection early. 1195 * Fields really needed: vendor, cpuid_level, family, model, mask, 1196 * cache alignment. 1197 * The others are not touched to avoid unwanted side effects. 1198 * 1199 * WARNING: this function is only called on the boot CPU. Don't add code 1200 * here that is supposed to run on all CPUs. 1201 */ 1202 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1203 { 1204 #ifdef CONFIG_X86_64 1205 c->x86_clflush_size = 64; 1206 c->x86_phys_bits = 36; 1207 c->x86_virt_bits = 48; 1208 #else 1209 c->x86_clflush_size = 32; 1210 c->x86_phys_bits = 32; 1211 c->x86_virt_bits = 32; 1212 #endif 1213 c->x86_cache_alignment = c->x86_clflush_size; 1214 1215 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1216 c->extended_cpuid_level = 0; 1217 1218 if (!have_cpuid_p()) 1219 identify_cpu_without_cpuid(c); 1220 1221 /* cyrix could have cpuid enabled via c_identify()*/ 1222 if (have_cpuid_p()) { 1223 cpu_detect(c); 1224 get_cpu_vendor(c); 1225 get_cpu_cap(c); 1226 get_cpu_address_sizes(c); 1227 setup_force_cpu_cap(X86_FEATURE_CPUID); 1228 1229 if (this_cpu->c_early_init) 1230 this_cpu->c_early_init(c); 1231 1232 c->cpu_index = 0; 1233 filter_cpuid_features(c, false); 1234 1235 if (this_cpu->c_bsp_init) 1236 this_cpu->c_bsp_init(c); 1237 } else { 1238 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1239 } 1240 1241 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1242 1243 cpu_set_bug_bits(c); 1244 1245 fpu__init_system(c); 1246 1247 #ifdef CONFIG_X86_32 1248 /* 1249 * Regardless of whether PCID is enumerated, the SDM says 1250 * that it can't be enabled in 32-bit mode. 1251 */ 1252 setup_clear_cpu_cap(X86_FEATURE_PCID); 1253 #endif 1254 1255 /* 1256 * Later in the boot process pgtable_l5_enabled() relies on 1257 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1258 * enabled by this point we need to clear the feature bit to avoid 1259 * false-positives at the later stage. 1260 * 1261 * pgtable_l5_enabled() can be false here for several reasons: 1262 * - 5-level paging is disabled compile-time; 1263 * - it's 32-bit kernel; 1264 * - machine doesn't support 5-level paging; 1265 * - user specified 'no5lvl' in kernel command line. 1266 */ 1267 if (!pgtable_l5_enabled()) 1268 setup_clear_cpu_cap(X86_FEATURE_LA57); 1269 1270 detect_nopl(); 1271 } 1272 1273 void __init early_cpu_init(void) 1274 { 1275 const struct cpu_dev *const *cdev; 1276 int count = 0; 1277 1278 #ifdef CONFIG_PROCESSOR_SELECT 1279 pr_info("KERNEL supported cpus:\n"); 1280 #endif 1281 1282 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1283 const struct cpu_dev *cpudev = *cdev; 1284 1285 if (count >= X86_VENDOR_NUM) 1286 break; 1287 cpu_devs[count] = cpudev; 1288 count++; 1289 1290 #ifdef CONFIG_PROCESSOR_SELECT 1291 { 1292 unsigned int j; 1293 1294 for (j = 0; j < 2; j++) { 1295 if (!cpudev->c_ident[j]) 1296 continue; 1297 pr_info(" %s %s\n", cpudev->c_vendor, 1298 cpudev->c_ident[j]); 1299 } 1300 } 1301 #endif 1302 } 1303 early_identify_cpu(&boot_cpu_data); 1304 } 1305 1306 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1307 { 1308 #ifdef CONFIG_X86_64 1309 /* 1310 * Empirically, writing zero to a segment selector on AMD does 1311 * not clear the base, whereas writing zero to a segment 1312 * selector on Intel does clear the base. Intel's behavior 1313 * allows slightly faster context switches in the common case 1314 * where GS is unused by the prev and next threads. 1315 * 1316 * Since neither vendor documents this anywhere that I can see, 1317 * detect it directly instead of hardcoding the choice by 1318 * vendor. 1319 * 1320 * I've designated AMD's behavior as the "bug" because it's 1321 * counterintuitive and less friendly. 1322 */ 1323 1324 unsigned long old_base, tmp; 1325 rdmsrl(MSR_FS_BASE, old_base); 1326 wrmsrl(MSR_FS_BASE, 1); 1327 loadsegment(fs, 0); 1328 rdmsrl(MSR_FS_BASE, tmp); 1329 if (tmp != 0) 1330 set_cpu_bug(c, X86_BUG_NULL_SEG); 1331 wrmsrl(MSR_FS_BASE, old_base); 1332 #endif 1333 } 1334 1335 static void generic_identify(struct cpuinfo_x86 *c) 1336 { 1337 c->extended_cpuid_level = 0; 1338 1339 if (!have_cpuid_p()) 1340 identify_cpu_without_cpuid(c); 1341 1342 /* cyrix could have cpuid enabled via c_identify()*/ 1343 if (!have_cpuid_p()) 1344 return; 1345 1346 cpu_detect(c); 1347 1348 get_cpu_vendor(c); 1349 1350 get_cpu_cap(c); 1351 1352 get_cpu_address_sizes(c); 1353 1354 if (c->cpuid_level >= 0x00000001) { 1355 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1356 #ifdef CONFIG_X86_32 1357 # ifdef CONFIG_SMP 1358 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1359 # else 1360 c->apicid = c->initial_apicid; 1361 # endif 1362 #endif 1363 c->phys_proc_id = c->initial_apicid; 1364 } 1365 1366 get_model_name(c); /* Default name */ 1367 1368 detect_null_seg_behavior(c); 1369 1370 /* 1371 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1372 * systems that run Linux at CPL > 0 may or may not have the 1373 * issue, but, even if they have the issue, there's absolutely 1374 * nothing we can do about it because we can't use the real IRET 1375 * instruction. 1376 * 1377 * NB: For the time being, only 32-bit kernels support 1378 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1379 * whether to apply espfix using paravirt hooks. If any 1380 * non-paravirt system ever shows up that does *not* have the 1381 * ESPFIX issue, we can change this. 1382 */ 1383 #ifdef CONFIG_X86_32 1384 # ifdef CONFIG_PARAVIRT_XXL 1385 do { 1386 extern void native_iret(void); 1387 if (pv_ops.cpu.iret == native_iret) 1388 set_cpu_bug(c, X86_BUG_ESPFIX); 1389 } while (0); 1390 # else 1391 set_cpu_bug(c, X86_BUG_ESPFIX); 1392 # endif 1393 #endif 1394 } 1395 1396 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1397 { 1398 /* 1399 * The heavy lifting of max_rmid and cache_occ_scale are handled 1400 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1401 * in case CQM bits really aren't there in this CPU. 1402 */ 1403 if (c != &boot_cpu_data) { 1404 boot_cpu_data.x86_cache_max_rmid = 1405 min(boot_cpu_data.x86_cache_max_rmid, 1406 c->x86_cache_max_rmid); 1407 } 1408 } 1409 1410 /* 1411 * Validate that ACPI/mptables have the same information about the 1412 * effective APIC id and update the package map. 1413 */ 1414 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1415 { 1416 #ifdef CONFIG_SMP 1417 unsigned int apicid, cpu = smp_processor_id(); 1418 1419 apicid = apic->cpu_present_to_apicid(cpu); 1420 1421 if (apicid != c->apicid) { 1422 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1423 cpu, apicid, c->initial_apicid); 1424 } 1425 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1426 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1427 #else 1428 c->logical_proc_id = 0; 1429 #endif 1430 } 1431 1432 /* 1433 * This does the hard work of actually picking apart the CPU stuff... 1434 */ 1435 static void identify_cpu(struct cpuinfo_x86 *c) 1436 { 1437 int i; 1438 1439 c->loops_per_jiffy = loops_per_jiffy; 1440 c->x86_cache_size = 0; 1441 c->x86_vendor = X86_VENDOR_UNKNOWN; 1442 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1443 c->x86_vendor_id[0] = '\0'; /* Unset */ 1444 c->x86_model_id[0] = '\0'; /* Unset */ 1445 c->x86_max_cores = 1; 1446 c->x86_coreid_bits = 0; 1447 c->cu_id = 0xff; 1448 #ifdef CONFIG_X86_64 1449 c->x86_clflush_size = 64; 1450 c->x86_phys_bits = 36; 1451 c->x86_virt_bits = 48; 1452 #else 1453 c->cpuid_level = -1; /* CPUID not detected */ 1454 c->x86_clflush_size = 32; 1455 c->x86_phys_bits = 32; 1456 c->x86_virt_bits = 32; 1457 #endif 1458 c->x86_cache_alignment = c->x86_clflush_size; 1459 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1460 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1461 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1462 #endif 1463 1464 generic_identify(c); 1465 1466 if (this_cpu->c_identify) 1467 this_cpu->c_identify(c); 1468 1469 /* Clear/Set all flags overridden by options, after probe */ 1470 apply_forced_caps(c); 1471 1472 #ifdef CONFIG_X86_64 1473 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1474 #endif 1475 1476 /* 1477 * Vendor-specific initialization. In this section we 1478 * canonicalize the feature flags, meaning if there are 1479 * features a certain CPU supports which CPUID doesn't 1480 * tell us, CPUID claiming incorrect flags, or other bugs, 1481 * we handle them here. 1482 * 1483 * At the end of this section, c->x86_capability better 1484 * indicate the features this CPU genuinely supports! 1485 */ 1486 if (this_cpu->c_init) 1487 this_cpu->c_init(c); 1488 1489 /* Disable the PN if appropriate */ 1490 squash_the_stupid_serial_number(c); 1491 1492 /* Set up SMEP/SMAP/UMIP */ 1493 setup_smep(c); 1494 setup_smap(c); 1495 setup_umip(c); 1496 1497 /* 1498 * The vendor-specific functions might have changed features. 1499 * Now we do "generic changes." 1500 */ 1501 1502 /* Filter out anything that depends on CPUID levels we don't have */ 1503 filter_cpuid_features(c, true); 1504 1505 /* If the model name is still unset, do table lookup. */ 1506 if (!c->x86_model_id[0]) { 1507 const char *p; 1508 p = table_lookup_model(c); 1509 if (p) 1510 strcpy(c->x86_model_id, p); 1511 else 1512 /* Last resort... */ 1513 sprintf(c->x86_model_id, "%02x/%02x", 1514 c->x86, c->x86_model); 1515 } 1516 1517 #ifdef CONFIG_X86_64 1518 detect_ht(c); 1519 #endif 1520 1521 x86_init_rdrand(c); 1522 x86_init_cache_qos(c); 1523 setup_pku(c); 1524 1525 /* 1526 * Clear/Set all flags overridden by options, need do it 1527 * before following smp all cpus cap AND. 1528 */ 1529 apply_forced_caps(c); 1530 1531 /* 1532 * On SMP, boot_cpu_data holds the common feature set between 1533 * all CPUs; so make sure that we indicate which features are 1534 * common between the CPUs. The first time this routine gets 1535 * executed, c == &boot_cpu_data. 1536 */ 1537 if (c != &boot_cpu_data) { 1538 /* AND the already accumulated flags with these */ 1539 for (i = 0; i < NCAPINTS; i++) 1540 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1541 1542 /* OR, i.e. replicate the bug flags */ 1543 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1544 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1545 } 1546 1547 /* Init Machine Check Exception if available. */ 1548 mcheck_cpu_init(c); 1549 1550 select_idle_routine(c); 1551 1552 #ifdef CONFIG_NUMA 1553 numa_add_cpu(smp_processor_id()); 1554 #endif 1555 } 1556 1557 /* 1558 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1559 * on 32-bit kernels: 1560 */ 1561 #ifdef CONFIG_X86_32 1562 void enable_sep_cpu(void) 1563 { 1564 struct tss_struct *tss; 1565 int cpu; 1566 1567 if (!boot_cpu_has(X86_FEATURE_SEP)) 1568 return; 1569 1570 cpu = get_cpu(); 1571 tss = &per_cpu(cpu_tss_rw, cpu); 1572 1573 /* 1574 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1575 * see the big comment in struct x86_hw_tss's definition. 1576 */ 1577 1578 tss->x86_tss.ss1 = __KERNEL_CS; 1579 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1580 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1581 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1582 1583 put_cpu(); 1584 } 1585 #endif 1586 1587 void __init identify_boot_cpu(void) 1588 { 1589 identify_cpu(&boot_cpu_data); 1590 #ifdef CONFIG_X86_32 1591 sysenter_setup(); 1592 enable_sep_cpu(); 1593 #endif 1594 cpu_detect_tlb(&boot_cpu_data); 1595 setup_cr_pinning(); 1596 1597 tsx_init(); 1598 } 1599 1600 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1601 { 1602 BUG_ON(c == &boot_cpu_data); 1603 identify_cpu(c); 1604 #ifdef CONFIG_X86_32 1605 enable_sep_cpu(); 1606 #endif 1607 mtrr_ap_init(); 1608 validate_apic_and_package_id(c); 1609 x86_spec_ctrl_setup_ap(); 1610 } 1611 1612 static __init int setup_noclflush(char *arg) 1613 { 1614 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1615 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1616 return 1; 1617 } 1618 __setup("noclflush", setup_noclflush); 1619 1620 void print_cpu_info(struct cpuinfo_x86 *c) 1621 { 1622 const char *vendor = NULL; 1623 1624 if (c->x86_vendor < X86_VENDOR_NUM) { 1625 vendor = this_cpu->c_vendor; 1626 } else { 1627 if (c->cpuid_level >= 0) 1628 vendor = c->x86_vendor_id; 1629 } 1630 1631 if (vendor && !strstr(c->x86_model_id, vendor)) 1632 pr_cont("%s ", vendor); 1633 1634 if (c->x86_model_id[0]) 1635 pr_cont("%s", c->x86_model_id); 1636 else 1637 pr_cont("%d86", c->x86); 1638 1639 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1640 1641 if (c->x86_stepping || c->cpuid_level >= 0) 1642 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1643 else 1644 pr_cont(")\n"); 1645 } 1646 1647 /* 1648 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1649 * But we need to keep a dummy __setup around otherwise it would 1650 * show up as an environment variable for init. 1651 */ 1652 static __init int setup_clearcpuid(char *arg) 1653 { 1654 return 1; 1655 } 1656 __setup("clearcpuid=", setup_clearcpuid); 1657 1658 #ifdef CONFIG_X86_64 1659 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1660 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1661 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1662 1663 /* 1664 * The following percpu variables are hot. Align current_task to 1665 * cacheline size such that they fall in the same cacheline. 1666 */ 1667 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1668 &init_task; 1669 EXPORT_PER_CPU_SYMBOL(current_task); 1670 1671 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1672 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1673 1674 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1675 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1676 1677 /* May not be marked __init: used by software suspend */ 1678 void syscall_init(void) 1679 { 1680 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1681 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1682 1683 #ifdef CONFIG_IA32_EMULATION 1684 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1685 /* 1686 * This only works on Intel CPUs. 1687 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1688 * This does not cause SYSENTER to jump to the wrong location, because 1689 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1690 */ 1691 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1692 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1693 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1694 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1695 #else 1696 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1697 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1698 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1699 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1700 #endif 1701 1702 /* Flags to clear on syscall */ 1703 wrmsrl(MSR_SYSCALL_MASK, 1704 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1705 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1706 } 1707 1708 DEFINE_PER_CPU(int, debug_stack_usage); 1709 DEFINE_PER_CPU(u32, debug_idt_ctr); 1710 1711 void debug_stack_set_zero(void) 1712 { 1713 this_cpu_inc(debug_idt_ctr); 1714 load_current_idt(); 1715 } 1716 NOKPROBE_SYMBOL(debug_stack_set_zero); 1717 1718 void debug_stack_reset(void) 1719 { 1720 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1721 return; 1722 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1723 load_current_idt(); 1724 } 1725 NOKPROBE_SYMBOL(debug_stack_reset); 1726 1727 #else /* CONFIG_X86_64 */ 1728 1729 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1730 EXPORT_PER_CPU_SYMBOL(current_task); 1731 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1732 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1733 1734 /* 1735 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1736 * the top of the kernel stack. Use an extra percpu variable to track the 1737 * top of the kernel stack directly. 1738 */ 1739 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1740 (unsigned long)&init_thread_union + THREAD_SIZE; 1741 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1742 1743 #ifdef CONFIG_STACKPROTECTOR 1744 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1745 #endif 1746 1747 #endif /* CONFIG_X86_64 */ 1748 1749 /* 1750 * Clear all 6 debug registers: 1751 */ 1752 static void clear_all_debug_regs(void) 1753 { 1754 int i; 1755 1756 for (i = 0; i < 8; i++) { 1757 /* Ignore db4, db5 */ 1758 if ((i == 4) || (i == 5)) 1759 continue; 1760 1761 set_debugreg(0, i); 1762 } 1763 } 1764 1765 #ifdef CONFIG_KGDB 1766 /* 1767 * Restore debug regs if using kgdbwait and you have a kernel debugger 1768 * connection established. 1769 */ 1770 static void dbg_restore_debug_regs(void) 1771 { 1772 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1773 arch_kgdb_ops.correct_hw_break(); 1774 } 1775 #else /* ! CONFIG_KGDB */ 1776 #define dbg_restore_debug_regs() 1777 #endif /* ! CONFIG_KGDB */ 1778 1779 static void wait_for_master_cpu(int cpu) 1780 { 1781 #ifdef CONFIG_SMP 1782 /* 1783 * wait for ACK from master CPU before continuing 1784 * with AP initialization 1785 */ 1786 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1787 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1788 cpu_relax(); 1789 #endif 1790 } 1791 1792 #ifdef CONFIG_X86_64 1793 static inline void setup_getcpu(int cpu) 1794 { 1795 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1796 struct desc_struct d = { }; 1797 1798 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1799 write_rdtscp_aux(cpudata); 1800 1801 /* Store CPU and node number in limit. */ 1802 d.limit0 = cpudata; 1803 d.limit1 = cpudata >> 16; 1804 1805 d.type = 5; /* RO data, expand down, accessed */ 1806 d.dpl = 3; /* Visible to user code */ 1807 d.s = 1; /* Not a system segment */ 1808 d.p = 1; /* Present */ 1809 d.d = 1; /* 32-bit */ 1810 1811 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1812 } 1813 1814 static inline void ucode_cpu_init(int cpu) 1815 { 1816 if (cpu) 1817 load_ucode_ap(); 1818 } 1819 1820 static inline void tss_setup_ist(struct tss_struct *tss) 1821 { 1822 /* Set up the per-CPU TSS IST stacks */ 1823 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1824 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1825 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1826 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1827 } 1828 1829 #else /* CONFIG_X86_64 */ 1830 1831 static inline void setup_getcpu(int cpu) { } 1832 1833 static inline void ucode_cpu_init(int cpu) 1834 { 1835 show_ucode_info_early(); 1836 } 1837 1838 static inline void tss_setup_ist(struct tss_struct *tss) { } 1839 1840 #endif /* !CONFIG_X86_64 */ 1841 1842 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 1843 { 1844 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 1845 1846 #ifdef CONFIG_X86_IOPL_IOPERM 1847 tss->io_bitmap.prev_max = 0; 1848 tss->io_bitmap.prev_sequence = 0; 1849 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 1850 /* 1851 * Invalidate the extra array entry past the end of the all 1852 * permission bitmap as required by the hardware. 1853 */ 1854 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 1855 #endif 1856 } 1857 1858 /* 1859 * cpu_init() initializes state that is per-CPU. Some data is already 1860 * initialized (naturally) in the bootstrap process, such as the GDT 1861 * and IDT. We reload them nevertheless, this function acts as a 1862 * 'CPU state barrier', nothing should get across. 1863 */ 1864 void cpu_init(void) 1865 { 1866 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1867 struct task_struct *cur = current; 1868 int cpu = raw_smp_processor_id(); 1869 1870 wait_for_master_cpu(cpu); 1871 1872 ucode_cpu_init(cpu); 1873 1874 #ifdef CONFIG_NUMA 1875 if (this_cpu_read(numa_node) == 0 && 1876 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1877 set_numa_node(early_cpu_to_node(cpu)); 1878 #endif 1879 setup_getcpu(cpu); 1880 1881 pr_debug("Initializing CPU#%d\n", cpu); 1882 1883 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 1884 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 1885 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1886 1887 /* 1888 * Initialize the per-CPU GDT with the boot GDT, 1889 * and set up the GDT descriptor: 1890 */ 1891 switch_to_new_gdt(cpu); 1892 load_current_idt(); 1893 1894 if (IS_ENABLED(CONFIG_X86_64)) { 1895 loadsegment(fs, 0); 1896 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1897 syscall_init(); 1898 1899 wrmsrl(MSR_FS_BASE, 0); 1900 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1901 barrier(); 1902 1903 x2apic_setup(); 1904 } 1905 1906 mmgrab(&init_mm); 1907 cur->active_mm = &init_mm; 1908 BUG_ON(cur->mm); 1909 initialize_tlbstate_and_flush(); 1910 enter_lazy_tlb(&init_mm, cur); 1911 1912 /* Initialize the TSS. */ 1913 tss_setup_ist(tss); 1914 tss_setup_io_bitmap(tss); 1915 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1916 1917 load_TR_desc(); 1918 /* 1919 * sp0 points to the entry trampoline stack regardless of what task 1920 * is running. 1921 */ 1922 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1923 1924 load_mm_ldt(&init_mm); 1925 1926 clear_all_debug_regs(); 1927 dbg_restore_debug_regs(); 1928 1929 doublefault_init_cpu_tss(); 1930 1931 fpu__init_cpu(); 1932 1933 if (is_uv_system()) 1934 uv_cpu_init(); 1935 1936 load_fixmap_gdt(cpu); 1937 } 1938 1939 /* 1940 * The microcode loader calls this upon late microcode load to recheck features, 1941 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1942 * hotplug lock. 1943 */ 1944 void microcode_check(void) 1945 { 1946 struct cpuinfo_x86 info; 1947 1948 perf_check_microcode(); 1949 1950 /* Reload CPUID max function as it might've changed. */ 1951 info.cpuid_level = cpuid_eax(0); 1952 1953 /* 1954 * Copy all capability leafs to pick up the synthetic ones so that 1955 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1956 * get overwritten in get_cpu_cap(). 1957 */ 1958 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1959 1960 get_cpu_cap(&info); 1961 1962 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1963 return; 1964 1965 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1966 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1967 } 1968 1969 /* 1970 * Invoked from core CPU hotplug code after hotplug operations 1971 */ 1972 void arch_smt_update(void) 1973 { 1974 /* Handle the speculative execution misfeatures */ 1975 cpu_bugs_smt_update(); 1976 /* Check whether IPI broadcasting can be enabled */ 1977 apic_smt_update(); 1978 } 1979