1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/kvm_types.h> 11 #include <linux/percpu.h> 12 #include <linux/string.h> 13 #include <linux/ctype.h> 14 #include <linux/delay.h> 15 #include <linux/sched/mm.h> 16 #include <linux/sched/clock.h> 17 #include <linux/sched/task.h> 18 #include <linux/sched/smt.h> 19 #include <linux/init.h> 20 #include <linux/kprobes.h> 21 #include <linux/kgdb.h> 22 #include <linux/mem_encrypt.h> 23 #include <linux/smp.h> 24 #include <linux/cpu.h> 25 #include <linux/io.h> 26 #include <linux/syscore_ops.h> 27 #include <linux/pgtable.h> 28 #include <linux/stackprotector.h> 29 #include <linux/utsname.h> 30 #include <linux/efi.h> 31 32 #include <asm/alternative.h> 33 #include <asm/cmdline.h> 34 #include <asm/cpuid/api.h> 35 #include <asm/perf_event.h> 36 #include <asm/mmu_context.h> 37 #include <asm/doublefault.h> 38 #include <asm/archrandom.h> 39 #include <asm/hypervisor.h> 40 #include <asm/processor.h> 41 #include <asm/tlbflush.h> 42 #include <asm/debugreg.h> 43 #include <asm/sections.h> 44 #include <asm/vsyscall.h> 45 #include <linux/topology.h> 46 #include <linux/cpumask.h> 47 #include <linux/atomic.h> 48 #include <asm/proto.h> 49 #include <asm/setup.h> 50 #include <asm/apic.h> 51 #include <asm/desc.h> 52 #include <asm/fpu/api.h> 53 #include <asm/mtrr.h> 54 #include <asm/hwcap2.h> 55 #include <linux/numa.h> 56 #include <asm/numa.h> 57 #include <asm/asm.h> 58 #include <asm/bugs.h> 59 #include <asm/cpu.h> 60 #include <asm/mce.h> 61 #include <asm/msr.h> 62 #include <asm/cacheinfo.h> 63 #include <asm/memtype.h> 64 #include <asm/microcode.h> 65 #include <asm/intel-family.h> 66 #include <asm/cpu_device_id.h> 67 #include <asm/fred.h> 68 #include <asm/uv/uv.h> 69 #include <asm/ia32.h> 70 #include <asm/set_memory.h> 71 #include <asm/traps.h> 72 #include <asm/sev.h> 73 #include <asm/tdx.h> 74 #include <asm/posted_intr.h> 75 #include <asm/runtime-const.h> 76 77 #include "cpu.h" 78 79 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 80 EXPORT_PER_CPU_SYMBOL(cpu_info); 81 82 /* Used for modules: built-in code uses runtime constants */ 83 unsigned long USER_PTR_MAX; 84 EXPORT_SYMBOL(USER_PTR_MAX); 85 86 u32 elf_hwcap2 __read_mostly; 87 88 /* Number of siblings per CPU package */ 89 unsigned int __max_threads_per_core __ro_after_init = 1; 90 EXPORT_SYMBOL(__max_threads_per_core); 91 92 unsigned int __max_dies_per_package __ro_after_init = 1; 93 EXPORT_SYMBOL(__max_dies_per_package); 94 95 unsigned int __max_logical_packages __ro_after_init = 1; 96 EXPORT_SYMBOL(__max_logical_packages); 97 98 unsigned int __num_nodes_per_package __ro_after_init = 1; 99 EXPORT_SYMBOL(__num_nodes_per_package); 100 101 unsigned int __num_cores_per_package __ro_after_init = 1; 102 EXPORT_SYMBOL(__num_cores_per_package); 103 104 unsigned int __num_threads_per_package __ro_after_init = 1; 105 EXPORT_SYMBOL(__num_threads_per_package); 106 107 static struct ppin_info { 108 int feature; 109 int msr_ppin_ctl; 110 int msr_ppin; 111 } ppin_info[] = { 112 [X86_VENDOR_INTEL] = { 113 .feature = X86_FEATURE_INTEL_PPIN, 114 .msr_ppin_ctl = MSR_PPIN_CTL, 115 .msr_ppin = MSR_PPIN 116 }, 117 [X86_VENDOR_AMD] = { 118 .feature = X86_FEATURE_AMD_PPIN, 119 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 120 .msr_ppin = MSR_AMD_PPIN 121 }, 122 }; 123 124 static const struct x86_cpu_id ppin_cpuids[] = { 125 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 126 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 127 128 /* Legacy models without CPUID enumeration */ 129 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 130 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 131 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 132 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 133 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 134 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 135 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 136 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 137 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 138 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 139 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 140 141 {} 142 }; 143 144 static void ppin_init(struct cpuinfo_x86 *c) 145 { 146 const struct x86_cpu_id *id; 147 unsigned long long val; 148 struct ppin_info *info; 149 150 id = x86_match_cpu(ppin_cpuids); 151 if (!id) 152 return; 153 154 /* 155 * Testing the presence of the MSR is not enough. Need to check 156 * that the PPIN_CTL allows reading of the PPIN. 157 */ 158 info = (struct ppin_info *)id->driver_data; 159 160 if (rdmsrq_safe(info->msr_ppin_ctl, &val)) 161 goto clear_ppin; 162 163 if ((val & 3UL) == 1UL) { 164 /* PPIN locked in disabled mode */ 165 goto clear_ppin; 166 } 167 168 /* If PPIN is disabled, try to enable */ 169 if (!(val & 2UL)) { 170 wrmsrq_safe(info->msr_ppin_ctl, val | 2UL); 171 rdmsrq_safe(info->msr_ppin_ctl, &val); 172 } 173 174 /* Is the enable bit set? */ 175 if (val & 2UL) { 176 c->ppin = native_rdmsrq(info->msr_ppin); 177 set_cpu_cap(c, info->feature); 178 return; 179 } 180 181 clear_ppin: 182 setup_clear_cpu_cap(info->feature); 183 } 184 185 static void default_init(struct cpuinfo_x86 *c) 186 { 187 #ifdef CONFIG_X86_64 188 cpu_detect_cache_sizes(c); 189 #else 190 /* Not much we can do here... */ 191 /* Check if at least it has cpuid */ 192 if (c->cpuid_level == -1) { 193 /* No cpuid. It must be an ancient CPU */ 194 if (c->x86 == 4) 195 strcpy(c->x86_model_id, "486"); 196 else if (c->x86 == 3) 197 strcpy(c->x86_model_id, "386"); 198 } 199 #endif 200 } 201 202 static const struct cpu_dev default_cpu = { 203 .c_init = default_init, 204 .c_vendor = "Unknown", 205 .c_x86_vendor = X86_VENDOR_UNKNOWN, 206 }; 207 208 static const struct cpu_dev *this_cpu = &default_cpu; 209 210 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 211 #ifdef CONFIG_X86_64 212 /* 213 * We need valid kernel segments for data and code in long mode too 214 * IRET will check the segment types kkeil 2000/10/28 215 * Also sysret mandates a special GDT layout 216 * 217 * TLS descriptors are currently at a different place compared to i386. 218 * Hopefully nobody expects them at a fixed place (Wine?) 219 */ 220 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 221 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 222 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff), 223 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 224 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff), 225 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff), 226 #else 227 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 228 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 229 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 230 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff), 231 /* 232 * Segments used for calling PnP BIOS have byte granularity. 233 * They code segments and data segments have fixed 64k limits, 234 * the transfer segment sizes are set at run time. 235 */ 236 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 237 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 238 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff), 239 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 240 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 241 /* 242 * The APM segments have byte granularity and their bases 243 * are set at run time. All have 64k limits. 244 */ 245 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 246 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 247 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff), 248 249 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 250 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 251 #endif 252 } }; 253 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 254 SYM_PIC_ALIAS(gdt_page); 255 256 #ifdef CONFIG_X86_64 257 static int __init x86_nopcid_setup(char *s) 258 { 259 /* nopcid doesn't accept parameters */ 260 if (s) 261 return -EINVAL; 262 263 /* do not emit a message if the feature is not present */ 264 if (!boot_cpu_has(X86_FEATURE_PCID)) 265 return 0; 266 267 setup_clear_cpu_cap(X86_FEATURE_PCID); 268 pr_info("nopcid: PCID feature disabled\n"); 269 return 0; 270 } 271 early_param("nopcid", x86_nopcid_setup); 272 #endif 273 274 static int __init x86_noinvpcid_setup(char *s) 275 { 276 /* noinvpcid doesn't accept parameters */ 277 if (s) 278 return -EINVAL; 279 280 /* do not emit a message if the feature is not present */ 281 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 282 return 0; 283 284 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 285 pr_info("noinvpcid: INVPCID feature disabled\n"); 286 return 0; 287 } 288 early_param("noinvpcid", x86_noinvpcid_setup); 289 290 /* Standard macro to see if a specific flag is changeable */ 291 static inline bool flag_is_changeable_p(unsigned long flag) 292 { 293 unsigned long f1, f2; 294 295 if (!IS_ENABLED(CONFIG_X86_32)) 296 return true; 297 298 /* 299 * Cyrix and IDT cpus allow disabling of CPUID 300 * so the code below may return different results 301 * when it is executed before and after enabling 302 * the CPUID. Add "volatile" to not allow gcc to 303 * optimize the subsequent calls to this function. 304 */ 305 asm volatile ("pushfl \n\t" 306 "pushfl \n\t" 307 "popl %0 \n\t" 308 "movl %0, %1 \n\t" 309 "xorl %2, %0 \n\t" 310 "pushl %0 \n\t" 311 "popfl \n\t" 312 "pushfl \n\t" 313 "popl %0 \n\t" 314 "popfl \n\t" 315 316 : "=&r" (f1), "=&r" (f2) 317 : "ir" (flag)); 318 319 return (f1 ^ f2) & flag; 320 } 321 322 #ifdef CONFIG_X86_32 323 static int cachesize_override = -1; 324 static int disable_x86_serial_nr = 1; 325 326 static int __init cachesize_setup(char *str) 327 { 328 get_option(&str, &cachesize_override); 329 return 1; 330 } 331 __setup("cachesize=", cachesize_setup); 332 333 /* Probe for the CPUID instruction */ 334 bool cpuid_feature(void) 335 { 336 return flag_is_changeable_p(X86_EFLAGS_ID); 337 } 338 339 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 340 { 341 unsigned long lo, hi; 342 343 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 344 return; 345 346 /* Disable processor serial number: */ 347 348 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 349 lo |= 0x200000; 350 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 351 352 pr_notice("CPU serial number disabled.\n"); 353 clear_cpu_cap(c, X86_FEATURE_PN); 354 355 /* Disabling the serial number may affect the cpuid level */ 356 c->cpuid_level = cpuid_eax(0); 357 } 358 359 static int __init x86_serial_nr_setup(char *s) 360 { 361 disable_x86_serial_nr = 0; 362 return 1; 363 } 364 __setup("serialnumber", x86_serial_nr_setup); 365 #else 366 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 367 { 368 } 369 #endif 370 371 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 372 { 373 if (cpu_has(c, X86_FEATURE_SMEP)) 374 cr4_set_bits(X86_CR4_SMEP); 375 } 376 377 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 378 { 379 unsigned long eflags = native_save_fl(); 380 381 /* This should have been cleared long ago */ 382 BUG_ON(eflags & X86_EFLAGS_AC); 383 384 if (cpu_has(c, X86_FEATURE_SMAP)) 385 cr4_set_bits(X86_CR4_SMAP); 386 } 387 388 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 389 { 390 /* Check the boot processor, plus build option for UMIP. */ 391 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 392 goto out; 393 394 /* Check the current processor's cpuid bits. */ 395 if (!cpu_has(c, X86_FEATURE_UMIP)) 396 goto out; 397 398 cr4_set_bits(X86_CR4_UMIP); 399 400 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 401 402 return; 403 404 out: 405 /* 406 * Make sure UMIP is disabled in case it was enabled in a 407 * previous boot (e.g., via kexec). 408 */ 409 cr4_clear_bits(X86_CR4_UMIP); 410 } 411 412 static __always_inline void setup_lass(struct cpuinfo_x86 *c) 413 { 414 if (!cpu_feature_enabled(X86_FEATURE_LASS)) 415 return; 416 417 /* 418 * Legacy vsyscall page access causes a #GP when LASS is active. 419 * Disable LASS because the #GP handler doesn't support vsyscall 420 * emulation. 421 * 422 * Also disable LASS when running under EFI, as some runtime and 423 * boot services rely on 1:1 mappings in the lower half. 424 */ 425 if (IS_ENABLED(CONFIG_X86_VSYSCALL_EMULATION) || 426 IS_ENABLED(CONFIG_EFI)) { 427 setup_clear_cpu_cap(X86_FEATURE_LASS); 428 return; 429 } 430 431 cr4_set_bits(X86_CR4_LASS); 432 } 433 434 /* These bits should not change their value after CPU init is finished. */ 435 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 436 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; 437 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 438 static unsigned long cr4_pinned_bits __ro_after_init; 439 440 void native_write_cr0(unsigned long val) 441 { 442 unsigned long bits_missing = 0; 443 444 set_register: 445 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 446 447 if (static_branch_likely(&cr_pinning)) { 448 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 449 bits_missing = X86_CR0_WP; 450 val |= bits_missing; 451 goto set_register; 452 } 453 /* Warn after we've set the missing bits. */ 454 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 455 } 456 } 457 EXPORT_SYMBOL(native_write_cr0); 458 459 void __no_profile native_write_cr4(unsigned long val) 460 { 461 unsigned long bits_changed = 0; 462 463 set_register: 464 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 465 466 if (static_branch_likely(&cr_pinning)) { 467 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 468 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 469 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 470 goto set_register; 471 } 472 /* Warn after we've corrected the changed bits. */ 473 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 474 bits_changed); 475 } 476 } 477 #if IS_MODULE(CONFIG_LKDTM) 478 EXPORT_SYMBOL_GPL(native_write_cr4); 479 #endif 480 481 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 482 { 483 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 484 485 lockdep_assert_irqs_disabled(); 486 487 newval = (cr4 & ~clear) | set; 488 if (newval != cr4) { 489 this_cpu_write(cpu_tlbstate.cr4, newval); 490 __write_cr4(newval); 491 } 492 } 493 EXPORT_SYMBOL_FOR_KVM(cr4_update_irqsoff); 494 495 /* Read the CR4 shadow. */ 496 unsigned long cr4_read_shadow(void) 497 { 498 return this_cpu_read(cpu_tlbstate.cr4); 499 } 500 EXPORT_SYMBOL_FOR_KVM(cr4_read_shadow); 501 502 void cr4_init(void) 503 { 504 unsigned long cr4 = __read_cr4(); 505 506 if (boot_cpu_has(X86_FEATURE_PCID)) 507 cr4 |= X86_CR4_PCIDE; 508 if (static_branch_likely(&cr_pinning)) 509 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 510 511 __write_cr4(cr4); 512 513 /* Initialize cr4 shadow for this CPU. */ 514 this_cpu_write(cpu_tlbstate.cr4, cr4); 515 } 516 517 /* 518 * Once CPU feature detection is finished (and boot params have been 519 * parsed), record any of the sensitive CR bits that are set, and 520 * enable CR pinning. 521 */ 522 static void __init setup_cr_pinning(void) 523 { 524 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 525 static_key_enable(&cr_pinning.key); 526 } 527 528 static __init int x86_nofsgsbase_setup(char *arg) 529 { 530 /* Require an exact match without trailing characters. */ 531 if (strlen(arg)) 532 return 0; 533 534 /* Do not emit a message if the feature is not present. */ 535 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 536 return 1; 537 538 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 539 pr_info("FSGSBASE disabled via kernel command line\n"); 540 return 1; 541 } 542 __setup("nofsgsbase", x86_nofsgsbase_setup); 543 544 /* 545 * Protection Keys are not available in 32-bit mode. 546 */ 547 static bool pku_disabled; 548 549 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 550 { 551 if (c == &boot_cpu_data) { 552 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 553 return; 554 /* 555 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 556 * bit to be set. Enforce it. 557 */ 558 setup_force_cpu_cap(X86_FEATURE_OSPKE); 559 560 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 561 return; 562 } 563 564 cr4_set_bits(X86_CR4_PKE); 565 /* Load the default PKRU value */ 566 pkru_write_default(); 567 } 568 569 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 570 static __init int setup_disable_pku(char *arg) 571 { 572 /* 573 * Do not clear the X86_FEATURE_PKU bit. All of the 574 * runtime checks are against OSPKE so clearing the 575 * bit does nothing. 576 * 577 * This way, we will see "pku" in cpuinfo, but not 578 * "ospke", which is exactly what we want. It shows 579 * that the CPU has PKU, but the OS has not enabled it. 580 * This happens to be exactly how a system would look 581 * if we disabled the config option. 582 */ 583 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 584 pku_disabled = true; 585 return 1; 586 } 587 __setup("nopku", setup_disable_pku); 588 #endif 589 590 #ifdef CONFIG_X86_KERNEL_IBT 591 592 __noendbr u64 ibt_save(bool disable) 593 { 594 u64 msr = 0; 595 596 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 597 rdmsrq(MSR_IA32_S_CET, msr); 598 if (disable) 599 wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 600 } 601 602 return msr; 603 } 604 605 __noendbr void ibt_restore(u64 save) 606 { 607 u64 msr; 608 609 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 610 rdmsrq(MSR_IA32_S_CET, msr); 611 msr &= ~CET_ENDBR_EN; 612 msr |= (save & CET_ENDBR_EN); 613 wrmsrq(MSR_IA32_S_CET, msr); 614 } 615 } 616 617 #endif 618 619 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 620 { 621 bool user_shstk, kernel_ibt; 622 623 if (!IS_ENABLED(CONFIG_X86_CET)) 624 return; 625 626 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 627 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 628 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 629 630 if (!kernel_ibt && !user_shstk) 631 return; 632 633 if (user_shstk) 634 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 635 636 if (kernel_ibt) 637 wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN); 638 else 639 wrmsrq(MSR_IA32_S_CET, 0); 640 641 cr4_set_bits(X86_CR4_CET); 642 643 if (kernel_ibt && ibt_selftest()) { 644 pr_err("IBT selftest: Failed!\n"); 645 wrmsrq(MSR_IA32_S_CET, 0); 646 setup_clear_cpu_cap(X86_FEATURE_IBT); 647 } 648 } 649 650 __noendbr void cet_disable(void) 651 { 652 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 653 cpu_feature_enabled(X86_FEATURE_SHSTK))) 654 return; 655 656 wrmsrq(MSR_IA32_S_CET, 0); 657 wrmsrq(MSR_IA32_U_CET, 0); 658 } 659 660 /* 661 * Some CPU features depend on higher CPUID levels, which may not always 662 * be available due to CPUID level capping or broken virtualization 663 * software. Add those features to this table to auto-disable them. 664 */ 665 struct cpuid_dependent_feature { 666 u32 feature; 667 u32 level; 668 }; 669 670 static const struct cpuid_dependent_feature 671 cpuid_dependent_features[] = { 672 { X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT }, 673 { X86_FEATURE_DCA, CPUID_LEAF_DCA }, 674 { X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE }, 675 { 0, 0 } 676 }; 677 678 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 679 { 680 const struct cpuid_dependent_feature *df; 681 682 for (df = cpuid_dependent_features; df->feature; df++) { 683 684 if (!cpu_has(c, df->feature)) 685 continue; 686 /* 687 * Note: cpuid_level is set to -1 if unavailable, but 688 * extended_extended_level is set to 0 if unavailable 689 * and the legitimate extended levels are all negative 690 * when signed; hence the weird messing around with 691 * signs here... 692 */ 693 if (!((s32)df->level < 0 ? 694 (u32)df->level > (u32)c->extended_cpuid_level : 695 (s32)df->level > (s32)c->cpuid_level)) 696 continue; 697 698 clear_cpu_cap(c, df->feature); 699 if (!warn) 700 continue; 701 702 pr_warn("CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 703 x86_cap_flags[df->feature], df->level); 704 } 705 } 706 707 /* 708 * Naming convention should be: <Name> [(<Codename>)] 709 * This table only is used unless init_<vendor>() below doesn't set it; 710 * in particular, if CPUID levels 0x80000002..4 are supported, this 711 * isn't used 712 */ 713 714 /* Look up CPU names by table lookup. */ 715 static const char *table_lookup_model(struct cpuinfo_x86 *c) 716 { 717 #ifdef CONFIG_X86_32 718 const struct legacy_cpu_model_info *info; 719 720 if (c->x86_model >= 16) 721 return NULL; /* Range check */ 722 723 if (!this_cpu) 724 return NULL; 725 726 info = this_cpu->legacy_models; 727 728 while (info->family) { 729 if (info->family == c->x86) 730 return info->model_names[c->x86_model]; 731 info++; 732 } 733 #endif 734 return NULL; /* Not found */ 735 } 736 737 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 738 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 739 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 740 741 #ifdef CONFIG_X86_32 742 /* The 32-bit entry code needs to find cpu_entry_area. */ 743 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 744 #endif 745 746 /* Load the original GDT from the per-cpu structure */ 747 void load_direct_gdt(int cpu) 748 { 749 struct desc_ptr gdt_descr; 750 751 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 752 gdt_descr.size = GDT_SIZE - 1; 753 load_gdt(&gdt_descr); 754 } 755 EXPORT_SYMBOL_FOR_KVM(load_direct_gdt); 756 757 /* Load a fixmap remapping of the per-cpu GDT */ 758 void load_fixmap_gdt(int cpu) 759 { 760 struct desc_ptr gdt_descr; 761 762 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 763 gdt_descr.size = GDT_SIZE - 1; 764 load_gdt(&gdt_descr); 765 } 766 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 767 768 /** 769 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 770 * @cpu: The CPU number for which this is invoked 771 * 772 * Invoked during early boot to switch from early GDT and early per CPU to 773 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 774 * switch is implicit by loading the direct GDT. On 64bit this requires 775 * to update GSBASE. 776 */ 777 void __init switch_gdt_and_percpu_base(int cpu) 778 { 779 load_direct_gdt(cpu); 780 781 #ifdef CONFIG_X86_64 782 /* 783 * No need to load %gs. It is already correct. 784 * 785 * Writing %gs on 64bit would zero GSBASE which would make any per 786 * CPU operation up to the point of the wrmsrq() fault. 787 * 788 * Set GSBASE to the new offset. Until the wrmsrq() happens the 789 * early mapping is still valid. That means the GSBASE update will 790 * lose any prior per CPU data which was not copied over in 791 * setup_per_cpu_areas(). 792 * 793 * This works even with stackprotector enabled because the 794 * per CPU stack canary is 0 in both per CPU areas. 795 */ 796 wrmsrq(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 797 #else 798 /* 799 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 800 * it is required to load FS again so that the 'hidden' part is 801 * updated from the new GDT. Up to this point the early per CPU 802 * translation is active. Any content of the early per CPU data 803 * which was not copied over in setup_per_cpu_areas() is lost. 804 */ 805 loadsegment(fs, __KERNEL_PERCPU); 806 #endif 807 } 808 809 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 810 811 static void get_model_name(struct cpuinfo_x86 *c) 812 { 813 unsigned int *v; 814 char *p, *q, *s; 815 816 if (c->extended_cpuid_level < 0x80000004) 817 return; 818 819 v = (unsigned int *)c->x86_model_id; 820 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 821 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 822 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 823 c->x86_model_id[48] = 0; 824 825 /* Trim whitespace */ 826 p = q = s = &c->x86_model_id[0]; 827 828 while (*p == ' ') 829 p++; 830 831 while (*p) { 832 /* Note the last non-whitespace index */ 833 if (!isspace(*p)) 834 s = q; 835 836 *q++ = *p++; 837 } 838 839 *(s + 1) = '\0'; 840 } 841 842 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 843 { 844 unsigned int n, dummy, ebx, ecx, edx, l2size; 845 846 n = c->extended_cpuid_level; 847 848 if (n >= 0x80000005) { 849 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 850 c->x86_cache_size = (ecx>>24) + (edx>>24); 851 #ifdef CONFIG_X86_64 852 /* On K8 L1 TLB is inclusive, so don't count it */ 853 c->x86_tlbsize = 0; 854 #endif 855 } 856 857 if (n < 0x80000006) /* Some chips just has a large L1. */ 858 return; 859 860 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 861 l2size = ecx >> 16; 862 863 #ifdef CONFIG_X86_64 864 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 865 #else 866 /* do processor-specific cache resizing */ 867 if (this_cpu->legacy_cache_size) 868 l2size = this_cpu->legacy_cache_size(c, l2size); 869 870 /* Allow user to override all this if necessary. */ 871 if (cachesize_override != -1) 872 l2size = cachesize_override; 873 874 if (l2size == 0) 875 return; /* Again, no L2 cache is possible */ 876 #endif 877 878 c->x86_cache_size = l2size; 879 } 880 881 u16 __read_mostly tlb_lli_4k; 882 u16 __read_mostly tlb_lli_2m; 883 u16 __read_mostly tlb_lli_4m; 884 u16 __read_mostly tlb_lld_4k; 885 u16 __read_mostly tlb_lld_2m; 886 u16 __read_mostly tlb_lld_4m; 887 u16 __read_mostly tlb_lld_1g; 888 889 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 890 { 891 if (this_cpu->c_detect_tlb) 892 this_cpu->c_detect_tlb(c); 893 894 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 895 tlb_lli_4k, tlb_lli_2m, tlb_lli_4m); 896 897 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 898 tlb_lld_4k, tlb_lld_2m, tlb_lld_4m, tlb_lld_1g); 899 } 900 901 void get_cpu_vendor(struct cpuinfo_x86 *c) 902 { 903 char *v = c->x86_vendor_id; 904 int i; 905 906 for (i = 0; i < X86_VENDOR_NUM; i++) { 907 if (!cpu_devs[i]) 908 break; 909 910 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 911 (cpu_devs[i]->c_ident[1] && 912 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 913 914 this_cpu = cpu_devs[i]; 915 c->x86_vendor = this_cpu->c_x86_vendor; 916 return; 917 } 918 } 919 920 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 921 "CPU: Your system may be unstable.\n", v); 922 923 c->x86_vendor = X86_VENDOR_UNKNOWN; 924 this_cpu = &default_cpu; 925 } 926 927 void cpu_detect(struct cpuinfo_x86 *c) 928 { 929 /* Get vendor name */ 930 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 931 (unsigned int *)&c->x86_vendor_id[0], 932 (unsigned int *)&c->x86_vendor_id[8], 933 (unsigned int *)&c->x86_vendor_id[4]); 934 935 c->x86 = 4; 936 /* Intel-defined flags: level 0x00000001 */ 937 if (c->cpuid_level >= 0x00000001) { 938 u32 junk, tfms, cap0, misc; 939 940 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 941 c->x86 = x86_family(tfms); 942 c->x86_model = x86_model(tfms); 943 c->x86_stepping = x86_stepping(tfms); 944 945 if (cap0 & (1<<19)) { 946 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 947 c->x86_cache_alignment = c->x86_clflush_size; 948 } 949 } 950 } 951 952 static void apply_forced_caps(struct cpuinfo_x86 *c) 953 { 954 int i; 955 956 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 957 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 958 c->x86_capability[i] |= cpu_caps_set[i]; 959 } 960 } 961 962 static void init_speculation_control(struct cpuinfo_x86 *c) 963 { 964 /* 965 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 966 * and they also have a different bit for STIBP support. Also, 967 * a hypervisor might have set the individual AMD bits even on 968 * Intel CPUs, for finer-grained selection of what's available. 969 */ 970 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 971 set_cpu_cap(c, X86_FEATURE_IBRS); 972 set_cpu_cap(c, X86_FEATURE_IBPB); 973 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 974 } 975 976 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 977 set_cpu_cap(c, X86_FEATURE_STIBP); 978 979 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 980 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 981 set_cpu_cap(c, X86_FEATURE_SSBD); 982 983 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 984 set_cpu_cap(c, X86_FEATURE_IBRS); 985 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 986 } 987 988 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 989 set_cpu_cap(c, X86_FEATURE_IBPB); 990 991 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 992 set_cpu_cap(c, X86_FEATURE_STIBP); 993 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 994 } 995 996 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 997 set_cpu_cap(c, X86_FEATURE_SSBD); 998 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 999 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1000 } 1001 } 1002 1003 void get_cpu_cap(struct cpuinfo_x86 *c) 1004 { 1005 u32 eax, ebx, ecx, edx; 1006 1007 /* Intel-defined flags: level 0x00000001 */ 1008 if (c->cpuid_level >= 0x00000001) { 1009 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1010 1011 c->x86_capability[CPUID_1_ECX] = ecx; 1012 c->x86_capability[CPUID_1_EDX] = edx; 1013 } 1014 1015 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1016 if (c->cpuid_level >= 0x00000006) 1017 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1018 1019 /* Additional Intel-defined flags: level 0x00000007 */ 1020 if (c->cpuid_level >= 0x00000007) { 1021 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1022 c->x86_capability[CPUID_7_0_EBX] = ebx; 1023 c->x86_capability[CPUID_7_ECX] = ecx; 1024 c->x86_capability[CPUID_7_EDX] = edx; 1025 1026 /* Check valid sub-leaf index before accessing it */ 1027 if (eax >= 1) { 1028 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1029 c->x86_capability[CPUID_7_1_EAX] = eax; 1030 } 1031 } 1032 1033 /* Extended state features: level 0x0000000d */ 1034 if (c->cpuid_level >= 0x0000000d) { 1035 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1036 1037 c->x86_capability[CPUID_D_1_EAX] = eax; 1038 } 1039 1040 /* 1041 * Check if extended CPUID leaves are implemented: Max extended 1042 * CPUID leaf must be in the 0x80000001-0x8000ffff range. 1043 */ 1044 eax = cpuid_eax(0x80000000); 1045 c->extended_cpuid_level = ((eax & 0xffff0000) == 0x80000000) ? eax : 0; 1046 1047 if (c->extended_cpuid_level >= 0x80000001) { 1048 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1049 1050 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1051 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1052 } 1053 1054 if (c->extended_cpuid_level >= 0x80000007) 1055 c->x86_power = cpuid_edx(0x80000007); 1056 1057 if (c->extended_cpuid_level >= 0x80000008) { 1058 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1059 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1060 } 1061 1062 if (c->extended_cpuid_level >= 0x8000000a) 1063 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1064 1065 if (c->extended_cpuid_level >= 0x8000001f) 1066 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1067 1068 if (c->extended_cpuid_level >= 0x80000021) 1069 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1070 1071 init_scattered_cpuid_features(c); 1072 init_speculation_control(c); 1073 1074 if (IS_ENABLED(CONFIG_X86_64) || cpu_has(c, X86_FEATURE_SEP)) 1075 set_cpu_cap(c, X86_FEATURE_SYSFAST32); 1076 1077 /* 1078 * Clear/Set all flags overridden by options, after probe. 1079 * This needs to happen each time we re-probe, which may happen 1080 * several times during CPU initialization. 1081 */ 1082 apply_forced_caps(c); 1083 } 1084 1085 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1086 { 1087 u32 eax, ebx, ecx, edx; 1088 1089 if (!cpu_has(c, X86_FEATURE_CPUID) || 1090 (c->extended_cpuid_level < 0x80000008)) { 1091 if (IS_ENABLED(CONFIG_X86_64)) { 1092 c->x86_clflush_size = 64; 1093 c->x86_phys_bits = 36; 1094 c->x86_virt_bits = 48; 1095 } else { 1096 c->x86_clflush_size = 32; 1097 c->x86_virt_bits = 32; 1098 c->x86_phys_bits = 32; 1099 1100 if (cpu_has(c, X86_FEATURE_PAE) || 1101 cpu_has(c, X86_FEATURE_PSE36)) 1102 c->x86_phys_bits = 36; 1103 } 1104 } else { 1105 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1106 1107 c->x86_virt_bits = (eax >> 8) & 0xff; 1108 c->x86_phys_bits = eax & 0xff; 1109 1110 /* Provide a sane default if not enumerated: */ 1111 if (!c->x86_clflush_size) 1112 c->x86_clflush_size = 32; 1113 } 1114 1115 c->x86_cache_bits = c->x86_phys_bits; 1116 c->x86_cache_alignment = c->x86_clflush_size; 1117 } 1118 1119 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1120 { 1121 int i; 1122 1123 /* 1124 * First of all, decide if this is a 486 or higher 1125 * It's a 486 if we can modify the AC flag 1126 */ 1127 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1128 c->x86 = 4; 1129 else 1130 c->x86 = 3; 1131 1132 for (i = 0; i < X86_VENDOR_NUM; i++) 1133 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1134 c->x86_vendor_id[0] = 0; 1135 cpu_devs[i]->c_identify(c); 1136 if (c->x86_vendor_id[0]) { 1137 get_cpu_vendor(c); 1138 break; 1139 } 1140 } 1141 } 1142 1143 #define NO_SPECULATION BIT(0) 1144 #define NO_MELTDOWN BIT(1) 1145 #define NO_SSB BIT(2) 1146 #define NO_L1TF BIT(3) 1147 #define NO_MDS BIT(4) 1148 #define MSBDS_ONLY BIT(5) 1149 #define NO_SWAPGS BIT(6) 1150 #define NO_ITLB_MULTIHIT BIT(7) 1151 #define NO_SPECTRE_V2 BIT(8) 1152 #define NO_MMIO BIT(9) 1153 #define NO_EIBRS_PBRSB BIT(10) 1154 #define NO_BHI BIT(11) 1155 1156 #define VULNWL(vendor, family, model, whitelist) \ 1157 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1158 1159 #define VULNWL_INTEL(vfm, whitelist) \ 1160 X86_MATCH_VFM(vfm, whitelist) 1161 1162 #define VULNWL_AMD(family, whitelist) \ 1163 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1164 1165 #define VULNWL_HYGON(family, whitelist) \ 1166 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1167 1168 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1169 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1170 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1171 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1172 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1173 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1174 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1175 1176 /* Intel Family 6 */ 1177 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), 1178 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), 1179 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), 1180 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), 1181 1182 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1183 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1184 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1185 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1186 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1187 1188 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1189 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1190 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1191 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1192 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1193 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1194 1195 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), 1196 1197 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY), 1198 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1199 1200 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1201 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1202 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1203 1204 /* 1205 * Technically, swapgs isn't serializing on AMD (despite it previously 1206 * being documented as such in the APM). But according to AMD, %gs is 1207 * updated non-speculatively, and the issuing of %gs-relative memory 1208 * operands will be blocked until the %gs update completes, which is 1209 * good enough for our purposes. 1210 */ 1211 1212 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), 1213 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1214 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1215 1216 /* AMD Family 0xf - 0x12 */ 1217 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1218 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1219 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1220 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1221 1222 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1223 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1224 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1225 1226 /* Zhaoxin Family 7 */ 1227 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1228 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1229 {} 1230 }; 1231 1232 #define VULNBL(vendor, family, model, blacklist) \ 1233 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1234 1235 #define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \ 1236 X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues) 1237 1238 #define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \ 1239 X86_MATCH_VFM_CPU_TYPE(vfm, INTEL_CPU_TYPE_##cpu_type, issues) 1240 1241 #define VULNBL_AMD(family, blacklist) \ 1242 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1243 1244 #define VULNBL_HYGON(family, blacklist) \ 1245 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1246 1247 #define SRBDS BIT(0) 1248 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1249 #define MMIO BIT(1) 1250 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1251 #define MMIO_SBDS BIT(2) 1252 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1253 #define RETBLEED BIT(3) 1254 /* CPU is affected by SMT (cross-thread) return predictions */ 1255 #define SMT_RSB BIT(4) 1256 /* CPU is affected by SRSO */ 1257 #define SRSO BIT(5) 1258 /* CPU is affected by GDS */ 1259 #define GDS BIT(6) 1260 /* CPU is affected by Register File Data Sampling */ 1261 #define RFDS BIT(7) 1262 /* CPU is affected by Indirect Target Selection */ 1263 #define ITS BIT(8) 1264 /* CPU is affected by Indirect Target Selection, but guest-host isolation is not affected */ 1265 #define ITS_NATIVE_ONLY BIT(9) 1266 /* CPU is affected by Transient Scheduler Attacks */ 1267 #define TSA BIT(10) 1268 /* CPU is affected by VMSCAPE */ 1269 #define VMSCAPE BIT(11) 1270 1271 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1272 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE_X, X86_STEP_MAX, VMSCAPE), 1273 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE, X86_STEP_MAX, VMSCAPE), 1274 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE_X, X86_STEP_MAX, VMSCAPE), 1275 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS | VMSCAPE), 1276 VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS | VMSCAPE), 1277 VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS | VMSCAPE), 1278 VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE), 1279 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO | VMSCAPE), 1280 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO | VMSCAPE), 1281 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO | VMSCAPE), 1282 VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE), 1283 VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS | VMSCAPE), 1284 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, 0x5, MMIO | RETBLEED | GDS | VMSCAPE), 1285 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | VMSCAPE), 1286 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1287 VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1288 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, 0xb, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1289 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE), 1290 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, 0xc, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1291 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE), 1292 VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED | VMSCAPE), 1293 VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1294 VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1295 VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1296 VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE), 1297 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED | ITS | VMSCAPE), 1298 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE), 1299 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1300 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1301 VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED), 1302 VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1303 VULNBL_INTEL_TYPE(INTEL_ALDERLAKE, ATOM, RFDS | VMSCAPE), 1304 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE, X86_STEP_MAX, VMSCAPE), 1305 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS | VMSCAPE), 1306 VULNBL_INTEL_TYPE(INTEL_RAPTORLAKE, ATOM, RFDS | VMSCAPE), 1307 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE, X86_STEP_MAX, VMSCAPE), 1308 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS | VMSCAPE), 1309 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS | VMSCAPE), 1310 VULNBL_INTEL_STEPS(INTEL_METEORLAKE_L, X86_STEP_MAX, VMSCAPE), 1311 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_H, X86_STEP_MAX, VMSCAPE), 1312 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE, X86_STEP_MAX, VMSCAPE), 1313 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_U, X86_STEP_MAX, VMSCAPE), 1314 VULNBL_INTEL_STEPS(INTEL_LUNARLAKE_M, X86_STEP_MAX, VMSCAPE), 1315 VULNBL_INTEL_STEPS(INTEL_SAPPHIRERAPIDS_X, X86_STEP_MAX, VMSCAPE), 1316 VULNBL_INTEL_STEPS(INTEL_GRANITERAPIDS_X, X86_STEP_MAX, VMSCAPE), 1317 VULNBL_INTEL_STEPS(INTEL_EMERALDRAPIDS_X, X86_STEP_MAX, VMSCAPE), 1318 VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS | VMSCAPE), 1319 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1320 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS), 1321 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1322 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS), 1323 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS), 1324 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS), 1325 VULNBL_INTEL_STEPS(INTEL_ATOM_CRESTMONT_X, X86_STEP_MAX, VMSCAPE), 1326 1327 VULNBL_AMD(0x15, RETBLEED), 1328 VULNBL_AMD(0x16, RETBLEED), 1329 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO | VMSCAPE), 1330 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO | VMSCAPE), 1331 VULNBL_AMD(0x19, SRSO | TSA | VMSCAPE), 1332 VULNBL_AMD(0x1a, SRSO | VMSCAPE), 1333 {} 1334 }; 1335 1336 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1337 { 1338 const struct x86_cpu_id *m = x86_match_cpu(table); 1339 1340 return m && !!(m->driver_data & which); 1341 } 1342 1343 u64 x86_read_arch_cap_msr(void) 1344 { 1345 u64 x86_arch_cap_msr = 0; 1346 1347 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1348 rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1349 1350 return x86_arch_cap_msr; 1351 } 1352 1353 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr) 1354 { 1355 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO && 1356 x86_arch_cap_msr & ARCH_CAP_PSDP_NO && 1357 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO); 1358 } 1359 1360 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr) 1361 { 1362 /* The "immunity" bit trumps everything else: */ 1363 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO) 1364 return false; 1365 1366 /* 1367 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to 1368 * indicate that mitigation is needed because guest is running on a 1369 * vulnerable hardware or may migrate to such hardware: 1370 */ 1371 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 1372 return true; 1373 1374 /* Only consult the blacklist when there is no enumeration: */ 1375 return cpu_matches(cpu_vuln_blacklist, RFDS); 1376 } 1377 1378 static bool __init vulnerable_to_its(u64 x86_arch_cap_msr) 1379 { 1380 /* The "immunity" bit trumps everything else: */ 1381 if (x86_arch_cap_msr & ARCH_CAP_ITS_NO) 1382 return false; 1383 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 1384 return false; 1385 1386 /* None of the affected CPUs have BHI_CTRL */ 1387 if (boot_cpu_has(X86_FEATURE_BHI_CTRL)) 1388 return false; 1389 1390 /* 1391 * If a VMM did not expose ITS_NO, assume that a guest could 1392 * be running on a vulnerable hardware or may migrate to such 1393 * hardware. 1394 */ 1395 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1396 return true; 1397 1398 if (cpu_matches(cpu_vuln_blacklist, ITS)) 1399 return true; 1400 1401 return false; 1402 } 1403 1404 static struct x86_cpu_id cpu_latest_microcode[] = { 1405 #include "microcode/intel-ucode-defs.h" 1406 {} 1407 }; 1408 1409 static bool __init cpu_has_old_microcode(void) 1410 { 1411 const struct x86_cpu_id *m = x86_match_cpu(cpu_latest_microcode); 1412 1413 /* Give unknown CPUs a pass: */ 1414 if (!m) { 1415 /* Intel CPUs should be in the list. Warn if not: */ 1416 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 1417 pr_info("x86/CPU: Model not found in latest microcode list\n"); 1418 return false; 1419 } 1420 1421 /* 1422 * Hosts usually lie to guests with a super high microcode 1423 * version. Just ignore what hosts tell guests: 1424 */ 1425 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1426 return false; 1427 1428 /* Consider all debug microcode to be old: */ 1429 if (boot_cpu_data.microcode & BIT(31)) 1430 return true; 1431 1432 /* Give new microcode a pass: */ 1433 if (boot_cpu_data.microcode >= m->driver_data) 1434 return false; 1435 1436 /* Uh oh, too old: */ 1437 return true; 1438 } 1439 1440 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1441 { 1442 u64 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1443 1444 if (cpu_has_old_microcode()) { 1445 pr_warn("x86/CPU: Running old microcode\n"); 1446 setup_force_cpu_bug(X86_BUG_OLD_MICROCODE); 1447 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1448 } 1449 1450 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1451 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1452 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO)) 1453 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1454 1455 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1456 return; 1457 1458 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1459 1460 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) { 1461 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1462 setup_force_cpu_bug(X86_BUG_SPECTRE_V2_USER); 1463 } 1464 1465 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1466 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) && 1467 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1468 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1469 1470 /* 1471 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1472 * flag and protect from vendor-specific bugs via the whitelist. 1473 * 1474 * Don't use AutoIBRS when SNP is enabled because it degrades host 1475 * userspace indirect branch performance. 1476 */ 1477 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || 1478 (cpu_has(c, X86_FEATURE_AUTOIBRS) && 1479 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { 1480 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1481 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1482 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO)) 1483 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1484 } 1485 1486 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1487 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) { 1488 setup_force_cpu_bug(X86_BUG_MDS); 1489 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1490 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1491 } 1492 1493 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1494 setup_force_cpu_bug(X86_BUG_SWAPGS); 1495 1496 /* 1497 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1498 * - TSX is supported or 1499 * - TSX_CTRL is present 1500 * 1501 * TSX_CTRL check is needed for cases when TSX could be disabled before 1502 * the kernel boot e.g. kexec. 1503 * TSX_CTRL check alone is not sufficient for cases when the microcode 1504 * update is not present or running as guest that don't get TSX_CTRL. 1505 */ 1506 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) && 1507 (cpu_has(c, X86_FEATURE_RTM) || 1508 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))) 1509 setup_force_cpu_bug(X86_BUG_TAA); 1510 1511 /* 1512 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1513 * in the vulnerability blacklist. 1514 * 1515 * Some of the implications and mitigation of Shared Buffers Data 1516 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1517 * SRBDS. 1518 */ 1519 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1520 cpu_has(c, X86_FEATURE_RDSEED)) && 1521 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1522 setup_force_cpu_bug(X86_BUG_SRBDS); 1523 1524 /* 1525 * Processor MMIO Stale Data bug enumeration 1526 * 1527 * Affected CPU list is generally enough to enumerate the vulnerability, 1528 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1529 * not want the guest to enumerate the bug. 1530 */ 1531 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { 1532 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1533 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1534 } 1535 1536 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1537 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA)) 1538 setup_force_cpu_bug(X86_BUG_RETBLEED); 1539 } 1540 1541 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1542 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1543 1544 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1545 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1546 setup_force_cpu_bug(X86_BUG_SRSO); 1547 } 1548 1549 /* 1550 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1551 * an affected processor, the VMM may have disabled the use of GATHER by 1552 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1553 * which means that AVX will be disabled. 1554 */ 1555 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) && 1556 boot_cpu_has(X86_FEATURE_AVX)) 1557 setup_force_cpu_bug(X86_BUG_GDS); 1558 1559 if (vulnerable_to_rfds(x86_arch_cap_msr)) 1560 setup_force_cpu_bug(X86_BUG_RFDS); 1561 1562 /* 1563 * Intel parts with eIBRS are vulnerable to BHI attacks. Parts with 1564 * BHI_NO still need to use the BHI mitigation to prevent Intra-mode 1565 * attacks. When virtualized, eIBRS could be hidden, assume vulnerable. 1566 */ 1567 if (!cpu_matches(cpu_vuln_whitelist, NO_BHI) && 1568 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) || 1569 boot_cpu_has(X86_FEATURE_HYPERVISOR))) 1570 setup_force_cpu_bug(X86_BUG_BHI); 1571 1572 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET)) 1573 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET); 1574 1575 if (vulnerable_to_its(x86_arch_cap_msr)) { 1576 setup_force_cpu_bug(X86_BUG_ITS); 1577 if (cpu_matches(cpu_vuln_blacklist, ITS_NATIVE_ONLY)) 1578 setup_force_cpu_bug(X86_BUG_ITS_NATIVE_ONLY); 1579 } 1580 1581 if (c->x86_vendor == X86_VENDOR_AMD) { 1582 if (!cpu_has(c, X86_FEATURE_TSA_SQ_NO) || 1583 !cpu_has(c, X86_FEATURE_TSA_L1_NO)) { 1584 if (cpu_matches(cpu_vuln_blacklist, TSA) || 1585 /* Enable bug on Zen guests to allow for live migration. */ 1586 (cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_ZEN))) 1587 setup_force_cpu_bug(X86_BUG_TSA); 1588 } 1589 } 1590 1591 /* 1592 * Set the bug only on bare-metal. A nested hypervisor should already be 1593 * deploying IBPB to isolate itself from nested guests. 1594 */ 1595 if (cpu_matches(cpu_vuln_blacklist, VMSCAPE) && 1596 !boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1597 setup_force_cpu_bug(X86_BUG_VMSCAPE); 1598 1599 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1600 return; 1601 1602 /* Rogue Data Cache Load? No! */ 1603 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO) 1604 return; 1605 1606 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1607 1608 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1609 return; 1610 1611 setup_force_cpu_bug(X86_BUG_L1TF); 1612 } 1613 1614 /* 1615 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1616 * unfortunately, that's not true in practice because of early VIA 1617 * chips and (more importantly) broken virtualizers that are not easy 1618 * to detect. In the latter case it doesn't even *fail* reliably, so 1619 * probing for it doesn't even work. Disable it completely on 32-bit 1620 * unless we can find a reliable way to detect all the broken cases. 1621 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1622 */ 1623 static void detect_nopl(void) 1624 { 1625 #ifdef CONFIG_X86_32 1626 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1627 #else 1628 setup_force_cpu_cap(X86_FEATURE_NOPL); 1629 #endif 1630 } 1631 1632 static inline bool parse_set_clear_cpuid(char *arg, bool set) 1633 { 1634 char *opt; 1635 int taint = 0; 1636 1637 while (arg) { 1638 bool found __maybe_unused = false; 1639 unsigned int bit; 1640 1641 opt = strsep(&arg, ","); 1642 1643 /* 1644 * Handle naked numbers first for feature flags which don't 1645 * have names. It doesn't make sense for a bug not to have a 1646 * name so don't handle bug flags here. 1647 */ 1648 if (!kstrtouint(opt, 10, &bit)) { 1649 if (bit < NCAPINTS * 32) { 1650 1651 if (set) { 1652 pr_warn("setcpuid: force-enabling CPU feature flag:"); 1653 setup_force_cpu_cap(bit); 1654 } else { 1655 pr_warn("clearcpuid: force-disabling CPU feature flag:"); 1656 setup_clear_cpu_cap(bit); 1657 } 1658 /* empty-string, i.e., ""-defined feature flags */ 1659 if (!x86_cap_flags[bit]) 1660 pr_cont(" %d:%d\n", bit >> 5, bit & 31); 1661 else 1662 pr_cont(" %s\n", x86_cap_flags[bit]); 1663 1664 taint++; 1665 } 1666 /* 1667 * The assumption is that there are no feature names with only 1668 * numbers in the name thus go to the next argument. 1669 */ 1670 continue; 1671 } 1672 1673 for (bit = 0; bit < 32 * (NCAPINTS + NBUGINTS); bit++) { 1674 const char *flag; 1675 const char *kind; 1676 1677 if (bit < 32 * NCAPINTS) { 1678 flag = x86_cap_flags[bit]; 1679 kind = "feature"; 1680 } else { 1681 kind = "bug"; 1682 flag = x86_bug_flags[bit - (32 * NCAPINTS)]; 1683 } 1684 1685 if (!flag) 1686 continue; 1687 1688 if (strcmp(flag, opt)) 1689 continue; 1690 1691 if (set) { 1692 pr_warn("setcpuid: force-enabling CPU %s flag: %s\n", 1693 kind, flag); 1694 setup_force_cpu_cap(bit); 1695 } else { 1696 pr_warn("clearcpuid: force-disabling CPU %s flag: %s\n", 1697 kind, flag); 1698 setup_clear_cpu_cap(bit); 1699 } 1700 taint++; 1701 found = true; 1702 break; 1703 } 1704 1705 if (!found) 1706 pr_warn("%s: unknown CPU flag: %s", set ? "setcpuid" : "clearcpuid", opt); 1707 } 1708 1709 return taint; 1710 } 1711 1712 1713 /* 1714 * We parse cpu parameters early because fpu__init_system() is executed 1715 * before parse_early_param(). 1716 */ 1717 static void __init cpu_parse_early_param(void) 1718 { 1719 bool cpuid_taint = false; 1720 char arg[128]; 1721 int arglen; 1722 1723 #ifdef CONFIG_X86_32 1724 if (cmdline_find_option_bool(boot_command_line, "no387")) 1725 #ifdef CONFIG_MATH_EMULATION 1726 setup_clear_cpu_cap(X86_FEATURE_FPU); 1727 #else 1728 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1729 #endif 1730 1731 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1732 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1733 #endif 1734 1735 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1736 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1737 1738 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1739 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1740 1741 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1742 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1743 1744 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1745 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1746 1747 /* Minimize the gap between FRED is available and available but disabled. */ 1748 arglen = cmdline_find_option(boot_command_line, "fred", arg, sizeof(arg)); 1749 if (arglen != 2 || strncmp(arg, "on", 2)) 1750 setup_clear_cpu_cap(X86_FEATURE_FRED); 1751 1752 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1753 if (arglen > 0) 1754 cpuid_taint |= parse_set_clear_cpuid(arg, false); 1755 1756 arglen = cmdline_find_option(boot_command_line, "setcpuid", arg, sizeof(arg)); 1757 if (arglen > 0) 1758 cpuid_taint |= parse_set_clear_cpuid(arg, true); 1759 1760 if (cpuid_taint) { 1761 pr_warn("!!! setcpuid=/clearcpuid= in use, this is for TESTING ONLY, may break things horribly. Tainting kernel.\n"); 1762 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1763 } 1764 } 1765 1766 /* 1767 * Do minimum CPU detection early. 1768 * Fields really needed: vendor, cpuid_level, family, model, mask, 1769 * cache alignment. 1770 * The others are not touched to avoid unwanted side effects. 1771 * 1772 * WARNING: this function is only called on the boot CPU. Don't add code 1773 * here that is supposed to run on all CPUs. 1774 */ 1775 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1776 { 1777 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1778 c->extended_cpuid_level = 0; 1779 1780 if (!cpuid_feature()) 1781 identify_cpu_without_cpuid(c); 1782 1783 /* cyrix could have cpuid enabled via c_identify()*/ 1784 if (cpuid_feature()) { 1785 cpu_detect(c); 1786 get_cpu_vendor(c); 1787 intel_unlock_cpuid_leafs(c); 1788 get_cpu_cap(c); 1789 setup_force_cpu_cap(X86_FEATURE_CPUID); 1790 get_cpu_address_sizes(c); 1791 cpu_parse_early_param(); 1792 1793 cpu_init_topology(c); 1794 1795 if (this_cpu->c_early_init) 1796 this_cpu->c_early_init(c); 1797 1798 c->cpu_index = 0; 1799 filter_cpuid_features(c, false); 1800 check_cpufeature_deps(c); 1801 1802 if (this_cpu->c_bsp_init) 1803 this_cpu->c_bsp_init(c); 1804 } else { 1805 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1806 get_cpu_address_sizes(c); 1807 cpu_init_topology(c); 1808 } 1809 1810 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1811 1812 cpu_set_bug_bits(c); 1813 1814 sld_setup(c); 1815 1816 #ifdef CONFIG_X86_32 1817 /* 1818 * Regardless of whether PCID is enumerated, the SDM says 1819 * that it can't be enabled in 32-bit mode. 1820 */ 1821 setup_clear_cpu_cap(X86_FEATURE_PCID); 1822 1823 /* 1824 * Never use SYSCALL on a 32-bit kernel 1825 */ 1826 setup_clear_cpu_cap(X86_FEATURE_SYSCALL32); 1827 #endif 1828 1829 /* 1830 * Later in the boot process pgtable_l5_enabled() relies on 1831 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1832 * enabled by this point we need to clear the feature bit to avoid 1833 * false-positives at the later stage. 1834 * 1835 * pgtable_l5_enabled() can be false here for several reasons: 1836 * - 5-level paging is disabled compile-time; 1837 * - it's 32-bit kernel; 1838 * - machine doesn't support 5-level paging; 1839 * - user specified 'no5lvl' in kernel command line. 1840 */ 1841 if (!pgtable_l5_enabled()) 1842 setup_clear_cpu_cap(X86_FEATURE_LA57); 1843 1844 detect_nopl(); 1845 mca_bsp_init(c); 1846 } 1847 1848 void __init init_cpu_devs(void) 1849 { 1850 const struct cpu_dev *const *cdev; 1851 int count = 0; 1852 1853 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1854 const struct cpu_dev *cpudev = *cdev; 1855 1856 if (count >= X86_VENDOR_NUM) 1857 break; 1858 cpu_devs[count] = cpudev; 1859 count++; 1860 } 1861 } 1862 1863 void __init early_cpu_init(void) 1864 { 1865 #ifdef CONFIG_PROCESSOR_SELECT 1866 unsigned int i, j; 1867 1868 pr_info("KERNEL supported cpus:\n"); 1869 #endif 1870 1871 init_cpu_devs(); 1872 1873 #ifdef CONFIG_PROCESSOR_SELECT 1874 for (i = 0; i < X86_VENDOR_NUM && cpu_devs[i]; i++) { 1875 for (j = 0; j < 2; j++) { 1876 if (!cpu_devs[i]->c_ident[j]) 1877 continue; 1878 pr_info(" %s %s\n", cpu_devs[i]->c_vendor, 1879 cpu_devs[i]->c_ident[j]); 1880 } 1881 } 1882 #endif 1883 1884 early_identify_cpu(&boot_cpu_data); 1885 } 1886 1887 static bool detect_null_seg_behavior(void) 1888 { 1889 /* 1890 * Empirically, writing zero to a segment selector on AMD does 1891 * not clear the base, whereas writing zero to a segment 1892 * selector on Intel does clear the base. Intel's behavior 1893 * allows slightly faster context switches in the common case 1894 * where GS is unused by the prev and next threads. 1895 * 1896 * Since neither vendor documents this anywhere that I can see, 1897 * detect it directly instead of hard-coding the choice by 1898 * vendor. 1899 * 1900 * I've designated AMD's behavior as the "bug" because it's 1901 * counterintuitive and less friendly. 1902 */ 1903 1904 unsigned long old_base, tmp; 1905 rdmsrq(MSR_FS_BASE, old_base); 1906 wrmsrq(MSR_FS_BASE, 1); 1907 loadsegment(fs, 0); 1908 rdmsrq(MSR_FS_BASE, tmp); 1909 wrmsrq(MSR_FS_BASE, old_base); 1910 return tmp == 0; 1911 } 1912 1913 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1914 { 1915 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1916 if (!IS_ENABLED(CONFIG_X86_64)) 1917 return; 1918 1919 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1920 return; 1921 1922 /* 1923 * CPUID bit above wasn't set. If this kernel is still running 1924 * as a HV guest, then the HV has decided not to advertize 1925 * that CPUID bit for whatever reason. For example, one 1926 * member of the migration pool might be vulnerable. Which 1927 * means, the bug is present: set the BUG flag and return. 1928 */ 1929 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1930 set_cpu_bug(c, X86_BUG_NULL_SEG); 1931 return; 1932 } 1933 1934 /* 1935 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1936 * 0x18 is the respective family for Hygon. 1937 */ 1938 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1939 detect_null_seg_behavior()) 1940 return; 1941 1942 /* All the remaining ones are affected */ 1943 set_cpu_bug(c, X86_BUG_NULL_SEG); 1944 } 1945 1946 static void generic_identify(struct cpuinfo_x86 *c) 1947 { 1948 c->extended_cpuid_level = 0; 1949 1950 if (!cpuid_feature()) 1951 identify_cpu_without_cpuid(c); 1952 1953 /* cyrix could have cpuid enabled via c_identify()*/ 1954 if (!cpuid_feature()) 1955 return; 1956 1957 cpu_detect(c); 1958 1959 get_cpu_vendor(c); 1960 intel_unlock_cpuid_leafs(c); 1961 get_cpu_cap(c); 1962 1963 get_cpu_address_sizes(c); 1964 1965 get_model_name(c); /* Default name */ 1966 1967 /* 1968 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1969 * systems that run Linux at CPL > 0 may or may not have the 1970 * issue, but, even if they have the issue, there's absolutely 1971 * nothing we can do about it because we can't use the real IRET 1972 * instruction. 1973 * 1974 * NB: For the time being, only 32-bit kernels support 1975 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1976 * whether to apply espfix using paravirt hooks. If any 1977 * non-paravirt system ever shows up that does *not* have the 1978 * ESPFIX issue, we can change this. 1979 */ 1980 #ifdef CONFIG_X86_32 1981 set_cpu_bug(c, X86_BUG_ESPFIX); 1982 #endif 1983 } 1984 1985 /* 1986 * This does the hard work of actually picking apart the CPU stuff... 1987 */ 1988 static void identify_cpu(struct cpuinfo_x86 *c) 1989 { 1990 int i; 1991 1992 c->loops_per_jiffy = loops_per_jiffy; 1993 c->x86_cache_size = 0; 1994 c->x86_vendor = X86_VENDOR_UNKNOWN; 1995 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1996 c->x86_vendor_id[0] = '\0'; /* Unset */ 1997 c->x86_model_id[0] = '\0'; /* Unset */ 1998 #ifdef CONFIG_X86_64 1999 c->x86_clflush_size = 64; 2000 c->x86_phys_bits = 36; 2001 c->x86_virt_bits = 48; 2002 #else 2003 c->cpuid_level = -1; /* CPUID not detected */ 2004 c->x86_clflush_size = 32; 2005 c->x86_phys_bits = 32; 2006 c->x86_virt_bits = 32; 2007 #endif 2008 c->x86_cache_alignment = c->x86_clflush_size; 2009 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 2010 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 2011 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 2012 #endif 2013 2014 generic_identify(c); 2015 2016 cpu_parse_topology(c); 2017 2018 if (this_cpu->c_identify) 2019 this_cpu->c_identify(c); 2020 2021 /* Clear/Set all flags overridden by options, after probe */ 2022 apply_forced_caps(c); 2023 2024 /* 2025 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 2026 * Hygon will clear it in ->c_init() below. 2027 */ 2028 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 2029 2030 /* 2031 * Vendor-specific initialization. In this section we 2032 * canonicalize the feature flags, meaning if there are 2033 * features a certain CPU supports which CPUID doesn't 2034 * tell us, CPUID claiming incorrect flags, or other bugs, 2035 * we handle them here. 2036 * 2037 * At the end of this section, c->x86_capability better 2038 * indicate the features this CPU genuinely supports! 2039 */ 2040 if (this_cpu->c_init) 2041 this_cpu->c_init(c); 2042 2043 bus_lock_init(); 2044 2045 /* Disable the PN if appropriate */ 2046 squash_the_stupid_serial_number(c); 2047 2048 setup_smep(c); 2049 setup_smap(c); 2050 setup_umip(c); 2051 setup_lass(c); 2052 2053 /* Enable FSGSBASE instructions if available. */ 2054 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 2055 cr4_set_bits(X86_CR4_FSGSBASE); 2056 elf_hwcap2 |= HWCAP2_FSGSBASE; 2057 } 2058 2059 /* 2060 * The vendor-specific functions might have changed features. 2061 * Now we do "generic changes." 2062 */ 2063 2064 /* Filter out anything that depends on CPUID levels we don't have */ 2065 filter_cpuid_features(c, true); 2066 2067 /* Check for unmet dependencies based on the CPUID dependency table */ 2068 check_cpufeature_deps(c); 2069 2070 /* If the model name is still unset, do table lookup. */ 2071 if (!c->x86_model_id[0]) { 2072 const char *p; 2073 p = table_lookup_model(c); 2074 if (p) 2075 strcpy(c->x86_model_id, p); 2076 else 2077 /* Last resort... */ 2078 sprintf(c->x86_model_id, "%02x/%02x", 2079 c->x86, c->x86_model); 2080 } 2081 2082 x86_init_rdrand(c); 2083 setup_pku(c); 2084 setup_cet(c); 2085 2086 /* 2087 * Clear/Set all flags overridden by options, need do it 2088 * before following smp all cpus cap AND. 2089 */ 2090 apply_forced_caps(c); 2091 2092 /* 2093 * On SMP, boot_cpu_data holds the common feature set between 2094 * all CPUs; so make sure that we indicate which features are 2095 * common between the CPUs. The first time this routine gets 2096 * executed, c == &boot_cpu_data. 2097 */ 2098 if (c != &boot_cpu_data) { 2099 /* AND the already accumulated flags with these */ 2100 for (i = 0; i < NCAPINTS; i++) 2101 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 2102 2103 /* OR, i.e. replicate the bug flags */ 2104 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 2105 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 2106 } 2107 2108 ppin_init(c); 2109 2110 /* Init Machine Check Exception if available. */ 2111 mcheck_cpu_init(c); 2112 2113 numa_add_cpu(smp_processor_id()); 2114 } 2115 2116 /* 2117 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 2118 * on 32-bit kernels: 2119 */ 2120 #ifdef CONFIG_X86_32 2121 void enable_sep_cpu(void) 2122 { 2123 struct tss_struct *tss; 2124 int cpu; 2125 2126 if (!boot_cpu_has(X86_FEATURE_SEP)) 2127 return; 2128 2129 cpu = get_cpu(); 2130 tss = &per_cpu(cpu_tss_rw, cpu); 2131 2132 /* 2133 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 2134 * see the big comment in struct x86_hw_tss's definition. 2135 */ 2136 2137 tss->x86_tss.ss1 = __KERNEL_CS; 2138 wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1); 2139 wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 2140 wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32); 2141 2142 put_cpu(); 2143 } 2144 #endif 2145 2146 static __init void identify_boot_cpu(void) 2147 { 2148 identify_cpu(&boot_cpu_data); 2149 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 2150 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 2151 #ifdef CONFIG_X86_32 2152 enable_sep_cpu(); 2153 #endif 2154 cpu_detect_tlb(&boot_cpu_data); 2155 setup_cr_pinning(); 2156 2157 tsx_init(); 2158 tdx_init(); 2159 lkgs_init(); 2160 } 2161 2162 void identify_secondary_cpu(unsigned int cpu) 2163 { 2164 struct cpuinfo_x86 *c = &cpu_data(cpu); 2165 2166 /* Copy boot_cpu_data only on the first bringup */ 2167 if (!c->initialized) 2168 *c = boot_cpu_data; 2169 c->cpu_index = cpu; 2170 2171 identify_cpu(c); 2172 #ifdef CONFIG_X86_32 2173 enable_sep_cpu(); 2174 #endif 2175 x86_spec_ctrl_setup_ap(); 2176 update_srbds_msr(); 2177 if (boot_cpu_has_bug(X86_BUG_GDS)) 2178 update_gds_msr(); 2179 2180 tsx_ap_init(); 2181 c->initialized = true; 2182 } 2183 2184 void print_cpu_info(struct cpuinfo_x86 *c) 2185 { 2186 const char *vendor = NULL; 2187 2188 if (c->x86_vendor < X86_VENDOR_NUM) { 2189 vendor = this_cpu->c_vendor; 2190 } else { 2191 if (c->cpuid_level >= 0) 2192 vendor = c->x86_vendor_id; 2193 } 2194 2195 if (vendor && !strstr(c->x86_model_id, vendor)) 2196 pr_cont("%s ", vendor); 2197 2198 if (c->x86_model_id[0]) 2199 pr_cont("%s", c->x86_model_id); 2200 else 2201 pr_cont("%d86", c->x86); 2202 2203 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2204 2205 if (c->x86_stepping || c->cpuid_level >= 0) 2206 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2207 else 2208 pr_cont(")\n"); 2209 } 2210 2211 /* 2212 * clearcpuid= and setcpuid= were already parsed in cpu_parse_early_param(). 2213 * These dummy functions prevent them from becoming an environment variable for 2214 * init. 2215 */ 2216 2217 static __init int setup_clearcpuid(char *arg) 2218 { 2219 return 1; 2220 } 2221 __setup("clearcpuid=", setup_clearcpuid); 2222 2223 static __init int setup_setcpuid(char *arg) 2224 { 2225 return 1; 2226 } 2227 __setup("setcpuid=", setup_setcpuid); 2228 2229 DEFINE_PER_CPU_CACHE_HOT(struct task_struct *, current_task) = &init_task; 2230 EXPORT_PER_CPU_SYMBOL(current_task); 2231 EXPORT_PER_CPU_SYMBOL(const_current_task); 2232 2233 DEFINE_PER_CPU_CACHE_HOT(int, __preempt_count) = INIT_PREEMPT_COUNT; 2234 EXPORT_PER_CPU_SYMBOL(__preempt_count); 2235 2236 DEFINE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 2237 2238 #ifdef CONFIG_X86_64 2239 /* 2240 * Note: Do not make this dependant on CONFIG_MITIGATION_CALL_DEPTH_TRACKING 2241 * so that this space is reserved in the hot cache section even when the 2242 * mitigation is disabled. 2243 */ 2244 DEFINE_PER_CPU_CACHE_HOT(u64, __x86_call_depth); 2245 EXPORT_PER_CPU_SYMBOL(__x86_call_depth); 2246 2247 static void wrmsrq_cstar(unsigned long val) 2248 { 2249 /* 2250 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2251 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2252 * guest. Avoid the pointless write on all Intel CPUs. 2253 */ 2254 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2255 wrmsrq(MSR_CSTAR, val); 2256 } 2257 2258 static inline void idt_syscall_init(void) 2259 { 2260 wrmsrq(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2261 2262 if (ia32_enabled()) { 2263 wrmsrq_cstar((unsigned long)entry_SYSCALL_compat); 2264 /* 2265 * This only works on Intel CPUs. 2266 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2267 * This does not cause SYSENTER to jump to the wrong location, because 2268 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2269 */ 2270 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2271 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 2272 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2273 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2274 } else { 2275 wrmsrq_cstar((unsigned long)entry_SYSCALL32_ignore); 2276 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2277 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2278 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2279 } 2280 2281 /* 2282 * Flags to clear on syscall; clear as much as possible 2283 * to minimize user space-kernel interference. 2284 */ 2285 wrmsrq(MSR_SYSCALL_MASK, 2286 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2287 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2288 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2289 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2290 X86_EFLAGS_AC|X86_EFLAGS_ID); 2291 } 2292 2293 /* May not be marked __init: used by software suspend */ 2294 void syscall_init(void) 2295 { 2296 /* The default user and kernel segments */ 2297 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2298 2299 /* 2300 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and 2301 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED 2302 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit 2303 * instruction to return to ring 3 (both sysexit and sysret cause 2304 * #UD when FRED is enabled). 2305 */ 2306 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2307 idt_syscall_init(); 2308 } 2309 #endif /* CONFIG_X86_64 */ 2310 2311 #ifdef CONFIG_STACKPROTECTOR 2312 DEFINE_PER_CPU_CACHE_HOT(unsigned long, __stack_chk_guard); 2313 #ifndef CONFIG_SMP 2314 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2315 #endif 2316 #endif 2317 2318 static void initialize_debug_regs(void) 2319 { 2320 /* Control register first -- to make sure everything is disabled. */ 2321 set_debugreg(DR7_FIXED_1, 7); 2322 set_debugreg(DR6_RESERVED, 6); 2323 /* dr5 and dr4 don't exist */ 2324 set_debugreg(0, 3); 2325 set_debugreg(0, 2); 2326 set_debugreg(0, 1); 2327 set_debugreg(0, 0); 2328 } 2329 2330 #ifdef CONFIG_KGDB 2331 /* 2332 * Restore debug regs if using kgdbwait and you have a kernel debugger 2333 * connection established. 2334 */ 2335 static void dbg_restore_debug_regs(void) 2336 { 2337 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2338 arch_kgdb_ops.correct_hw_break(); 2339 } 2340 #else /* ! CONFIG_KGDB */ 2341 #define dbg_restore_debug_regs() 2342 #endif /* ! CONFIG_KGDB */ 2343 2344 static inline void setup_getcpu(int cpu) 2345 { 2346 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2347 struct desc_struct d = { }; 2348 2349 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2350 wrmsrq(MSR_TSC_AUX, cpudata); 2351 2352 /* Store CPU and node number in limit. */ 2353 d.limit0 = cpudata; 2354 d.limit1 = cpudata >> 16; 2355 2356 d.type = 5; /* RO data, expand down, accessed */ 2357 d.dpl = 3; /* Visible to user code */ 2358 d.s = 1; /* Not a system segment */ 2359 d.p = 1; /* Present */ 2360 d.d = 1; /* 32-bit */ 2361 2362 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2363 } 2364 2365 #ifdef CONFIG_X86_64 2366 static inline void tss_setup_ist(struct tss_struct *tss) 2367 { 2368 /* Set up the per-CPU TSS IST stacks */ 2369 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2370 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2371 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2372 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2373 /* Only mapped when SEV-ES is active */ 2374 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2375 } 2376 #else /* CONFIG_X86_64 */ 2377 static inline void tss_setup_ist(struct tss_struct *tss) { } 2378 #endif /* !CONFIG_X86_64 */ 2379 2380 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2381 { 2382 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2383 2384 #ifdef CONFIG_X86_IOPL_IOPERM 2385 tss->io_bitmap.prev_max = 0; 2386 tss->io_bitmap.prev_sequence = 0; 2387 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2388 /* 2389 * Invalidate the extra array entry past the end of the all 2390 * permission bitmap as required by the hardware. 2391 */ 2392 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2393 #endif 2394 } 2395 2396 /* 2397 * Setup everything needed to handle exceptions from the IDT, including the IST 2398 * exceptions which use paranoid_entry(). 2399 */ 2400 void cpu_init_exception_handling(bool boot_cpu) 2401 { 2402 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2403 int cpu = raw_smp_processor_id(); 2404 2405 /* paranoid_entry() gets the CPU number from the GDT */ 2406 setup_getcpu(cpu); 2407 2408 /* For IDT mode, IST vectors need to be set in TSS. */ 2409 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2410 tss_setup_ist(tss); 2411 tss_setup_io_bitmap(tss); 2412 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2413 2414 load_TR_desc(); 2415 2416 /* GHCB needs to be setup to handle #VC. */ 2417 setup_ghcb(); 2418 2419 if (cpu_feature_enabled(X86_FEATURE_FRED)) { 2420 /* The boot CPU has enabled FRED during early boot */ 2421 if (!boot_cpu) 2422 cpu_init_fred_exceptions(); 2423 2424 cpu_init_fred_rsps(); 2425 } else { 2426 load_current_idt(); 2427 } 2428 } 2429 2430 void __init cpu_init_replace_early_idt(void) 2431 { 2432 if (cpu_feature_enabled(X86_FEATURE_FRED)) 2433 cpu_init_fred_exceptions(); 2434 else 2435 idt_setup_early_pf(); 2436 } 2437 2438 /* 2439 * cpu_init() initializes state that is per-CPU. Some data is already 2440 * initialized (naturally) in the bootstrap process, such as the GDT. We 2441 * reload it nevertheless, this function acts as a 'CPU state barrier', 2442 * nothing should get across. 2443 */ 2444 void cpu_init(void) 2445 { 2446 struct task_struct *cur = current; 2447 int cpu = raw_smp_processor_id(); 2448 2449 #ifdef CONFIG_NUMA 2450 if (this_cpu_read(numa_node) == 0 && 2451 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2452 set_numa_node(early_cpu_to_node(cpu)); 2453 #endif 2454 pr_debug("Initializing CPU#%d\n", cpu); 2455 2456 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2457 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2458 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2459 2460 if (IS_ENABLED(CONFIG_X86_64)) { 2461 loadsegment(fs, 0); 2462 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2463 syscall_init(); 2464 2465 wrmsrq(MSR_FS_BASE, 0); 2466 wrmsrq(MSR_KERNEL_GS_BASE, 0); 2467 barrier(); 2468 2469 x2apic_setup(); 2470 2471 intel_posted_msi_init(); 2472 } 2473 2474 mmgrab(&init_mm); 2475 cur->active_mm = &init_mm; 2476 BUG_ON(cur->mm); 2477 initialize_tlbstate_and_flush(); 2478 enter_lazy_tlb(&init_mm, cur); 2479 2480 /* 2481 * sp0 points to the entry trampoline stack regardless of what task 2482 * is running. 2483 */ 2484 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2485 2486 load_mm_ldt(&init_mm); 2487 2488 initialize_debug_regs(); 2489 dbg_restore_debug_regs(); 2490 2491 doublefault_init_cpu_tss(); 2492 2493 if (is_uv_system()) 2494 uv_cpu_init(); 2495 2496 load_fixmap_gdt(cpu); 2497 } 2498 2499 #ifdef CONFIG_MICROCODE_LATE_LOADING 2500 /** 2501 * store_cpu_caps() - Store a snapshot of CPU capabilities 2502 * @curr_info: Pointer where to store it 2503 * 2504 * Returns: None 2505 */ 2506 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2507 { 2508 /* Reload CPUID max function as it might've changed. */ 2509 curr_info->cpuid_level = cpuid_eax(0); 2510 2511 /* Copy all capability leafs and pick up the synthetic ones. */ 2512 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2513 sizeof(curr_info->x86_capability)); 2514 2515 /* Get the hardware CPUID leafs */ 2516 get_cpu_cap(curr_info); 2517 } 2518 2519 /** 2520 * microcode_check() - Check if any CPU capabilities changed after an update. 2521 * @prev_info: CPU capabilities stored before an update. 2522 * 2523 * The microcode loader calls this upon late microcode load to recheck features, 2524 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2525 * 2526 * Return: None 2527 */ 2528 void microcode_check(struct cpuinfo_x86 *prev_info) 2529 { 2530 struct cpuinfo_x86 curr_info; 2531 2532 perf_check_microcode(); 2533 2534 amd_check_microcode(); 2535 2536 store_cpu_caps(&curr_info); 2537 2538 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2539 sizeof(prev_info->x86_capability))) 2540 return; 2541 2542 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2543 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2544 } 2545 #endif 2546 2547 /* 2548 * Invoked from core CPU hotplug code after hotplug operations 2549 */ 2550 void arch_smt_update(void) 2551 { 2552 /* Handle the speculative execution misfeatures */ 2553 cpu_bugs_smt_update(); 2554 /* Check whether IPI broadcasting can be enabled */ 2555 apic_smt_update(); 2556 } 2557 2558 void __init arch_cpu_finalize_init(void) 2559 { 2560 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 2561 2562 identify_boot_cpu(); 2563 2564 select_idle_routine(); 2565 2566 /* 2567 * identify_boot_cpu() initialized SMT support information, let the 2568 * core code know. 2569 */ 2570 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core); 2571 2572 if (!IS_ENABLED(CONFIG_SMP)) { 2573 pr_info("CPU: "); 2574 print_cpu_info(&boot_cpu_data); 2575 } 2576 2577 cpu_select_mitigations(); 2578 2579 arch_smt_update(); 2580 2581 if (IS_ENABLED(CONFIG_X86_32)) { 2582 /* 2583 * Check whether this is a real i386 which is not longer 2584 * supported and fixup the utsname. 2585 */ 2586 if (boot_cpu_data.x86 < 4) 2587 panic("Kernel requires i486+ for 'invlpg' and other features"); 2588 2589 init_utsname()->machine[1] = 2590 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2591 } 2592 2593 /* 2594 * Must be before alternatives because it might set or clear 2595 * feature bits. 2596 */ 2597 fpu__init_system(); 2598 fpu__init_cpu(); 2599 2600 /* 2601 * This needs to follow the FPU initializtion, since EFI depends on it. 2602 */ 2603 if (efi_enabled(EFI_RUNTIME_SERVICES)) 2604 efi_enter_virtual_mode(); 2605 2606 /* 2607 * Ensure that access to the per CPU representation has the initial 2608 * boot CPU configuration. 2609 */ 2610 *c = boot_cpu_data; 2611 c->initialized = true; 2612 2613 alternative_instructions(); 2614 2615 if (IS_ENABLED(CONFIG_X86_64)) { 2616 USER_PTR_MAX = TASK_SIZE_MAX; 2617 2618 /* 2619 * Enable this when LAM is gated on LASS support 2620 if (cpu_feature_enabled(X86_FEATURE_LAM)) 2621 USER_PTR_MAX = (1ul << 63) - PAGE_SIZE; 2622 */ 2623 runtime_const_init(ptr, USER_PTR_MAX); 2624 2625 /* 2626 * Make sure the first 2MB area is not mapped by huge pages 2627 * There are typically fixed size MTRRs in there and overlapping 2628 * MTRRs into large pages causes slow downs. 2629 * 2630 * Right now we don't do that with gbpages because there seems 2631 * very little benefit for that case. 2632 */ 2633 if (!direct_gbpages) 2634 set_memory_4k((unsigned long)__va(0), 1); 2635 } else { 2636 fpu__init_check_bugs(); 2637 } 2638 2639 /* 2640 * This needs to be called before any devices perform DMA 2641 * operations that might use the SWIOTLB bounce buffers. It will 2642 * mark the bounce buffers as decrypted so that their usage will 2643 * not cause "plain-text" data to be decrypted when accessed. It 2644 * must be called after late_time_init() so that Hyper-V x86/x64 2645 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2646 */ 2647 mem_encrypt_init(); 2648 } 2649