1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_event.h> 17 #include <asm/mmu_context.h> 18 #include <asm/archrandom.h> 19 #include <asm/hypervisor.h> 20 #include <asm/processor.h> 21 #include <asm/debugreg.h> 22 #include <asm/sections.h> 23 #include <linux/topology.h> 24 #include <linux/cpumask.h> 25 #include <asm/pgtable.h> 26 #include <linux/atomic.h> 27 #include <asm/proto.h> 28 #include <asm/setup.h> 29 #include <asm/apic.h> 30 #include <asm/desc.h> 31 #include <asm/i387.h> 32 #include <asm/fpu-internal.h> 33 #include <asm/mtrr.h> 34 #include <linux/numa.h> 35 #include <asm/asm.h> 36 #include <asm/cpu.h> 37 #include <asm/mce.h> 38 #include <asm/msr.h> 39 #include <asm/pat.h> 40 41 #ifdef CONFIG_X86_LOCAL_APIC 42 #include <asm/uv/uv.h> 43 #endif 44 45 #include "cpu.h" 46 47 /* all of these masks are initialized in setup_cpu_local_masks() */ 48 cpumask_var_t cpu_initialized_mask; 49 cpumask_var_t cpu_callout_mask; 50 cpumask_var_t cpu_callin_mask; 51 52 /* representing cpus for which sibling maps can be computed */ 53 cpumask_var_t cpu_sibling_setup_mask; 54 55 /* correctly size the local cpu masks */ 56 void __init setup_cpu_local_masks(void) 57 { 58 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 59 alloc_bootmem_cpumask_var(&cpu_callin_mask); 60 alloc_bootmem_cpumask_var(&cpu_callout_mask); 61 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 62 } 63 64 static void __cpuinit default_init(struct cpuinfo_x86 *c) 65 { 66 #ifdef CONFIG_X86_64 67 cpu_detect_cache_sizes(c); 68 #else 69 /* Not much we can do here... */ 70 /* Check if at least it has cpuid */ 71 if (c->cpuid_level == -1) { 72 /* No cpuid. It must be an ancient CPU */ 73 if (c->x86 == 4) 74 strcpy(c->x86_model_id, "486"); 75 else if (c->x86 == 3) 76 strcpy(c->x86_model_id, "386"); 77 } 78 #endif 79 } 80 81 static const struct cpu_dev __cpuinitconst default_cpu = { 82 .c_init = default_init, 83 .c_vendor = "Unknown", 84 .c_x86_vendor = X86_VENDOR_UNKNOWN, 85 }; 86 87 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; 88 89 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 90 #ifdef CONFIG_X86_64 91 /* 92 * We need valid kernel segments for data and code in long mode too 93 * IRET will check the segment types kkeil 2000/10/28 94 * Also sysret mandates a special GDT layout 95 * 96 * TLS descriptors are currently at a different place compared to i386. 97 * Hopefully nobody expects them at a fixed place (Wine?) 98 */ 99 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 100 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 101 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 102 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 103 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 104 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 105 #else 106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 110 /* 111 * Segments used for calling PnP BIOS have byte granularity. 112 * They code segments and data segments have fixed 64k limits, 113 * the transfer segment sizes are set at run time. 114 */ 115 /* 32-bit code */ 116 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 117 /* 16-bit code */ 118 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 119 /* 16-bit data */ 120 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 121 /* 16-bit data */ 122 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 123 /* 16-bit data */ 124 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 125 /* 126 * The APM segments have byte granularity and their bases 127 * are set at run time. All have 64k limits. 128 */ 129 /* 32-bit code */ 130 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 131 /* 16-bit code */ 132 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 133 /* data */ 134 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 135 136 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 137 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 138 GDT_STACK_CANARY_INIT 139 #endif 140 } }; 141 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 142 143 static int __init x86_xsave_setup(char *s) 144 { 145 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 146 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 147 setup_clear_cpu_cap(X86_FEATURE_AVX); 148 setup_clear_cpu_cap(X86_FEATURE_AVX2); 149 return 1; 150 } 151 __setup("noxsave", x86_xsave_setup); 152 153 static int __init x86_xsaveopt_setup(char *s) 154 { 155 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 156 return 1; 157 } 158 __setup("noxsaveopt", x86_xsaveopt_setup); 159 160 #ifdef CONFIG_X86_32 161 static int cachesize_override __cpuinitdata = -1; 162 static int disable_x86_serial_nr __cpuinitdata = 1; 163 164 static int __init cachesize_setup(char *str) 165 { 166 get_option(&str, &cachesize_override); 167 return 1; 168 } 169 __setup("cachesize=", cachesize_setup); 170 171 static int __init x86_fxsr_setup(char *s) 172 { 173 setup_clear_cpu_cap(X86_FEATURE_FXSR); 174 setup_clear_cpu_cap(X86_FEATURE_XMM); 175 return 1; 176 } 177 __setup("nofxsr", x86_fxsr_setup); 178 179 static int __init x86_sep_setup(char *s) 180 { 181 setup_clear_cpu_cap(X86_FEATURE_SEP); 182 return 1; 183 } 184 __setup("nosep", x86_sep_setup); 185 186 /* Standard macro to see if a specific flag is changeable */ 187 static inline int flag_is_changeable_p(u32 flag) 188 { 189 u32 f1, f2; 190 191 /* 192 * Cyrix and IDT cpus allow disabling of CPUID 193 * so the code below may return different results 194 * when it is executed before and after enabling 195 * the CPUID. Add "volatile" to not allow gcc to 196 * optimize the subsequent calls to this function. 197 */ 198 asm volatile ("pushfl \n\t" 199 "pushfl \n\t" 200 "popl %0 \n\t" 201 "movl %0, %1 \n\t" 202 "xorl %2, %0 \n\t" 203 "pushl %0 \n\t" 204 "popfl \n\t" 205 "pushfl \n\t" 206 "popl %0 \n\t" 207 "popfl \n\t" 208 209 : "=&r" (f1), "=&r" (f2) 210 : "ir" (flag)); 211 212 return ((f1^f2) & flag) != 0; 213 } 214 215 /* Probe for the CPUID instruction */ 216 static int __cpuinit have_cpuid_p(void) 217 { 218 return flag_is_changeable_p(X86_EFLAGS_ID); 219 } 220 221 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 222 { 223 unsigned long lo, hi; 224 225 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 226 return; 227 228 /* Disable processor serial number: */ 229 230 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 231 lo |= 0x200000; 232 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 233 234 printk(KERN_NOTICE "CPU serial number disabled.\n"); 235 clear_cpu_cap(c, X86_FEATURE_PN); 236 237 /* Disabling the serial number may affect the cpuid level */ 238 c->cpuid_level = cpuid_eax(0); 239 } 240 241 static int __init x86_serial_nr_setup(char *s) 242 { 243 disable_x86_serial_nr = 0; 244 return 1; 245 } 246 __setup("serialnumber", x86_serial_nr_setup); 247 #else 248 static inline int flag_is_changeable_p(u32 flag) 249 { 250 return 1; 251 } 252 /* Probe for the CPUID instruction */ 253 static inline int have_cpuid_p(void) 254 { 255 return 1; 256 } 257 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 258 { 259 } 260 #endif 261 262 static __init int setup_disable_smep(char *arg) 263 { 264 setup_clear_cpu_cap(X86_FEATURE_SMEP); 265 return 1; 266 } 267 __setup("nosmep", setup_disable_smep); 268 269 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 270 { 271 if (cpu_has(c, X86_FEATURE_SMEP)) 272 set_in_cr4(X86_CR4_SMEP); 273 } 274 275 static __init int setup_disable_smap(char *arg) 276 { 277 setup_clear_cpu_cap(X86_FEATURE_SMAP); 278 return 1; 279 } 280 __setup("nosmap", setup_disable_smap); 281 282 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 283 { 284 unsigned long eflags; 285 286 /* This should have been cleared long ago */ 287 raw_local_save_flags(eflags); 288 BUG_ON(eflags & X86_EFLAGS_AC); 289 290 if (cpu_has(c, X86_FEATURE_SMAP)) 291 set_in_cr4(X86_CR4_SMAP); 292 } 293 294 /* 295 * Some CPU features depend on higher CPUID levels, which may not always 296 * be available due to CPUID level capping or broken virtualization 297 * software. Add those features to this table to auto-disable them. 298 */ 299 struct cpuid_dependent_feature { 300 u32 feature; 301 u32 level; 302 }; 303 304 static const struct cpuid_dependent_feature __cpuinitconst 305 cpuid_dependent_features[] = { 306 { X86_FEATURE_MWAIT, 0x00000005 }, 307 { X86_FEATURE_DCA, 0x00000009 }, 308 { X86_FEATURE_XSAVE, 0x0000000d }, 309 { 0, 0 } 310 }; 311 312 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 313 { 314 const struct cpuid_dependent_feature *df; 315 316 for (df = cpuid_dependent_features; df->feature; df++) { 317 318 if (!cpu_has(c, df->feature)) 319 continue; 320 /* 321 * Note: cpuid_level is set to -1 if unavailable, but 322 * extended_extended_level is set to 0 if unavailable 323 * and the legitimate extended levels are all negative 324 * when signed; hence the weird messing around with 325 * signs here... 326 */ 327 if (!((s32)df->level < 0 ? 328 (u32)df->level > (u32)c->extended_cpuid_level : 329 (s32)df->level > (s32)c->cpuid_level)) 330 continue; 331 332 clear_cpu_cap(c, df->feature); 333 if (!warn) 334 continue; 335 336 printk(KERN_WARNING 337 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 338 x86_cap_flags[df->feature], df->level); 339 } 340 } 341 342 /* 343 * Naming convention should be: <Name> [(<Codename>)] 344 * This table only is used unless init_<vendor>() below doesn't set it; 345 * in particular, if CPUID levels 0x80000002..4 are supported, this 346 * isn't used 347 */ 348 349 /* Look up CPU names by table lookup. */ 350 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 351 { 352 const struct cpu_model_info *info; 353 354 if (c->x86_model >= 16) 355 return NULL; /* Range check */ 356 357 if (!this_cpu) 358 return NULL; 359 360 info = this_cpu->c_models; 361 362 while (info && info->family) { 363 if (info->family == c->x86) 364 return info->model_names[c->x86_model]; 365 info++; 366 } 367 return NULL; /* Not found */ 368 } 369 370 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; 371 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; 372 373 void load_percpu_segment(int cpu) 374 { 375 #ifdef CONFIG_X86_32 376 loadsegment(fs, __KERNEL_PERCPU); 377 #else 378 loadsegment(gs, 0); 379 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 380 #endif 381 load_stack_canary_segment(); 382 } 383 384 /* 385 * Current gdt points %fs at the "master" per-cpu area: after this, 386 * it's on the real one. 387 */ 388 void switch_to_new_gdt(int cpu) 389 { 390 struct desc_ptr gdt_descr; 391 392 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 393 gdt_descr.size = GDT_SIZE - 1; 394 load_gdt(&gdt_descr); 395 /* Reload the per-cpu base */ 396 397 load_percpu_segment(cpu); 398 } 399 400 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 401 402 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 403 { 404 unsigned int *v; 405 char *p, *q; 406 407 if (c->extended_cpuid_level < 0x80000004) 408 return; 409 410 v = (unsigned int *)c->x86_model_id; 411 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 412 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 413 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 414 c->x86_model_id[48] = 0; 415 416 /* 417 * Intel chips right-justify this string for some dumb reason; 418 * undo that brain damage: 419 */ 420 p = q = &c->x86_model_id[0]; 421 while (*p == ' ') 422 p++; 423 if (p != q) { 424 while (*p) 425 *q++ = *p++; 426 while (q <= &c->x86_model_id[48]) 427 *q++ = '\0'; /* Zero-pad the rest */ 428 } 429 } 430 431 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 432 { 433 unsigned int n, dummy, ebx, ecx, edx, l2size; 434 435 n = c->extended_cpuid_level; 436 437 if (n >= 0x80000005) { 438 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 439 c->x86_cache_size = (ecx>>24) + (edx>>24); 440 #ifdef CONFIG_X86_64 441 /* On K8 L1 TLB is inclusive, so don't count it */ 442 c->x86_tlbsize = 0; 443 #endif 444 } 445 446 if (n < 0x80000006) /* Some chips just has a large L1. */ 447 return; 448 449 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 450 l2size = ecx >> 16; 451 452 #ifdef CONFIG_X86_64 453 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 454 #else 455 /* do processor-specific cache resizing */ 456 if (this_cpu->c_size_cache) 457 l2size = this_cpu->c_size_cache(c, l2size); 458 459 /* Allow user to override all this if necessary. */ 460 if (cachesize_override != -1) 461 l2size = cachesize_override; 462 463 if (l2size == 0) 464 return; /* Again, no L2 cache is possible */ 465 #endif 466 467 c->x86_cache_size = l2size; 468 } 469 470 u16 __read_mostly tlb_lli_4k[NR_INFO]; 471 u16 __read_mostly tlb_lli_2m[NR_INFO]; 472 u16 __read_mostly tlb_lli_4m[NR_INFO]; 473 u16 __read_mostly tlb_lld_4k[NR_INFO]; 474 u16 __read_mostly tlb_lld_2m[NR_INFO]; 475 u16 __read_mostly tlb_lld_4m[NR_INFO]; 476 477 /* 478 * tlb_flushall_shift shows the balance point in replacing cr3 write 479 * with multiple 'invlpg'. It will do this replacement when 480 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. 481 * If tlb_flushall_shift is -1, means the replacement will be disabled. 482 */ 483 s8 __read_mostly tlb_flushall_shift = -1; 484 485 void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c) 486 { 487 if (this_cpu->c_detect_tlb) 488 this_cpu->c_detect_tlb(c); 489 490 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 491 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ 492 "tlb_flushall_shift: %d\n", 493 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 494 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], 495 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], 496 tlb_flushall_shift); 497 } 498 499 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 500 { 501 #ifdef CONFIG_X86_HT 502 u32 eax, ebx, ecx, edx; 503 int index_msb, core_bits; 504 static bool printed; 505 506 if (!cpu_has(c, X86_FEATURE_HT)) 507 return; 508 509 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 510 goto out; 511 512 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 513 return; 514 515 cpuid(1, &eax, &ebx, &ecx, &edx); 516 517 smp_num_siblings = (ebx & 0xff0000) >> 16; 518 519 if (smp_num_siblings == 1) { 520 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 521 goto out; 522 } 523 524 if (smp_num_siblings <= 1) 525 goto out; 526 527 index_msb = get_count_order(smp_num_siblings); 528 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 529 530 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 531 532 index_msb = get_count_order(smp_num_siblings); 533 534 core_bits = get_count_order(c->x86_max_cores); 535 536 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 537 ((1 << core_bits) - 1); 538 539 out: 540 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 541 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 542 c->phys_proc_id); 543 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 544 c->cpu_core_id); 545 printed = 1; 546 } 547 #endif 548 } 549 550 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 551 { 552 char *v = c->x86_vendor_id; 553 int i; 554 555 for (i = 0; i < X86_VENDOR_NUM; i++) { 556 if (!cpu_devs[i]) 557 break; 558 559 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 560 (cpu_devs[i]->c_ident[1] && 561 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 562 563 this_cpu = cpu_devs[i]; 564 c->x86_vendor = this_cpu->c_x86_vendor; 565 return; 566 } 567 } 568 569 printk_once(KERN_ERR 570 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 571 "CPU: Your system may be unstable.\n", v); 572 573 c->x86_vendor = X86_VENDOR_UNKNOWN; 574 this_cpu = &default_cpu; 575 } 576 577 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 578 { 579 /* Get vendor name */ 580 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 581 (unsigned int *)&c->x86_vendor_id[0], 582 (unsigned int *)&c->x86_vendor_id[8], 583 (unsigned int *)&c->x86_vendor_id[4]); 584 585 c->x86 = 4; 586 /* Intel-defined flags: level 0x00000001 */ 587 if (c->cpuid_level >= 0x00000001) { 588 u32 junk, tfms, cap0, misc; 589 590 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 591 c->x86 = (tfms >> 8) & 0xf; 592 c->x86_model = (tfms >> 4) & 0xf; 593 c->x86_mask = tfms & 0xf; 594 595 if (c->x86 == 0xf) 596 c->x86 += (tfms >> 20) & 0xff; 597 if (c->x86 >= 0x6) 598 c->x86_model += ((tfms >> 16) & 0xf) << 4; 599 600 if (cap0 & (1<<19)) { 601 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 602 c->x86_cache_alignment = c->x86_clflush_size; 603 } 604 } 605 } 606 607 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 608 { 609 u32 tfms, xlvl; 610 u32 ebx; 611 612 /* Intel-defined flags: level 0x00000001 */ 613 if (c->cpuid_level >= 0x00000001) { 614 u32 capability, excap; 615 616 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 617 c->x86_capability[0] = capability; 618 c->x86_capability[4] = excap; 619 } 620 621 /* Additional Intel-defined flags: level 0x00000007 */ 622 if (c->cpuid_level >= 0x00000007) { 623 u32 eax, ebx, ecx, edx; 624 625 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 626 627 c->x86_capability[9] = ebx; 628 } 629 630 /* AMD-defined flags: level 0x80000001 */ 631 xlvl = cpuid_eax(0x80000000); 632 c->extended_cpuid_level = xlvl; 633 634 if ((xlvl & 0xffff0000) == 0x80000000) { 635 if (xlvl >= 0x80000001) { 636 c->x86_capability[1] = cpuid_edx(0x80000001); 637 c->x86_capability[6] = cpuid_ecx(0x80000001); 638 } 639 } 640 641 if (c->extended_cpuid_level >= 0x80000008) { 642 u32 eax = cpuid_eax(0x80000008); 643 644 c->x86_virt_bits = (eax >> 8) & 0xff; 645 c->x86_phys_bits = eax & 0xff; 646 } 647 #ifdef CONFIG_X86_32 648 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 649 c->x86_phys_bits = 36; 650 #endif 651 652 if (c->extended_cpuid_level >= 0x80000007) 653 c->x86_power = cpuid_edx(0x80000007); 654 655 init_scattered_cpuid_features(c); 656 } 657 658 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 659 { 660 #ifdef CONFIG_X86_32 661 int i; 662 663 /* 664 * First of all, decide if this is a 486 or higher 665 * It's a 486 if we can modify the AC flag 666 */ 667 if (flag_is_changeable_p(X86_EFLAGS_AC)) 668 c->x86 = 4; 669 else 670 c->x86 = 3; 671 672 for (i = 0; i < X86_VENDOR_NUM; i++) 673 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 674 c->x86_vendor_id[0] = 0; 675 cpu_devs[i]->c_identify(c); 676 if (c->x86_vendor_id[0]) { 677 get_cpu_vendor(c); 678 break; 679 } 680 } 681 #endif 682 } 683 684 /* 685 * Do minimum CPU detection early. 686 * Fields really needed: vendor, cpuid_level, family, model, mask, 687 * cache alignment. 688 * The others are not touched to avoid unwanted side effects. 689 * 690 * WARNING: this function is only called on the BP. Don't add code here 691 * that is supposed to run on all CPUs. 692 */ 693 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 694 { 695 #ifdef CONFIG_X86_64 696 c->x86_clflush_size = 64; 697 c->x86_phys_bits = 36; 698 c->x86_virt_bits = 48; 699 #else 700 c->x86_clflush_size = 32; 701 c->x86_phys_bits = 32; 702 c->x86_virt_bits = 32; 703 #endif 704 c->x86_cache_alignment = c->x86_clflush_size; 705 706 memset(&c->x86_capability, 0, sizeof c->x86_capability); 707 c->extended_cpuid_level = 0; 708 709 if (!have_cpuid_p()) 710 identify_cpu_without_cpuid(c); 711 712 /* cyrix could have cpuid enabled via c_identify()*/ 713 if (!have_cpuid_p()) 714 return; 715 716 cpu_detect(c); 717 718 get_cpu_vendor(c); 719 720 get_cpu_cap(c); 721 722 if (this_cpu->c_early_init) 723 this_cpu->c_early_init(c); 724 725 c->cpu_index = 0; 726 filter_cpuid_features(c, false); 727 728 if (this_cpu->c_bsp_init) 729 this_cpu->c_bsp_init(c); 730 } 731 732 void __init early_cpu_init(void) 733 { 734 const struct cpu_dev *const *cdev; 735 int count = 0; 736 737 #ifdef CONFIG_PROCESSOR_SELECT 738 printk(KERN_INFO "KERNEL supported cpus:\n"); 739 #endif 740 741 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 742 const struct cpu_dev *cpudev = *cdev; 743 744 if (count >= X86_VENDOR_NUM) 745 break; 746 cpu_devs[count] = cpudev; 747 count++; 748 749 #ifdef CONFIG_PROCESSOR_SELECT 750 { 751 unsigned int j; 752 753 for (j = 0; j < 2; j++) { 754 if (!cpudev->c_ident[j]) 755 continue; 756 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 757 cpudev->c_ident[j]); 758 } 759 } 760 #endif 761 } 762 early_identify_cpu(&boot_cpu_data); 763 } 764 765 /* 766 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 767 * unfortunately, that's not true in practice because of early VIA 768 * chips and (more importantly) broken virtualizers that are not easy 769 * to detect. In the latter case it doesn't even *fail* reliably, so 770 * probing for it doesn't even work. Disable it completely on 32-bit 771 * unless we can find a reliable way to detect all the broken cases. 772 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 773 */ 774 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 775 { 776 #ifdef CONFIG_X86_32 777 clear_cpu_cap(c, X86_FEATURE_NOPL); 778 #else 779 set_cpu_cap(c, X86_FEATURE_NOPL); 780 #endif 781 } 782 783 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 784 { 785 c->extended_cpuid_level = 0; 786 787 if (!have_cpuid_p()) 788 identify_cpu_without_cpuid(c); 789 790 /* cyrix could have cpuid enabled via c_identify()*/ 791 if (!have_cpuid_p()) 792 return; 793 794 cpu_detect(c); 795 796 get_cpu_vendor(c); 797 798 get_cpu_cap(c); 799 800 if (c->cpuid_level >= 0x00000001) { 801 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 802 #ifdef CONFIG_X86_32 803 # ifdef CONFIG_X86_HT 804 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 805 # else 806 c->apicid = c->initial_apicid; 807 # endif 808 #endif 809 c->phys_proc_id = c->initial_apicid; 810 } 811 812 get_model_name(c); /* Default name */ 813 814 detect_nopl(c); 815 } 816 817 /* 818 * This does the hard work of actually picking apart the CPU stuff... 819 */ 820 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 821 { 822 int i; 823 824 c->loops_per_jiffy = loops_per_jiffy; 825 c->x86_cache_size = -1; 826 c->x86_vendor = X86_VENDOR_UNKNOWN; 827 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 828 c->x86_vendor_id[0] = '\0'; /* Unset */ 829 c->x86_model_id[0] = '\0'; /* Unset */ 830 c->x86_max_cores = 1; 831 c->x86_coreid_bits = 0; 832 #ifdef CONFIG_X86_64 833 c->x86_clflush_size = 64; 834 c->x86_phys_bits = 36; 835 c->x86_virt_bits = 48; 836 #else 837 c->cpuid_level = -1; /* CPUID not detected */ 838 c->x86_clflush_size = 32; 839 c->x86_phys_bits = 32; 840 c->x86_virt_bits = 32; 841 #endif 842 c->x86_cache_alignment = c->x86_clflush_size; 843 memset(&c->x86_capability, 0, sizeof c->x86_capability); 844 845 generic_identify(c); 846 847 if (this_cpu->c_identify) 848 this_cpu->c_identify(c); 849 850 /* Clear/Set all flags overriden by options, after probe */ 851 for (i = 0; i < NCAPINTS; i++) { 852 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 853 c->x86_capability[i] |= cpu_caps_set[i]; 854 } 855 856 #ifdef CONFIG_X86_64 857 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 858 #endif 859 860 /* 861 * Vendor-specific initialization. In this section we 862 * canonicalize the feature flags, meaning if there are 863 * features a certain CPU supports which CPUID doesn't 864 * tell us, CPUID claiming incorrect flags, or other bugs, 865 * we handle them here. 866 * 867 * At the end of this section, c->x86_capability better 868 * indicate the features this CPU genuinely supports! 869 */ 870 if (this_cpu->c_init) 871 this_cpu->c_init(c); 872 873 /* Disable the PN if appropriate */ 874 squash_the_stupid_serial_number(c); 875 876 /* Set up SMEP/SMAP */ 877 setup_smep(c); 878 setup_smap(c); 879 880 /* 881 * The vendor-specific functions might have changed features. 882 * Now we do "generic changes." 883 */ 884 885 /* Filter out anything that depends on CPUID levels we don't have */ 886 filter_cpuid_features(c, true); 887 888 /* If the model name is still unset, do table lookup. */ 889 if (!c->x86_model_id[0]) { 890 const char *p; 891 p = table_lookup_model(c); 892 if (p) 893 strcpy(c->x86_model_id, p); 894 else 895 /* Last resort... */ 896 sprintf(c->x86_model_id, "%02x/%02x", 897 c->x86, c->x86_model); 898 } 899 900 #ifdef CONFIG_X86_64 901 detect_ht(c); 902 #endif 903 904 init_hypervisor(c); 905 x86_init_rdrand(c); 906 907 /* 908 * Clear/Set all flags overriden by options, need do it 909 * before following smp all cpus cap AND. 910 */ 911 for (i = 0; i < NCAPINTS; i++) { 912 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 913 c->x86_capability[i] |= cpu_caps_set[i]; 914 } 915 916 /* 917 * On SMP, boot_cpu_data holds the common feature set between 918 * all CPUs; so make sure that we indicate which features are 919 * common between the CPUs. The first time this routine gets 920 * executed, c == &boot_cpu_data. 921 */ 922 if (c != &boot_cpu_data) { 923 /* AND the already accumulated flags with these */ 924 for (i = 0; i < NCAPINTS; i++) 925 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 926 } 927 928 /* Init Machine Check Exception if available. */ 929 mcheck_cpu_init(c); 930 931 select_idle_routine(c); 932 933 #ifdef CONFIG_NUMA 934 numa_add_cpu(smp_processor_id()); 935 #endif 936 } 937 938 #ifdef CONFIG_X86_64 939 static void vgetcpu_set_mode(void) 940 { 941 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 942 vgetcpu_mode = VGETCPU_RDTSCP; 943 else 944 vgetcpu_mode = VGETCPU_LSL; 945 } 946 #endif 947 948 void __init identify_boot_cpu(void) 949 { 950 identify_cpu(&boot_cpu_data); 951 init_amd_e400_c1e_mask(); 952 #ifdef CONFIG_X86_32 953 sysenter_setup(); 954 enable_sep_cpu(); 955 #else 956 vgetcpu_set_mode(); 957 #endif 958 cpu_detect_tlb(&boot_cpu_data); 959 } 960 961 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 962 { 963 BUG_ON(c == &boot_cpu_data); 964 identify_cpu(c); 965 #ifdef CONFIG_X86_32 966 enable_sep_cpu(); 967 #endif 968 mtrr_ap_init(); 969 } 970 971 struct msr_range { 972 unsigned min; 973 unsigned max; 974 }; 975 976 static const struct msr_range msr_range_array[] __cpuinitconst = { 977 { 0x00000000, 0x00000418}, 978 { 0xc0000000, 0xc000040b}, 979 { 0xc0010000, 0xc0010142}, 980 { 0xc0011000, 0xc001103b}, 981 }; 982 983 static void __cpuinit __print_cpu_msr(void) 984 { 985 unsigned index_min, index_max; 986 unsigned index; 987 u64 val; 988 int i; 989 990 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 991 index_min = msr_range_array[i].min; 992 index_max = msr_range_array[i].max; 993 994 for (index = index_min; index < index_max; index++) { 995 if (rdmsrl_safe(index, &val)) 996 continue; 997 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 998 } 999 } 1000 } 1001 1002 static int show_msr __cpuinitdata; 1003 1004 static __init int setup_show_msr(char *arg) 1005 { 1006 int num; 1007 1008 get_option(&arg, &num); 1009 1010 if (num > 0) 1011 show_msr = num; 1012 return 1; 1013 } 1014 __setup("show_msr=", setup_show_msr); 1015 1016 static __init int setup_noclflush(char *arg) 1017 { 1018 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 1019 return 1; 1020 } 1021 __setup("noclflush", setup_noclflush); 1022 1023 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 1024 { 1025 const char *vendor = NULL; 1026 1027 if (c->x86_vendor < X86_VENDOR_NUM) { 1028 vendor = this_cpu->c_vendor; 1029 } else { 1030 if (c->cpuid_level >= 0) 1031 vendor = c->x86_vendor_id; 1032 } 1033 1034 if (vendor && !strstr(c->x86_model_id, vendor)) 1035 printk(KERN_CONT "%s ", vendor); 1036 1037 if (c->x86_model_id[0]) 1038 printk(KERN_CONT "%s", strim(c->x86_model_id)); 1039 else 1040 printk(KERN_CONT "%d86", c->x86); 1041 1042 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); 1043 1044 if (c->x86_mask || c->cpuid_level >= 0) 1045 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); 1046 else 1047 printk(KERN_CONT ")\n"); 1048 1049 print_cpu_msr(c); 1050 } 1051 1052 void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c) 1053 { 1054 if (c->cpu_index < show_msr) 1055 __print_cpu_msr(); 1056 } 1057 1058 static __init int setup_disablecpuid(char *arg) 1059 { 1060 int bit; 1061 1062 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1063 setup_clear_cpu_cap(bit); 1064 else 1065 return 0; 1066 1067 return 1; 1068 } 1069 __setup("clearcpuid=", setup_disablecpuid); 1070 1071 #ifdef CONFIG_X86_64 1072 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1073 struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1, 1074 (unsigned long) nmi_idt_table }; 1075 1076 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1077 irq_stack_union) __aligned(PAGE_SIZE); 1078 1079 /* 1080 * The following four percpu variables are hot. Align current_task to 1081 * cacheline size such that all four fall in the same cacheline. 1082 */ 1083 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1084 &init_task; 1085 EXPORT_PER_CPU_SYMBOL(current_task); 1086 1087 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1088 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1089 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1090 1091 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1092 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1093 1094 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 1095 1096 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1097 1098 /* 1099 * Special IST stacks which the CPU switches to when it calls 1100 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1101 * limit), all of them are 4K, except the debug stack which 1102 * is 8K. 1103 */ 1104 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1105 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1106 [DEBUG_STACK - 1] = DEBUG_STKSZ 1107 }; 1108 1109 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1110 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1111 1112 /* May not be marked __init: used by software suspend */ 1113 void syscall_init(void) 1114 { 1115 /* 1116 * LSTAR and STAR live in a bit strange symbiosis. 1117 * They both write to the same internal register. STAR allows to 1118 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1119 */ 1120 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1121 wrmsrl(MSR_LSTAR, system_call); 1122 wrmsrl(MSR_CSTAR, ignore_sysret); 1123 1124 #ifdef CONFIG_IA32_EMULATION 1125 syscall32_cpu_init(); 1126 #endif 1127 1128 /* Flags to clear on syscall */ 1129 wrmsrl(MSR_SYSCALL_MASK, 1130 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1131 X86_EFLAGS_IOPL|X86_EFLAGS_AC); 1132 } 1133 1134 /* 1135 * Copies of the original ist values from the tss are only accessed during 1136 * debugging, no special alignment required. 1137 */ 1138 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1139 1140 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1141 DEFINE_PER_CPU(int, debug_stack_usage); 1142 1143 int is_debug_stack(unsigned long addr) 1144 { 1145 return __get_cpu_var(debug_stack_usage) || 1146 (addr <= __get_cpu_var(debug_stack_addr) && 1147 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); 1148 } 1149 1150 static DEFINE_PER_CPU(u32, debug_stack_use_ctr); 1151 1152 void debug_stack_set_zero(void) 1153 { 1154 this_cpu_inc(debug_stack_use_ctr); 1155 load_idt((const struct desc_ptr *)&nmi_idt_descr); 1156 } 1157 1158 void debug_stack_reset(void) 1159 { 1160 if (WARN_ON(!this_cpu_read(debug_stack_use_ctr))) 1161 return; 1162 if (this_cpu_dec_return(debug_stack_use_ctr) == 0) 1163 load_idt((const struct desc_ptr *)&idt_descr); 1164 } 1165 1166 #else /* CONFIG_X86_64 */ 1167 1168 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1169 EXPORT_PER_CPU_SYMBOL(current_task); 1170 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1171 1172 #ifdef CONFIG_CC_STACKPROTECTOR 1173 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1174 #endif 1175 1176 #endif /* CONFIG_X86_64 */ 1177 1178 /* 1179 * Clear all 6 debug registers: 1180 */ 1181 static void clear_all_debug_regs(void) 1182 { 1183 int i; 1184 1185 for (i = 0; i < 8; i++) { 1186 /* Ignore db4, db5 */ 1187 if ((i == 4) || (i == 5)) 1188 continue; 1189 1190 set_debugreg(0, i); 1191 } 1192 } 1193 1194 #ifdef CONFIG_KGDB 1195 /* 1196 * Restore debug regs if using kgdbwait and you have a kernel debugger 1197 * connection established. 1198 */ 1199 static void dbg_restore_debug_regs(void) 1200 { 1201 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1202 arch_kgdb_ops.correct_hw_break(); 1203 } 1204 #else /* ! CONFIG_KGDB */ 1205 #define dbg_restore_debug_regs() 1206 #endif /* ! CONFIG_KGDB */ 1207 1208 /* 1209 * cpu_init() initializes state that is per-CPU. Some data is already 1210 * initialized (naturally) in the bootstrap process, such as the GDT 1211 * and IDT. We reload them nevertheless, this function acts as a 1212 * 'CPU state barrier', nothing should get across. 1213 * A lot of state is already set up in PDA init for 64 bit 1214 */ 1215 #ifdef CONFIG_X86_64 1216 1217 void __cpuinit cpu_init(void) 1218 { 1219 struct orig_ist *oist; 1220 struct task_struct *me; 1221 struct tss_struct *t; 1222 unsigned long v; 1223 int cpu; 1224 int i; 1225 1226 cpu = stack_smp_processor_id(); 1227 t = &per_cpu(init_tss, cpu); 1228 oist = &per_cpu(orig_ist, cpu); 1229 1230 #ifdef CONFIG_NUMA 1231 if (this_cpu_read(numa_node) == 0 && 1232 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1233 set_numa_node(early_cpu_to_node(cpu)); 1234 #endif 1235 1236 me = current; 1237 1238 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1239 panic("CPU#%d already initialized!\n", cpu); 1240 1241 pr_debug("Initializing CPU#%d\n", cpu); 1242 1243 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1244 1245 /* 1246 * Initialize the per-CPU GDT with the boot GDT, 1247 * and set up the GDT descriptor: 1248 */ 1249 1250 switch_to_new_gdt(cpu); 1251 loadsegment(fs, 0); 1252 1253 load_idt((const struct desc_ptr *)&idt_descr); 1254 1255 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1256 syscall_init(); 1257 1258 wrmsrl(MSR_FS_BASE, 0); 1259 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1260 barrier(); 1261 1262 x86_configure_nx(); 1263 enable_x2apic(); 1264 1265 /* 1266 * set up and load the per-CPU TSS 1267 */ 1268 if (!oist->ist[0]) { 1269 char *estacks = per_cpu(exception_stacks, cpu); 1270 1271 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1272 estacks += exception_stack_sizes[v]; 1273 oist->ist[v] = t->x86_tss.ist[v] = 1274 (unsigned long)estacks; 1275 if (v == DEBUG_STACK-1) 1276 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1277 } 1278 } 1279 1280 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1281 1282 /* 1283 * <= is required because the CPU will access up to 1284 * 8 bits beyond the end of the IO permission bitmap. 1285 */ 1286 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1287 t->io_bitmap[i] = ~0UL; 1288 1289 atomic_inc(&init_mm.mm_count); 1290 me->active_mm = &init_mm; 1291 BUG_ON(me->mm); 1292 enter_lazy_tlb(&init_mm, me); 1293 1294 load_sp0(t, ¤t->thread); 1295 set_tss_desc(cpu, t); 1296 load_TR_desc(); 1297 load_LDT(&init_mm.context); 1298 1299 clear_all_debug_regs(); 1300 dbg_restore_debug_regs(); 1301 1302 fpu_init(); 1303 1304 if (is_uv_system()) 1305 uv_cpu_init(); 1306 } 1307 1308 #else 1309 1310 void __cpuinit cpu_init(void) 1311 { 1312 int cpu = smp_processor_id(); 1313 struct task_struct *curr = current; 1314 struct tss_struct *t = &per_cpu(init_tss, cpu); 1315 struct thread_struct *thread = &curr->thread; 1316 1317 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1318 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1319 for (;;) 1320 local_irq_enable(); 1321 } 1322 1323 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1324 1325 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1326 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1327 1328 load_idt(&idt_descr); 1329 switch_to_new_gdt(cpu); 1330 1331 /* 1332 * Set up and load the per-CPU TSS and LDT 1333 */ 1334 atomic_inc(&init_mm.mm_count); 1335 curr->active_mm = &init_mm; 1336 BUG_ON(curr->mm); 1337 enter_lazy_tlb(&init_mm, curr); 1338 1339 load_sp0(t, thread); 1340 set_tss_desc(cpu, t); 1341 load_TR_desc(); 1342 load_LDT(&init_mm.context); 1343 1344 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1345 1346 #ifdef CONFIG_DOUBLEFAULT 1347 /* Set up doublefault TSS pointer in the GDT */ 1348 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1349 #endif 1350 1351 clear_all_debug_regs(); 1352 dbg_restore_debug_regs(); 1353 1354 fpu_init(); 1355 } 1356 #endif 1357