1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/init.h> 18 #include <linux/kprobes.h> 19 #include <linux/kgdb.h> 20 #include <linux/smp.h> 21 #include <linux/io.h> 22 #include <linux/syscore_ops.h> 23 24 #include <asm/stackprotector.h> 25 #include <asm/perf_event.h> 26 #include <asm/mmu_context.h> 27 #include <asm/archrandom.h> 28 #include <asm/hypervisor.h> 29 #include <asm/processor.h> 30 #include <asm/tlbflush.h> 31 #include <asm/debugreg.h> 32 #include <asm/sections.h> 33 #include <asm/vsyscall.h> 34 #include <linux/topology.h> 35 #include <linux/cpumask.h> 36 #include <asm/pgtable.h> 37 #include <linux/atomic.h> 38 #include <asm/proto.h> 39 #include <asm/setup.h> 40 #include <asm/apic.h> 41 #include <asm/desc.h> 42 #include <asm/fpu/internal.h> 43 #include <asm/mtrr.h> 44 #include <asm/hwcap2.h> 45 #include <linux/numa.h> 46 #include <asm/asm.h> 47 #include <asm/bugs.h> 48 #include <asm/cpu.h> 49 #include <asm/mce.h> 50 #include <asm/msr.h> 51 #include <asm/pat.h> 52 #include <asm/microcode.h> 53 #include <asm/microcode_intel.h> 54 #include <asm/intel-family.h> 55 #include <asm/cpu_device_id.h> 56 57 #ifdef CONFIG_X86_LOCAL_APIC 58 #include <asm/uv/uv.h> 59 #endif 60 61 #include "cpu.h" 62 63 u32 elf_hwcap2 __read_mostly; 64 65 /* all of these masks are initialized in setup_cpu_local_masks() */ 66 cpumask_var_t cpu_initialized_mask; 67 cpumask_var_t cpu_callout_mask; 68 cpumask_var_t cpu_callin_mask; 69 70 /* representing cpus for which sibling maps can be computed */ 71 cpumask_var_t cpu_sibling_setup_mask; 72 73 /* Number of siblings per CPU package */ 74 int smp_num_siblings = 1; 75 EXPORT_SYMBOL(smp_num_siblings); 76 77 /* Last level cache ID of each logical CPU */ 78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 79 80 /* correctly size the local cpu masks */ 81 void __init setup_cpu_local_masks(void) 82 { 83 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 84 alloc_bootmem_cpumask_var(&cpu_callin_mask); 85 alloc_bootmem_cpumask_var(&cpu_callout_mask); 86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 87 } 88 89 static void default_init(struct cpuinfo_x86 *c) 90 { 91 #ifdef CONFIG_X86_64 92 cpu_detect_cache_sizes(c); 93 #else 94 /* Not much we can do here... */ 95 /* Check if at least it has cpuid */ 96 if (c->cpuid_level == -1) { 97 /* No cpuid. It must be an ancient CPU */ 98 if (c->x86 == 4) 99 strcpy(c->x86_model_id, "486"); 100 else if (c->x86 == 3) 101 strcpy(c->x86_model_id, "386"); 102 } 103 #endif 104 } 105 106 static const struct cpu_dev default_cpu = { 107 .c_init = default_init, 108 .c_vendor = "Unknown", 109 .c_x86_vendor = X86_VENDOR_UNKNOWN, 110 }; 111 112 static const struct cpu_dev *this_cpu = &default_cpu; 113 114 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 115 #ifdef CONFIG_X86_64 116 /* 117 * We need valid kernel segments for data and code in long mode too 118 * IRET will check the segment types kkeil 2000/10/28 119 * Also sysret mandates a special GDT layout 120 * 121 * TLS descriptors are currently at a different place compared to i386. 122 * Hopefully nobody expects them at a fixed place (Wine?) 123 */ 124 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 125 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 126 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 128 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 130 #else 131 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 132 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 133 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 134 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 135 /* 136 * Segments used for calling PnP BIOS have byte granularity. 137 * They code segments and data segments have fixed 64k limits, 138 * the transfer segment sizes are set at run time. 139 */ 140 /* 32-bit code */ 141 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 142 /* 16-bit code */ 143 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 144 /* 16-bit data */ 145 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 146 /* 16-bit data */ 147 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 148 /* 16-bit data */ 149 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 150 /* 151 * The APM segments have byte granularity and their bases 152 * are set at run time. All have 64k limits. 153 */ 154 /* 32-bit code */ 155 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 156 /* 16-bit code */ 157 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 158 /* data */ 159 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 160 161 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 162 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 163 GDT_STACK_CANARY_INIT 164 #endif 165 } }; 166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 167 168 static int __init x86_mpx_setup(char *s) 169 { 170 /* require an exact match without trailing characters */ 171 if (strlen(s)) 172 return 0; 173 174 /* do not emit a message if the feature is not present */ 175 if (!boot_cpu_has(X86_FEATURE_MPX)) 176 return 1; 177 178 setup_clear_cpu_cap(X86_FEATURE_MPX); 179 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 180 return 1; 181 } 182 __setup("nompx", x86_mpx_setup); 183 184 #ifdef CONFIG_X86_64 185 static int __init x86_nopcid_setup(char *s) 186 { 187 /* nopcid doesn't accept parameters */ 188 if (s) 189 return -EINVAL; 190 191 /* do not emit a message if the feature is not present */ 192 if (!boot_cpu_has(X86_FEATURE_PCID)) 193 return 0; 194 195 setup_clear_cpu_cap(X86_FEATURE_PCID); 196 pr_info("nopcid: PCID feature disabled\n"); 197 return 0; 198 } 199 early_param("nopcid", x86_nopcid_setup); 200 #endif 201 202 static int __init x86_noinvpcid_setup(char *s) 203 { 204 /* noinvpcid doesn't accept parameters */ 205 if (s) 206 return -EINVAL; 207 208 /* do not emit a message if the feature is not present */ 209 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 210 return 0; 211 212 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 213 pr_info("noinvpcid: INVPCID feature disabled\n"); 214 return 0; 215 } 216 early_param("noinvpcid", x86_noinvpcid_setup); 217 218 #ifdef CONFIG_X86_32 219 static int cachesize_override = -1; 220 static int disable_x86_serial_nr = 1; 221 222 static int __init cachesize_setup(char *str) 223 { 224 get_option(&str, &cachesize_override); 225 return 1; 226 } 227 __setup("cachesize=", cachesize_setup); 228 229 static int __init x86_sep_setup(char *s) 230 { 231 setup_clear_cpu_cap(X86_FEATURE_SEP); 232 return 1; 233 } 234 __setup("nosep", x86_sep_setup); 235 236 /* Standard macro to see if a specific flag is changeable */ 237 static inline int flag_is_changeable_p(u32 flag) 238 { 239 u32 f1, f2; 240 241 /* 242 * Cyrix and IDT cpus allow disabling of CPUID 243 * so the code below may return different results 244 * when it is executed before and after enabling 245 * the CPUID. Add "volatile" to not allow gcc to 246 * optimize the subsequent calls to this function. 247 */ 248 asm volatile ("pushfl \n\t" 249 "pushfl \n\t" 250 "popl %0 \n\t" 251 "movl %0, %1 \n\t" 252 "xorl %2, %0 \n\t" 253 "pushl %0 \n\t" 254 "popfl \n\t" 255 "pushfl \n\t" 256 "popl %0 \n\t" 257 "popfl \n\t" 258 259 : "=&r" (f1), "=&r" (f2) 260 : "ir" (flag)); 261 262 return ((f1^f2) & flag) != 0; 263 } 264 265 /* Probe for the CPUID instruction */ 266 int have_cpuid_p(void) 267 { 268 return flag_is_changeable_p(X86_EFLAGS_ID); 269 } 270 271 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 272 { 273 unsigned long lo, hi; 274 275 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 276 return; 277 278 /* Disable processor serial number: */ 279 280 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 281 lo |= 0x200000; 282 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 283 284 pr_notice("CPU serial number disabled.\n"); 285 clear_cpu_cap(c, X86_FEATURE_PN); 286 287 /* Disabling the serial number may affect the cpuid level */ 288 c->cpuid_level = cpuid_eax(0); 289 } 290 291 static int __init x86_serial_nr_setup(char *s) 292 { 293 disable_x86_serial_nr = 0; 294 return 1; 295 } 296 __setup("serialnumber", x86_serial_nr_setup); 297 #else 298 static inline int flag_is_changeable_p(u32 flag) 299 { 300 return 1; 301 } 302 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 303 { 304 } 305 #endif 306 307 static __init int setup_disable_smep(char *arg) 308 { 309 setup_clear_cpu_cap(X86_FEATURE_SMEP); 310 /* Check for things that depend on SMEP being enabled: */ 311 check_mpx_erratum(&boot_cpu_data); 312 return 1; 313 } 314 __setup("nosmep", setup_disable_smep); 315 316 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 317 { 318 if (cpu_has(c, X86_FEATURE_SMEP)) 319 cr4_set_bits(X86_CR4_SMEP); 320 } 321 322 static __init int setup_disable_smap(char *arg) 323 { 324 setup_clear_cpu_cap(X86_FEATURE_SMAP); 325 return 1; 326 } 327 __setup("nosmap", setup_disable_smap); 328 329 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 330 { 331 unsigned long eflags = native_save_fl(); 332 333 /* This should have been cleared long ago */ 334 BUG_ON(eflags & X86_EFLAGS_AC); 335 336 if (cpu_has(c, X86_FEATURE_SMAP)) { 337 #ifdef CONFIG_X86_SMAP 338 cr4_set_bits(X86_CR4_SMAP); 339 #else 340 cr4_clear_bits(X86_CR4_SMAP); 341 #endif 342 } 343 } 344 345 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 346 { 347 /* Check the boot processor, plus build option for UMIP. */ 348 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 349 goto out; 350 351 /* Check the current processor's cpuid bits. */ 352 if (!cpu_has(c, X86_FEATURE_UMIP)) 353 goto out; 354 355 cr4_set_bits(X86_CR4_UMIP); 356 357 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 358 359 return; 360 361 out: 362 /* 363 * Make sure UMIP is disabled in case it was enabled in a 364 * previous boot (e.g., via kexec). 365 */ 366 cr4_clear_bits(X86_CR4_UMIP); 367 } 368 369 /* 370 * Protection Keys are not available in 32-bit mode. 371 */ 372 static bool pku_disabled; 373 374 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 375 { 376 struct pkru_state *pk; 377 378 /* check the boot processor, plus compile options for PKU: */ 379 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 380 return; 381 /* checks the actual processor's cpuid bits: */ 382 if (!cpu_has(c, X86_FEATURE_PKU)) 383 return; 384 if (pku_disabled) 385 return; 386 387 cr4_set_bits(X86_CR4_PKE); 388 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 389 if (pk) 390 pk->pkru = init_pkru_value; 391 /* 392 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 393 * cpuid bit to be set. We need to ensure that we 394 * update that bit in this CPU's "cpu_info". 395 */ 396 get_cpu_cap(c); 397 } 398 399 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 400 static __init int setup_disable_pku(char *arg) 401 { 402 /* 403 * Do not clear the X86_FEATURE_PKU bit. All of the 404 * runtime checks are against OSPKE so clearing the 405 * bit does nothing. 406 * 407 * This way, we will see "pku" in cpuinfo, but not 408 * "ospke", which is exactly what we want. It shows 409 * that the CPU has PKU, but the OS has not enabled it. 410 * This happens to be exactly how a system would look 411 * if we disabled the config option. 412 */ 413 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 414 pku_disabled = true; 415 return 1; 416 } 417 __setup("nopku", setup_disable_pku); 418 #endif /* CONFIG_X86_64 */ 419 420 /* 421 * Some CPU features depend on higher CPUID levels, which may not always 422 * be available due to CPUID level capping or broken virtualization 423 * software. Add those features to this table to auto-disable them. 424 */ 425 struct cpuid_dependent_feature { 426 u32 feature; 427 u32 level; 428 }; 429 430 static const struct cpuid_dependent_feature 431 cpuid_dependent_features[] = { 432 { X86_FEATURE_MWAIT, 0x00000005 }, 433 { X86_FEATURE_DCA, 0x00000009 }, 434 { X86_FEATURE_XSAVE, 0x0000000d }, 435 { 0, 0 } 436 }; 437 438 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 439 { 440 const struct cpuid_dependent_feature *df; 441 442 for (df = cpuid_dependent_features; df->feature; df++) { 443 444 if (!cpu_has(c, df->feature)) 445 continue; 446 /* 447 * Note: cpuid_level is set to -1 if unavailable, but 448 * extended_extended_level is set to 0 if unavailable 449 * and the legitimate extended levels are all negative 450 * when signed; hence the weird messing around with 451 * signs here... 452 */ 453 if (!((s32)df->level < 0 ? 454 (u32)df->level > (u32)c->extended_cpuid_level : 455 (s32)df->level > (s32)c->cpuid_level)) 456 continue; 457 458 clear_cpu_cap(c, df->feature); 459 if (!warn) 460 continue; 461 462 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 463 x86_cap_flag(df->feature), df->level); 464 } 465 } 466 467 /* 468 * Naming convention should be: <Name> [(<Codename>)] 469 * This table only is used unless init_<vendor>() below doesn't set it; 470 * in particular, if CPUID levels 0x80000002..4 are supported, this 471 * isn't used 472 */ 473 474 /* Look up CPU names by table lookup. */ 475 static const char *table_lookup_model(struct cpuinfo_x86 *c) 476 { 477 #ifdef CONFIG_X86_32 478 const struct legacy_cpu_model_info *info; 479 480 if (c->x86_model >= 16) 481 return NULL; /* Range check */ 482 483 if (!this_cpu) 484 return NULL; 485 486 info = this_cpu->legacy_models; 487 488 while (info->family) { 489 if (info->family == c->x86) 490 return info->model_names[c->x86_model]; 491 info++; 492 } 493 #endif 494 return NULL; /* Not found */ 495 } 496 497 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 498 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 499 500 void load_percpu_segment(int cpu) 501 { 502 #ifdef CONFIG_X86_32 503 loadsegment(fs, __KERNEL_PERCPU); 504 #else 505 __loadsegment_simple(gs, 0); 506 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 507 #endif 508 load_stack_canary_segment(); 509 } 510 511 #ifdef CONFIG_X86_32 512 /* The 32-bit entry code needs to find cpu_entry_area. */ 513 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 514 #endif 515 516 /* Load the original GDT from the per-cpu structure */ 517 void load_direct_gdt(int cpu) 518 { 519 struct desc_ptr gdt_descr; 520 521 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 522 gdt_descr.size = GDT_SIZE - 1; 523 load_gdt(&gdt_descr); 524 } 525 EXPORT_SYMBOL_GPL(load_direct_gdt); 526 527 /* Load a fixmap remapping of the per-cpu GDT */ 528 void load_fixmap_gdt(int cpu) 529 { 530 struct desc_ptr gdt_descr; 531 532 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 533 gdt_descr.size = GDT_SIZE - 1; 534 load_gdt(&gdt_descr); 535 } 536 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 537 538 /* 539 * Current gdt points %fs at the "master" per-cpu area: after this, 540 * it's on the real one. 541 */ 542 void switch_to_new_gdt(int cpu) 543 { 544 /* Load the original GDT */ 545 load_direct_gdt(cpu); 546 /* Reload the per-cpu base */ 547 load_percpu_segment(cpu); 548 } 549 550 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 551 552 static void get_model_name(struct cpuinfo_x86 *c) 553 { 554 unsigned int *v; 555 char *p, *q, *s; 556 557 if (c->extended_cpuid_level < 0x80000004) 558 return; 559 560 v = (unsigned int *)c->x86_model_id; 561 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 562 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 563 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 564 c->x86_model_id[48] = 0; 565 566 /* Trim whitespace */ 567 p = q = s = &c->x86_model_id[0]; 568 569 while (*p == ' ') 570 p++; 571 572 while (*p) { 573 /* Note the last non-whitespace index */ 574 if (!isspace(*p)) 575 s = q; 576 577 *q++ = *p++; 578 } 579 580 *(s + 1) = '\0'; 581 } 582 583 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 584 { 585 unsigned int eax, ebx, ecx, edx; 586 587 c->x86_max_cores = 1; 588 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 589 return; 590 591 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 592 if (eax & 0x1f) 593 c->x86_max_cores = (eax >> 26) + 1; 594 } 595 596 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 597 { 598 unsigned int n, dummy, ebx, ecx, edx, l2size; 599 600 n = c->extended_cpuid_level; 601 602 if (n >= 0x80000005) { 603 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 604 c->x86_cache_size = (ecx>>24) + (edx>>24); 605 #ifdef CONFIG_X86_64 606 /* On K8 L1 TLB is inclusive, so don't count it */ 607 c->x86_tlbsize = 0; 608 #endif 609 } 610 611 if (n < 0x80000006) /* Some chips just has a large L1. */ 612 return; 613 614 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 615 l2size = ecx >> 16; 616 617 #ifdef CONFIG_X86_64 618 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 619 #else 620 /* do processor-specific cache resizing */ 621 if (this_cpu->legacy_cache_size) 622 l2size = this_cpu->legacy_cache_size(c, l2size); 623 624 /* Allow user to override all this if necessary. */ 625 if (cachesize_override != -1) 626 l2size = cachesize_override; 627 628 if (l2size == 0) 629 return; /* Again, no L2 cache is possible */ 630 #endif 631 632 c->x86_cache_size = l2size; 633 } 634 635 u16 __read_mostly tlb_lli_4k[NR_INFO]; 636 u16 __read_mostly tlb_lli_2m[NR_INFO]; 637 u16 __read_mostly tlb_lli_4m[NR_INFO]; 638 u16 __read_mostly tlb_lld_4k[NR_INFO]; 639 u16 __read_mostly tlb_lld_2m[NR_INFO]; 640 u16 __read_mostly tlb_lld_4m[NR_INFO]; 641 u16 __read_mostly tlb_lld_1g[NR_INFO]; 642 643 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 644 { 645 if (this_cpu->c_detect_tlb) 646 this_cpu->c_detect_tlb(c); 647 648 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 649 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 650 tlb_lli_4m[ENTRIES]); 651 652 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 653 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 654 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 655 } 656 657 int detect_ht_early(struct cpuinfo_x86 *c) 658 { 659 #ifdef CONFIG_SMP 660 u32 eax, ebx, ecx, edx; 661 662 if (!cpu_has(c, X86_FEATURE_HT)) 663 return -1; 664 665 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 666 return -1; 667 668 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 669 return -1; 670 671 cpuid(1, &eax, &ebx, &ecx, &edx); 672 673 smp_num_siblings = (ebx & 0xff0000) >> 16; 674 if (smp_num_siblings == 1) 675 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 676 #endif 677 return 0; 678 } 679 680 void detect_ht(struct cpuinfo_x86 *c) 681 { 682 #ifdef CONFIG_SMP 683 int index_msb, core_bits; 684 685 if (detect_ht_early(c) < 0) 686 return; 687 688 index_msb = get_count_order(smp_num_siblings); 689 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 690 691 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 692 693 index_msb = get_count_order(smp_num_siblings); 694 695 core_bits = get_count_order(c->x86_max_cores); 696 697 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 698 ((1 << core_bits) - 1); 699 #endif 700 } 701 702 static void get_cpu_vendor(struct cpuinfo_x86 *c) 703 { 704 char *v = c->x86_vendor_id; 705 int i; 706 707 for (i = 0; i < X86_VENDOR_NUM; i++) { 708 if (!cpu_devs[i]) 709 break; 710 711 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 712 (cpu_devs[i]->c_ident[1] && 713 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 714 715 this_cpu = cpu_devs[i]; 716 c->x86_vendor = this_cpu->c_x86_vendor; 717 return; 718 } 719 } 720 721 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 722 "CPU: Your system may be unstable.\n", v); 723 724 c->x86_vendor = X86_VENDOR_UNKNOWN; 725 this_cpu = &default_cpu; 726 } 727 728 void cpu_detect(struct cpuinfo_x86 *c) 729 { 730 /* Get vendor name */ 731 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 732 (unsigned int *)&c->x86_vendor_id[0], 733 (unsigned int *)&c->x86_vendor_id[8], 734 (unsigned int *)&c->x86_vendor_id[4]); 735 736 c->x86 = 4; 737 /* Intel-defined flags: level 0x00000001 */ 738 if (c->cpuid_level >= 0x00000001) { 739 u32 junk, tfms, cap0, misc; 740 741 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 742 c->x86 = x86_family(tfms); 743 c->x86_model = x86_model(tfms); 744 c->x86_stepping = x86_stepping(tfms); 745 746 if (cap0 & (1<<19)) { 747 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 748 c->x86_cache_alignment = c->x86_clflush_size; 749 } 750 } 751 } 752 753 static void apply_forced_caps(struct cpuinfo_x86 *c) 754 { 755 int i; 756 757 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 758 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 759 c->x86_capability[i] |= cpu_caps_set[i]; 760 } 761 } 762 763 static void init_speculation_control(struct cpuinfo_x86 *c) 764 { 765 /* 766 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 767 * and they also have a different bit for STIBP support. Also, 768 * a hypervisor might have set the individual AMD bits even on 769 * Intel CPUs, for finer-grained selection of what's available. 770 */ 771 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 772 set_cpu_cap(c, X86_FEATURE_IBRS); 773 set_cpu_cap(c, X86_FEATURE_IBPB); 774 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 775 } 776 777 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 778 set_cpu_cap(c, X86_FEATURE_STIBP); 779 780 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 781 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 782 set_cpu_cap(c, X86_FEATURE_SSBD); 783 784 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 785 set_cpu_cap(c, X86_FEATURE_IBRS); 786 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 787 } 788 789 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 790 set_cpu_cap(c, X86_FEATURE_IBPB); 791 792 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 793 set_cpu_cap(c, X86_FEATURE_STIBP); 794 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 795 } 796 797 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 798 set_cpu_cap(c, X86_FEATURE_SSBD); 799 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 800 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 801 } 802 } 803 804 void get_cpu_cap(struct cpuinfo_x86 *c) 805 { 806 u32 eax, ebx, ecx, edx; 807 808 /* Intel-defined flags: level 0x00000001 */ 809 if (c->cpuid_level >= 0x00000001) { 810 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 811 812 c->x86_capability[CPUID_1_ECX] = ecx; 813 c->x86_capability[CPUID_1_EDX] = edx; 814 } 815 816 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 817 if (c->cpuid_level >= 0x00000006) 818 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 819 820 /* Additional Intel-defined flags: level 0x00000007 */ 821 if (c->cpuid_level >= 0x00000007) { 822 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 823 c->x86_capability[CPUID_7_0_EBX] = ebx; 824 c->x86_capability[CPUID_7_ECX] = ecx; 825 c->x86_capability[CPUID_7_EDX] = edx; 826 } 827 828 /* Extended state features: level 0x0000000d */ 829 if (c->cpuid_level >= 0x0000000d) { 830 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 831 832 c->x86_capability[CPUID_D_1_EAX] = eax; 833 } 834 835 /* Additional Intel-defined flags: level 0x0000000F */ 836 if (c->cpuid_level >= 0x0000000F) { 837 838 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 839 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 840 c->x86_capability[CPUID_F_0_EDX] = edx; 841 842 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 843 /* will be overridden if occupancy monitoring exists */ 844 c->x86_cache_max_rmid = ebx; 845 846 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 847 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 848 c->x86_capability[CPUID_F_1_EDX] = edx; 849 850 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 851 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 852 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 853 c->x86_cache_max_rmid = ecx; 854 c->x86_cache_occ_scale = ebx; 855 } 856 } else { 857 c->x86_cache_max_rmid = -1; 858 c->x86_cache_occ_scale = -1; 859 } 860 } 861 862 /* AMD-defined flags: level 0x80000001 */ 863 eax = cpuid_eax(0x80000000); 864 c->extended_cpuid_level = eax; 865 866 if ((eax & 0xffff0000) == 0x80000000) { 867 if (eax >= 0x80000001) { 868 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 869 870 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 871 c->x86_capability[CPUID_8000_0001_EDX] = edx; 872 } 873 } 874 875 if (c->extended_cpuid_level >= 0x80000007) { 876 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 877 878 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 879 c->x86_power = edx; 880 } 881 882 if (c->extended_cpuid_level >= 0x80000008) { 883 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 884 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 885 } 886 887 if (c->extended_cpuid_level >= 0x8000000a) 888 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 889 890 init_scattered_cpuid_features(c); 891 init_speculation_control(c); 892 893 /* 894 * Clear/Set all flags overridden by options, after probe. 895 * This needs to happen each time we re-probe, which may happen 896 * several times during CPU initialization. 897 */ 898 apply_forced_caps(c); 899 } 900 901 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 902 { 903 u32 eax, ebx, ecx, edx; 904 905 if (c->extended_cpuid_level >= 0x80000008) { 906 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 907 908 c->x86_virt_bits = (eax >> 8) & 0xff; 909 c->x86_phys_bits = eax & 0xff; 910 } 911 #ifdef CONFIG_X86_32 912 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 913 c->x86_phys_bits = 36; 914 #endif 915 c->x86_cache_bits = c->x86_phys_bits; 916 } 917 918 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 919 { 920 #ifdef CONFIG_X86_32 921 int i; 922 923 /* 924 * First of all, decide if this is a 486 or higher 925 * It's a 486 if we can modify the AC flag 926 */ 927 if (flag_is_changeable_p(X86_EFLAGS_AC)) 928 c->x86 = 4; 929 else 930 c->x86 = 3; 931 932 for (i = 0; i < X86_VENDOR_NUM; i++) 933 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 934 c->x86_vendor_id[0] = 0; 935 cpu_devs[i]->c_identify(c); 936 if (c->x86_vendor_id[0]) { 937 get_cpu_vendor(c); 938 break; 939 } 940 } 941 #endif 942 } 943 944 #define NO_SPECULATION BIT(0) 945 #define NO_MELTDOWN BIT(1) 946 #define NO_SSB BIT(2) 947 #define NO_L1TF BIT(3) 948 #define NO_MDS BIT(4) 949 #define MSBDS_ONLY BIT(5) 950 951 #define VULNWL(_vendor, _family, _model, _whitelist) \ 952 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } 953 954 #define VULNWL_INTEL(model, whitelist) \ 955 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 956 957 #define VULNWL_AMD(family, whitelist) \ 958 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 959 960 #define VULNWL_HYGON(family, whitelist) \ 961 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 962 963 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 964 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 965 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 966 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 967 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 968 969 /* Intel Family 6 */ 970 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION), 971 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION), 972 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION), 973 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), 974 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), 975 976 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), 977 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY), 978 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY), 979 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), 980 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY), 981 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY), 982 983 VULNWL_INTEL(CORE_YONAH, NO_SSB), 984 985 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY), 986 987 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF), 988 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF), 989 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF), 990 991 /* AMD Family 0xf - 0x12 */ 992 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 993 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 994 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 995 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 996 997 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 998 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), 999 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), 1000 {} 1001 }; 1002 1003 static bool __init cpu_matches(unsigned long which) 1004 { 1005 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 1006 1007 return m && !!(m->driver_data & which); 1008 } 1009 1010 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1011 { 1012 u64 ia32_cap = 0; 1013 1014 if (cpu_matches(NO_SPECULATION)) 1015 return; 1016 1017 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1018 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1019 1020 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) 1021 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1022 1023 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 1024 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1025 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1026 1027 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1028 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1029 1030 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1031 setup_force_cpu_bug(X86_BUG_MDS); 1032 if (cpu_matches(MSBDS_ONLY)) 1033 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1034 } 1035 1036 if (cpu_matches(NO_MELTDOWN)) 1037 return; 1038 1039 /* Rogue Data Cache Load? No! */ 1040 if (ia32_cap & ARCH_CAP_RDCL_NO) 1041 return; 1042 1043 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1044 1045 if (cpu_matches(NO_L1TF)) 1046 return; 1047 1048 setup_force_cpu_bug(X86_BUG_L1TF); 1049 } 1050 1051 /* 1052 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1053 * unfortunately, that's not true in practice because of early VIA 1054 * chips and (more importantly) broken virtualizers that are not easy 1055 * to detect. In the latter case it doesn't even *fail* reliably, so 1056 * probing for it doesn't even work. Disable it completely on 32-bit 1057 * unless we can find a reliable way to detect all the broken cases. 1058 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1059 */ 1060 static void detect_nopl(void) 1061 { 1062 #ifdef CONFIG_X86_32 1063 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1064 #else 1065 setup_force_cpu_cap(X86_FEATURE_NOPL); 1066 #endif 1067 } 1068 1069 /* 1070 * Do minimum CPU detection early. 1071 * Fields really needed: vendor, cpuid_level, family, model, mask, 1072 * cache alignment. 1073 * The others are not touched to avoid unwanted side effects. 1074 * 1075 * WARNING: this function is only called on the boot CPU. Don't add code 1076 * here that is supposed to run on all CPUs. 1077 */ 1078 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1079 { 1080 #ifdef CONFIG_X86_64 1081 c->x86_clflush_size = 64; 1082 c->x86_phys_bits = 36; 1083 c->x86_virt_bits = 48; 1084 #else 1085 c->x86_clflush_size = 32; 1086 c->x86_phys_bits = 32; 1087 c->x86_virt_bits = 32; 1088 #endif 1089 c->x86_cache_alignment = c->x86_clflush_size; 1090 1091 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1092 c->extended_cpuid_level = 0; 1093 1094 if (!have_cpuid_p()) 1095 identify_cpu_without_cpuid(c); 1096 1097 /* cyrix could have cpuid enabled via c_identify()*/ 1098 if (have_cpuid_p()) { 1099 cpu_detect(c); 1100 get_cpu_vendor(c); 1101 get_cpu_cap(c); 1102 get_cpu_address_sizes(c); 1103 setup_force_cpu_cap(X86_FEATURE_CPUID); 1104 1105 if (this_cpu->c_early_init) 1106 this_cpu->c_early_init(c); 1107 1108 c->cpu_index = 0; 1109 filter_cpuid_features(c, false); 1110 1111 if (this_cpu->c_bsp_init) 1112 this_cpu->c_bsp_init(c); 1113 } else { 1114 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1115 } 1116 1117 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1118 1119 cpu_set_bug_bits(c); 1120 1121 fpu__init_system(c); 1122 1123 #ifdef CONFIG_X86_32 1124 /* 1125 * Regardless of whether PCID is enumerated, the SDM says 1126 * that it can't be enabled in 32-bit mode. 1127 */ 1128 setup_clear_cpu_cap(X86_FEATURE_PCID); 1129 #endif 1130 1131 /* 1132 * Later in the boot process pgtable_l5_enabled() relies on 1133 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1134 * enabled by this point we need to clear the feature bit to avoid 1135 * false-positives at the later stage. 1136 * 1137 * pgtable_l5_enabled() can be false here for several reasons: 1138 * - 5-level paging is disabled compile-time; 1139 * - it's 32-bit kernel; 1140 * - machine doesn't support 5-level paging; 1141 * - user specified 'no5lvl' in kernel command line. 1142 */ 1143 if (!pgtable_l5_enabled()) 1144 setup_clear_cpu_cap(X86_FEATURE_LA57); 1145 1146 detect_nopl(); 1147 } 1148 1149 void __init early_cpu_init(void) 1150 { 1151 const struct cpu_dev *const *cdev; 1152 int count = 0; 1153 1154 #ifdef CONFIG_PROCESSOR_SELECT 1155 pr_info("KERNEL supported cpus:\n"); 1156 #endif 1157 1158 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1159 const struct cpu_dev *cpudev = *cdev; 1160 1161 if (count >= X86_VENDOR_NUM) 1162 break; 1163 cpu_devs[count] = cpudev; 1164 count++; 1165 1166 #ifdef CONFIG_PROCESSOR_SELECT 1167 { 1168 unsigned int j; 1169 1170 for (j = 0; j < 2; j++) { 1171 if (!cpudev->c_ident[j]) 1172 continue; 1173 pr_info(" %s %s\n", cpudev->c_vendor, 1174 cpudev->c_ident[j]); 1175 } 1176 } 1177 #endif 1178 } 1179 early_identify_cpu(&boot_cpu_data); 1180 } 1181 1182 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1183 { 1184 #ifdef CONFIG_X86_64 1185 /* 1186 * Empirically, writing zero to a segment selector on AMD does 1187 * not clear the base, whereas writing zero to a segment 1188 * selector on Intel does clear the base. Intel's behavior 1189 * allows slightly faster context switches in the common case 1190 * where GS is unused by the prev and next threads. 1191 * 1192 * Since neither vendor documents this anywhere that I can see, 1193 * detect it directly instead of hardcoding the choice by 1194 * vendor. 1195 * 1196 * I've designated AMD's behavior as the "bug" because it's 1197 * counterintuitive and less friendly. 1198 */ 1199 1200 unsigned long old_base, tmp; 1201 rdmsrl(MSR_FS_BASE, old_base); 1202 wrmsrl(MSR_FS_BASE, 1); 1203 loadsegment(fs, 0); 1204 rdmsrl(MSR_FS_BASE, tmp); 1205 if (tmp != 0) 1206 set_cpu_bug(c, X86_BUG_NULL_SEG); 1207 wrmsrl(MSR_FS_BASE, old_base); 1208 #endif 1209 } 1210 1211 static void generic_identify(struct cpuinfo_x86 *c) 1212 { 1213 c->extended_cpuid_level = 0; 1214 1215 if (!have_cpuid_p()) 1216 identify_cpu_without_cpuid(c); 1217 1218 /* cyrix could have cpuid enabled via c_identify()*/ 1219 if (!have_cpuid_p()) 1220 return; 1221 1222 cpu_detect(c); 1223 1224 get_cpu_vendor(c); 1225 1226 get_cpu_cap(c); 1227 1228 get_cpu_address_sizes(c); 1229 1230 if (c->cpuid_level >= 0x00000001) { 1231 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1232 #ifdef CONFIG_X86_32 1233 # ifdef CONFIG_SMP 1234 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1235 # else 1236 c->apicid = c->initial_apicid; 1237 # endif 1238 #endif 1239 c->phys_proc_id = c->initial_apicid; 1240 } 1241 1242 get_model_name(c); /* Default name */ 1243 1244 detect_null_seg_behavior(c); 1245 1246 /* 1247 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1248 * systems that run Linux at CPL > 0 may or may not have the 1249 * issue, but, even if they have the issue, there's absolutely 1250 * nothing we can do about it because we can't use the real IRET 1251 * instruction. 1252 * 1253 * NB: For the time being, only 32-bit kernels support 1254 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1255 * whether to apply espfix using paravirt hooks. If any 1256 * non-paravirt system ever shows up that does *not* have the 1257 * ESPFIX issue, we can change this. 1258 */ 1259 #ifdef CONFIG_X86_32 1260 # ifdef CONFIG_PARAVIRT_XXL 1261 do { 1262 extern void native_iret(void); 1263 if (pv_ops.cpu.iret == native_iret) 1264 set_cpu_bug(c, X86_BUG_ESPFIX); 1265 } while (0); 1266 # else 1267 set_cpu_bug(c, X86_BUG_ESPFIX); 1268 # endif 1269 #endif 1270 } 1271 1272 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1273 { 1274 /* 1275 * The heavy lifting of max_rmid and cache_occ_scale are handled 1276 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1277 * in case CQM bits really aren't there in this CPU. 1278 */ 1279 if (c != &boot_cpu_data) { 1280 boot_cpu_data.x86_cache_max_rmid = 1281 min(boot_cpu_data.x86_cache_max_rmid, 1282 c->x86_cache_max_rmid); 1283 } 1284 } 1285 1286 /* 1287 * Validate that ACPI/mptables have the same information about the 1288 * effective APIC id and update the package map. 1289 */ 1290 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1291 { 1292 #ifdef CONFIG_SMP 1293 unsigned int apicid, cpu = smp_processor_id(); 1294 1295 apicid = apic->cpu_present_to_apicid(cpu); 1296 1297 if (apicid != c->apicid) { 1298 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1299 cpu, apicid, c->initial_apicid); 1300 } 1301 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1302 #else 1303 c->logical_proc_id = 0; 1304 #endif 1305 } 1306 1307 /* 1308 * This does the hard work of actually picking apart the CPU stuff... 1309 */ 1310 static void identify_cpu(struct cpuinfo_x86 *c) 1311 { 1312 int i; 1313 1314 c->loops_per_jiffy = loops_per_jiffy; 1315 c->x86_cache_size = 0; 1316 c->x86_vendor = X86_VENDOR_UNKNOWN; 1317 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1318 c->x86_vendor_id[0] = '\0'; /* Unset */ 1319 c->x86_model_id[0] = '\0'; /* Unset */ 1320 c->x86_max_cores = 1; 1321 c->x86_coreid_bits = 0; 1322 c->cu_id = 0xff; 1323 #ifdef CONFIG_X86_64 1324 c->x86_clflush_size = 64; 1325 c->x86_phys_bits = 36; 1326 c->x86_virt_bits = 48; 1327 #else 1328 c->cpuid_level = -1; /* CPUID not detected */ 1329 c->x86_clflush_size = 32; 1330 c->x86_phys_bits = 32; 1331 c->x86_virt_bits = 32; 1332 #endif 1333 c->x86_cache_alignment = c->x86_clflush_size; 1334 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1335 1336 generic_identify(c); 1337 1338 if (this_cpu->c_identify) 1339 this_cpu->c_identify(c); 1340 1341 /* Clear/Set all flags overridden by options, after probe */ 1342 apply_forced_caps(c); 1343 1344 #ifdef CONFIG_X86_64 1345 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1346 #endif 1347 1348 /* 1349 * Vendor-specific initialization. In this section we 1350 * canonicalize the feature flags, meaning if there are 1351 * features a certain CPU supports which CPUID doesn't 1352 * tell us, CPUID claiming incorrect flags, or other bugs, 1353 * we handle them here. 1354 * 1355 * At the end of this section, c->x86_capability better 1356 * indicate the features this CPU genuinely supports! 1357 */ 1358 if (this_cpu->c_init) 1359 this_cpu->c_init(c); 1360 1361 /* Disable the PN if appropriate */ 1362 squash_the_stupid_serial_number(c); 1363 1364 /* Set up SMEP/SMAP/UMIP */ 1365 setup_smep(c); 1366 setup_smap(c); 1367 setup_umip(c); 1368 1369 /* 1370 * The vendor-specific functions might have changed features. 1371 * Now we do "generic changes." 1372 */ 1373 1374 /* Filter out anything that depends on CPUID levels we don't have */ 1375 filter_cpuid_features(c, true); 1376 1377 /* If the model name is still unset, do table lookup. */ 1378 if (!c->x86_model_id[0]) { 1379 const char *p; 1380 p = table_lookup_model(c); 1381 if (p) 1382 strcpy(c->x86_model_id, p); 1383 else 1384 /* Last resort... */ 1385 sprintf(c->x86_model_id, "%02x/%02x", 1386 c->x86, c->x86_model); 1387 } 1388 1389 #ifdef CONFIG_X86_64 1390 detect_ht(c); 1391 #endif 1392 1393 x86_init_rdrand(c); 1394 x86_init_cache_qos(c); 1395 setup_pku(c); 1396 1397 /* 1398 * Clear/Set all flags overridden by options, need do it 1399 * before following smp all cpus cap AND. 1400 */ 1401 apply_forced_caps(c); 1402 1403 /* 1404 * On SMP, boot_cpu_data holds the common feature set between 1405 * all CPUs; so make sure that we indicate which features are 1406 * common between the CPUs. The first time this routine gets 1407 * executed, c == &boot_cpu_data. 1408 */ 1409 if (c != &boot_cpu_data) { 1410 /* AND the already accumulated flags with these */ 1411 for (i = 0; i < NCAPINTS; i++) 1412 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1413 1414 /* OR, i.e. replicate the bug flags */ 1415 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1416 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1417 } 1418 1419 /* Init Machine Check Exception if available. */ 1420 mcheck_cpu_init(c); 1421 1422 select_idle_routine(c); 1423 1424 #ifdef CONFIG_NUMA 1425 numa_add_cpu(smp_processor_id()); 1426 #endif 1427 } 1428 1429 /* 1430 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1431 * on 32-bit kernels: 1432 */ 1433 #ifdef CONFIG_X86_32 1434 void enable_sep_cpu(void) 1435 { 1436 struct tss_struct *tss; 1437 int cpu; 1438 1439 if (!boot_cpu_has(X86_FEATURE_SEP)) 1440 return; 1441 1442 cpu = get_cpu(); 1443 tss = &per_cpu(cpu_tss_rw, cpu); 1444 1445 /* 1446 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1447 * see the big comment in struct x86_hw_tss's definition. 1448 */ 1449 1450 tss->x86_tss.ss1 = __KERNEL_CS; 1451 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1452 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1453 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1454 1455 put_cpu(); 1456 } 1457 #endif 1458 1459 void __init identify_boot_cpu(void) 1460 { 1461 identify_cpu(&boot_cpu_data); 1462 #ifdef CONFIG_X86_32 1463 sysenter_setup(); 1464 enable_sep_cpu(); 1465 #endif 1466 cpu_detect_tlb(&boot_cpu_data); 1467 } 1468 1469 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1470 { 1471 BUG_ON(c == &boot_cpu_data); 1472 identify_cpu(c); 1473 #ifdef CONFIG_X86_32 1474 enable_sep_cpu(); 1475 #endif 1476 mtrr_ap_init(); 1477 validate_apic_and_package_id(c); 1478 x86_spec_ctrl_setup_ap(); 1479 } 1480 1481 static __init int setup_noclflush(char *arg) 1482 { 1483 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1484 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1485 return 1; 1486 } 1487 __setup("noclflush", setup_noclflush); 1488 1489 void print_cpu_info(struct cpuinfo_x86 *c) 1490 { 1491 const char *vendor = NULL; 1492 1493 if (c->x86_vendor < X86_VENDOR_NUM) { 1494 vendor = this_cpu->c_vendor; 1495 } else { 1496 if (c->cpuid_level >= 0) 1497 vendor = c->x86_vendor_id; 1498 } 1499 1500 if (vendor && !strstr(c->x86_model_id, vendor)) 1501 pr_cont("%s ", vendor); 1502 1503 if (c->x86_model_id[0]) 1504 pr_cont("%s", c->x86_model_id); 1505 else 1506 pr_cont("%d86", c->x86); 1507 1508 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1509 1510 if (c->x86_stepping || c->cpuid_level >= 0) 1511 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1512 else 1513 pr_cont(")\n"); 1514 } 1515 1516 /* 1517 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1518 * But we need to keep a dummy __setup around otherwise it would 1519 * show up as an environment variable for init. 1520 */ 1521 static __init int setup_clearcpuid(char *arg) 1522 { 1523 return 1; 1524 } 1525 __setup("clearcpuid=", setup_clearcpuid); 1526 1527 #ifdef CONFIG_X86_64 1528 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1529 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1530 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1531 1532 /* 1533 * The following percpu variables are hot. Align current_task to 1534 * cacheline size such that they fall in the same cacheline. 1535 */ 1536 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1537 &init_task; 1538 EXPORT_PER_CPU_SYMBOL(current_task); 1539 1540 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1541 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1542 1543 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1544 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1545 1546 /* May not be marked __init: used by software suspend */ 1547 void syscall_init(void) 1548 { 1549 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1550 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1551 1552 #ifdef CONFIG_IA32_EMULATION 1553 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1554 /* 1555 * This only works on Intel CPUs. 1556 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1557 * This does not cause SYSENTER to jump to the wrong location, because 1558 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1559 */ 1560 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1561 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1562 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1563 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1564 #else 1565 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1566 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1567 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1568 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1569 #endif 1570 1571 /* Flags to clear on syscall */ 1572 wrmsrl(MSR_SYSCALL_MASK, 1573 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1574 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1575 } 1576 1577 DEFINE_PER_CPU(int, debug_stack_usage); 1578 DEFINE_PER_CPU(u32, debug_idt_ctr); 1579 1580 void debug_stack_set_zero(void) 1581 { 1582 this_cpu_inc(debug_idt_ctr); 1583 load_current_idt(); 1584 } 1585 NOKPROBE_SYMBOL(debug_stack_set_zero); 1586 1587 void debug_stack_reset(void) 1588 { 1589 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1590 return; 1591 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1592 load_current_idt(); 1593 } 1594 NOKPROBE_SYMBOL(debug_stack_reset); 1595 1596 #else /* CONFIG_X86_64 */ 1597 1598 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1599 EXPORT_PER_CPU_SYMBOL(current_task); 1600 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1601 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1602 1603 /* 1604 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1605 * the top of the kernel stack. Use an extra percpu variable to track the 1606 * top of the kernel stack directly. 1607 */ 1608 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1609 (unsigned long)&init_thread_union + THREAD_SIZE; 1610 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1611 1612 #ifdef CONFIG_STACKPROTECTOR 1613 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1614 #endif 1615 1616 #endif /* CONFIG_X86_64 */ 1617 1618 /* 1619 * Clear all 6 debug registers: 1620 */ 1621 static void clear_all_debug_regs(void) 1622 { 1623 int i; 1624 1625 for (i = 0; i < 8; i++) { 1626 /* Ignore db4, db5 */ 1627 if ((i == 4) || (i == 5)) 1628 continue; 1629 1630 set_debugreg(0, i); 1631 } 1632 } 1633 1634 #ifdef CONFIG_KGDB 1635 /* 1636 * Restore debug regs if using kgdbwait and you have a kernel debugger 1637 * connection established. 1638 */ 1639 static void dbg_restore_debug_regs(void) 1640 { 1641 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1642 arch_kgdb_ops.correct_hw_break(); 1643 } 1644 #else /* ! CONFIG_KGDB */ 1645 #define dbg_restore_debug_regs() 1646 #endif /* ! CONFIG_KGDB */ 1647 1648 static void wait_for_master_cpu(int cpu) 1649 { 1650 #ifdef CONFIG_SMP 1651 /* 1652 * wait for ACK from master CPU before continuing 1653 * with AP initialization 1654 */ 1655 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1656 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1657 cpu_relax(); 1658 #endif 1659 } 1660 1661 #ifdef CONFIG_X86_64 1662 static void setup_getcpu(int cpu) 1663 { 1664 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1665 struct desc_struct d = { }; 1666 1667 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1668 write_rdtscp_aux(cpudata); 1669 1670 /* Store CPU and node number in limit. */ 1671 d.limit0 = cpudata; 1672 d.limit1 = cpudata >> 16; 1673 1674 d.type = 5; /* RO data, expand down, accessed */ 1675 d.dpl = 3; /* Visible to user code */ 1676 d.s = 1; /* Not a system segment */ 1677 d.p = 1; /* Present */ 1678 d.d = 1; /* 32-bit */ 1679 1680 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1681 } 1682 #endif 1683 1684 /* 1685 * cpu_init() initializes state that is per-CPU. Some data is already 1686 * initialized (naturally) in the bootstrap process, such as the GDT 1687 * and IDT. We reload them nevertheless, this function acts as a 1688 * 'CPU state barrier', nothing should get across. 1689 */ 1690 #ifdef CONFIG_X86_64 1691 1692 void cpu_init(void) 1693 { 1694 int cpu = raw_smp_processor_id(); 1695 struct task_struct *me; 1696 struct tss_struct *t; 1697 int i; 1698 1699 wait_for_master_cpu(cpu); 1700 1701 /* 1702 * Initialize the CR4 shadow before doing anything that could 1703 * try to read it. 1704 */ 1705 cr4_init_shadow(); 1706 1707 if (cpu) 1708 load_ucode_ap(); 1709 1710 t = &per_cpu(cpu_tss_rw, cpu); 1711 1712 #ifdef CONFIG_NUMA 1713 if (this_cpu_read(numa_node) == 0 && 1714 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1715 set_numa_node(early_cpu_to_node(cpu)); 1716 #endif 1717 setup_getcpu(cpu); 1718 1719 me = current; 1720 1721 pr_debug("Initializing CPU#%d\n", cpu); 1722 1723 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1724 1725 /* 1726 * Initialize the per-CPU GDT with the boot GDT, 1727 * and set up the GDT descriptor: 1728 */ 1729 1730 switch_to_new_gdt(cpu); 1731 loadsegment(fs, 0); 1732 1733 load_current_idt(); 1734 1735 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1736 syscall_init(); 1737 1738 wrmsrl(MSR_FS_BASE, 0); 1739 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1740 barrier(); 1741 1742 x86_configure_nx(); 1743 x2apic_setup(); 1744 1745 /* 1746 * set up and load the per-CPU TSS 1747 */ 1748 if (!t->x86_tss.ist[0]) { 1749 t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1750 t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1751 t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1752 t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1753 } 1754 1755 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1756 1757 /* 1758 * <= is required because the CPU will access up to 1759 * 8 bits beyond the end of the IO permission bitmap. 1760 */ 1761 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1762 t->io_bitmap[i] = ~0UL; 1763 1764 mmgrab(&init_mm); 1765 me->active_mm = &init_mm; 1766 BUG_ON(me->mm); 1767 initialize_tlbstate_and_flush(); 1768 enter_lazy_tlb(&init_mm, me); 1769 1770 /* 1771 * Initialize the TSS. sp0 points to the entry trampoline stack 1772 * regardless of what task is running. 1773 */ 1774 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1775 load_TR_desc(); 1776 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1777 1778 load_mm_ldt(&init_mm); 1779 1780 clear_all_debug_regs(); 1781 dbg_restore_debug_regs(); 1782 1783 fpu__init_cpu(); 1784 1785 if (is_uv_system()) 1786 uv_cpu_init(); 1787 1788 load_fixmap_gdt(cpu); 1789 } 1790 1791 #else 1792 1793 void cpu_init(void) 1794 { 1795 int cpu = smp_processor_id(); 1796 struct task_struct *curr = current; 1797 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1798 1799 wait_for_master_cpu(cpu); 1800 1801 /* 1802 * Initialize the CR4 shadow before doing anything that could 1803 * try to read it. 1804 */ 1805 cr4_init_shadow(); 1806 1807 show_ucode_info_early(); 1808 1809 pr_info("Initializing CPU#%d\n", cpu); 1810 1811 if (cpu_feature_enabled(X86_FEATURE_VME) || 1812 boot_cpu_has(X86_FEATURE_TSC) || 1813 boot_cpu_has(X86_FEATURE_DE)) 1814 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1815 1816 load_current_idt(); 1817 switch_to_new_gdt(cpu); 1818 1819 /* 1820 * Set up and load the per-CPU TSS and LDT 1821 */ 1822 mmgrab(&init_mm); 1823 curr->active_mm = &init_mm; 1824 BUG_ON(curr->mm); 1825 initialize_tlbstate_and_flush(); 1826 enter_lazy_tlb(&init_mm, curr); 1827 1828 /* 1829 * Initialize the TSS. sp0 points to the entry trampoline stack 1830 * regardless of what task is running. 1831 */ 1832 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1833 load_TR_desc(); 1834 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1835 1836 load_mm_ldt(&init_mm); 1837 1838 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1839 1840 #ifdef CONFIG_DOUBLEFAULT 1841 /* Set up doublefault TSS pointer in the GDT */ 1842 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1843 #endif 1844 1845 clear_all_debug_regs(); 1846 dbg_restore_debug_regs(); 1847 1848 fpu__init_cpu(); 1849 1850 load_fixmap_gdt(cpu); 1851 } 1852 #endif 1853 1854 /* 1855 * The microcode loader calls this upon late microcode load to recheck features, 1856 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1857 * hotplug lock. 1858 */ 1859 void microcode_check(void) 1860 { 1861 struct cpuinfo_x86 info; 1862 1863 perf_check_microcode(); 1864 1865 /* Reload CPUID max function as it might've changed. */ 1866 info.cpuid_level = cpuid_eax(0); 1867 1868 /* 1869 * Copy all capability leafs to pick up the synthetic ones so that 1870 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1871 * get overwritten in get_cpu_cap(). 1872 */ 1873 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1874 1875 get_cpu_cap(&info); 1876 1877 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1878 return; 1879 1880 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1881 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1882 } 1883