1 #include <linux/init.h> 2 #include <linux/kernel.h> 3 #include <linux/sched.h> 4 #include <linux/string.h> 5 #include <linux/bootmem.h> 6 #include <linux/bitops.h> 7 #include <linux/module.h> 8 #include <linux/kgdb.h> 9 #include <linux/topology.h> 10 #include <linux/delay.h> 11 #include <linux/smp.h> 12 #include <linux/percpu.h> 13 #include <asm/i387.h> 14 #include <asm/msr.h> 15 #include <asm/io.h> 16 #include <asm/linkage.h> 17 #include <asm/mmu_context.h> 18 #include <asm/mtrr.h> 19 #include <asm/mce.h> 20 #include <asm/pat.h> 21 #include <asm/asm.h> 22 #include <asm/numa.h> 23 #include <asm/smp.h> 24 #ifdef CONFIG_X86_LOCAL_APIC 25 #include <asm/mpspec.h> 26 #include <asm/apic.h> 27 #include <mach_apic.h> 28 #include <asm/genapic.h> 29 #endif 30 31 #include <asm/pda.h> 32 #include <asm/pgtable.h> 33 #include <asm/processor.h> 34 #include <asm/desc.h> 35 #include <asm/atomic.h> 36 #include <asm/proto.h> 37 #include <asm/sections.h> 38 #include <asm/setup.h> 39 #include <asm/hypervisor.h> 40 41 #include "cpu.h" 42 43 #ifdef CONFIG_X86_64 44 45 /* all of these masks are initialized in setup_cpu_local_masks() */ 46 cpumask_var_t cpu_callin_mask; 47 cpumask_var_t cpu_callout_mask; 48 cpumask_var_t cpu_initialized_mask; 49 50 /* representing cpus for which sibling maps can be computed */ 51 cpumask_var_t cpu_sibling_setup_mask; 52 53 #else /* CONFIG_X86_32 */ 54 55 cpumask_t cpu_callin_map; 56 cpumask_t cpu_callout_map; 57 cpumask_t cpu_initialized; 58 cpumask_t cpu_sibling_setup_map; 59 60 #endif /* CONFIG_X86_32 */ 61 62 63 static struct cpu_dev *this_cpu __cpuinitdata; 64 65 #ifdef CONFIG_X86_64 66 /* We need valid kernel segments for data and code in long mode too 67 * IRET will check the segment types kkeil 2000/10/28 68 * Also sysret mandates a special GDT layout 69 */ 70 /* The TLS descriptors are currently at a different place compared to i386. 71 Hopefully nobody expects them at a fixed place (Wine?) */ 72 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { 73 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, 74 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, 75 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, 76 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, 77 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, 78 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, 79 } }; 80 #else 81 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 82 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 83 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 84 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 85 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 86 /* 87 * Segments used for calling PnP BIOS have byte granularity. 88 * They code segments and data segments have fixed 64k limits, 89 * the transfer segment sizes are set at run time. 90 */ 91 /* 32-bit code */ 92 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 93 /* 16-bit code */ 94 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 95 /* 16-bit data */ 96 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 97 /* 16-bit data */ 98 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 99 /* 16-bit data */ 100 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 101 /* 102 * The APM segments have byte granularity and their bases 103 * are set at run time. All have 64k limits. 104 */ 105 /* 32-bit code */ 106 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 107 /* 16-bit code */ 108 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 109 /* data */ 110 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 111 112 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, 113 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, 114 } }; 115 #endif 116 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 117 118 #ifdef CONFIG_X86_32 119 static int cachesize_override __cpuinitdata = -1; 120 static int disable_x86_serial_nr __cpuinitdata = 1; 121 122 static int __init cachesize_setup(char *str) 123 { 124 get_option(&str, &cachesize_override); 125 return 1; 126 } 127 __setup("cachesize=", cachesize_setup); 128 129 static int __init x86_fxsr_setup(char *s) 130 { 131 setup_clear_cpu_cap(X86_FEATURE_FXSR); 132 setup_clear_cpu_cap(X86_FEATURE_XMM); 133 return 1; 134 } 135 __setup("nofxsr", x86_fxsr_setup); 136 137 static int __init x86_sep_setup(char *s) 138 { 139 setup_clear_cpu_cap(X86_FEATURE_SEP); 140 return 1; 141 } 142 __setup("nosep", x86_sep_setup); 143 144 /* Standard macro to see if a specific flag is changeable */ 145 static inline int flag_is_changeable_p(u32 flag) 146 { 147 u32 f1, f2; 148 149 /* 150 * Cyrix and IDT cpus allow disabling of CPUID 151 * so the code below may return different results 152 * when it is executed before and after enabling 153 * the CPUID. Add "volatile" to not allow gcc to 154 * optimize the subsequent calls to this function. 155 */ 156 asm volatile ("pushfl\n\t" 157 "pushfl\n\t" 158 "popl %0\n\t" 159 "movl %0,%1\n\t" 160 "xorl %2,%0\n\t" 161 "pushl %0\n\t" 162 "popfl\n\t" 163 "pushfl\n\t" 164 "popl %0\n\t" 165 "popfl\n\t" 166 : "=&r" (f1), "=&r" (f2) 167 : "ir" (flag)); 168 169 return ((f1^f2) & flag) != 0; 170 } 171 172 /* Probe for the CPUID instruction */ 173 static int __cpuinit have_cpuid_p(void) 174 { 175 return flag_is_changeable_p(X86_EFLAGS_ID); 176 } 177 178 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 179 { 180 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { 181 /* Disable processor serial number */ 182 unsigned long lo, hi; 183 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 184 lo |= 0x200000; 185 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 186 printk(KERN_NOTICE "CPU serial number disabled.\n"); 187 clear_cpu_cap(c, X86_FEATURE_PN); 188 189 /* Disabling the serial number may affect the cpuid level */ 190 c->cpuid_level = cpuid_eax(0); 191 } 192 } 193 194 static int __init x86_serial_nr_setup(char *s) 195 { 196 disable_x86_serial_nr = 0; 197 return 1; 198 } 199 __setup("serialnumber", x86_serial_nr_setup); 200 #else 201 static inline int flag_is_changeable_p(u32 flag) 202 { 203 return 1; 204 } 205 /* Probe for the CPUID instruction */ 206 static inline int have_cpuid_p(void) 207 { 208 return 1; 209 } 210 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 211 { 212 } 213 #endif 214 215 /* 216 * Naming convention should be: <Name> [(<Codename>)] 217 * This table only is used unless init_<vendor>() below doesn't set it; 218 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used 219 * 220 */ 221 222 /* Look up CPU names by table lookup. */ 223 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) 224 { 225 struct cpu_model_info *info; 226 227 if (c->x86_model >= 16) 228 return NULL; /* Range check */ 229 230 if (!this_cpu) 231 return NULL; 232 233 info = this_cpu->c_models; 234 235 while (info && info->family) { 236 if (info->family == c->x86) 237 return info->model_names[c->x86_model]; 238 info++; 239 } 240 return NULL; /* Not found */ 241 } 242 243 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; 244 245 /* Current gdt points %fs at the "master" per-cpu area: after this, 246 * it's on the real one. */ 247 void switch_to_new_gdt(void) 248 { 249 struct desc_ptr gdt_descr; 250 251 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); 252 gdt_descr.size = GDT_SIZE - 1; 253 load_gdt(&gdt_descr); 254 #ifdef CONFIG_X86_32 255 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); 256 #endif 257 } 258 259 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 260 261 static void __cpuinit default_init(struct cpuinfo_x86 *c) 262 { 263 #ifdef CONFIG_X86_64 264 display_cacheinfo(c); 265 #else 266 /* Not much we can do here... */ 267 /* Check if at least it has cpuid */ 268 if (c->cpuid_level == -1) { 269 /* No cpuid. It must be an ancient CPU */ 270 if (c->x86 == 4) 271 strcpy(c->x86_model_id, "486"); 272 else if (c->x86 == 3) 273 strcpy(c->x86_model_id, "386"); 274 } 275 #endif 276 } 277 278 static struct cpu_dev __cpuinitdata default_cpu = { 279 .c_init = default_init, 280 .c_vendor = "Unknown", 281 .c_x86_vendor = X86_VENDOR_UNKNOWN, 282 }; 283 284 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 285 { 286 unsigned int *v; 287 char *p, *q; 288 289 if (c->extended_cpuid_level < 0x80000004) 290 return; 291 292 v = (unsigned int *) c->x86_model_id; 293 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 294 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 295 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 296 c->x86_model_id[48] = 0; 297 298 /* Intel chips right-justify this string for some dumb reason; 299 undo that brain damage */ 300 p = q = &c->x86_model_id[0]; 301 while (*p == ' ') 302 p++; 303 if (p != q) { 304 while (*p) 305 *q++ = *p++; 306 while (q <= &c->x86_model_id[48]) 307 *q++ = '\0'; /* Zero-pad the rest */ 308 } 309 } 310 311 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 312 { 313 unsigned int n, dummy, ebx, ecx, edx, l2size; 314 315 n = c->extended_cpuid_level; 316 317 if (n >= 0x80000005) { 318 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 319 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 320 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 321 c->x86_cache_size = (ecx>>24) + (edx>>24); 322 #ifdef CONFIG_X86_64 323 /* On K8 L1 TLB is inclusive, so don't count it */ 324 c->x86_tlbsize = 0; 325 #endif 326 } 327 328 if (n < 0x80000006) /* Some chips just has a large L1. */ 329 return; 330 331 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 332 l2size = ecx >> 16; 333 334 #ifdef CONFIG_X86_64 335 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 336 #else 337 /* do processor-specific cache resizing */ 338 if (this_cpu->c_size_cache) 339 l2size = this_cpu->c_size_cache(c, l2size); 340 341 /* Allow user to override all this if necessary. */ 342 if (cachesize_override != -1) 343 l2size = cachesize_override; 344 345 if (l2size == 0) 346 return; /* Again, no L2 cache is possible */ 347 #endif 348 349 c->x86_cache_size = l2size; 350 351 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 352 l2size, ecx & 0xFF); 353 } 354 355 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 356 { 357 #ifdef CONFIG_X86_HT 358 u32 eax, ebx, ecx, edx; 359 int index_msb, core_bits; 360 361 if (!cpu_has(c, X86_FEATURE_HT)) 362 return; 363 364 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 365 goto out; 366 367 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 368 return; 369 370 cpuid(1, &eax, &ebx, &ecx, &edx); 371 372 smp_num_siblings = (ebx & 0xff0000) >> 16; 373 374 if (smp_num_siblings == 1) { 375 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 376 } else if (smp_num_siblings > 1) { 377 378 if (smp_num_siblings > nr_cpu_ids) { 379 printk(KERN_WARNING "CPU: Unsupported number of siblings %d", 380 smp_num_siblings); 381 smp_num_siblings = 1; 382 return; 383 } 384 385 index_msb = get_count_order(smp_num_siblings); 386 #ifdef CONFIG_X86_64 387 c->phys_proc_id = phys_pkg_id(index_msb); 388 #else 389 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); 390 #endif 391 392 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 393 394 index_msb = get_count_order(smp_num_siblings); 395 396 core_bits = get_count_order(c->x86_max_cores); 397 398 #ifdef CONFIG_X86_64 399 c->cpu_core_id = phys_pkg_id(index_msb) & 400 ((1 << core_bits) - 1); 401 #else 402 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & 403 ((1 << core_bits) - 1); 404 #endif 405 } 406 407 out: 408 if ((c->x86_max_cores * smp_num_siblings) > 1) { 409 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 410 c->phys_proc_id); 411 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 412 c->cpu_core_id); 413 } 414 #endif 415 } 416 417 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 418 { 419 char *v = c->x86_vendor_id; 420 int i; 421 static int printed; 422 423 for (i = 0; i < X86_VENDOR_NUM; i++) { 424 if (!cpu_devs[i]) 425 break; 426 427 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 428 (cpu_devs[i]->c_ident[1] && 429 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 430 this_cpu = cpu_devs[i]; 431 c->x86_vendor = this_cpu->c_x86_vendor; 432 return; 433 } 434 } 435 436 if (!printed) { 437 printed++; 438 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); 439 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 440 } 441 442 c->x86_vendor = X86_VENDOR_UNKNOWN; 443 this_cpu = &default_cpu; 444 } 445 446 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 447 { 448 /* Get vendor name */ 449 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 450 (unsigned int *)&c->x86_vendor_id[0], 451 (unsigned int *)&c->x86_vendor_id[8], 452 (unsigned int *)&c->x86_vendor_id[4]); 453 454 c->x86 = 4; 455 /* Intel-defined flags: level 0x00000001 */ 456 if (c->cpuid_level >= 0x00000001) { 457 u32 junk, tfms, cap0, misc; 458 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 459 c->x86 = (tfms >> 8) & 0xf; 460 c->x86_model = (tfms >> 4) & 0xf; 461 c->x86_mask = tfms & 0xf; 462 if (c->x86 == 0xf) 463 c->x86 += (tfms >> 20) & 0xff; 464 if (c->x86 >= 0x6) 465 c->x86_model += ((tfms >> 16) & 0xf) << 4; 466 if (cap0 & (1<<19)) { 467 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 468 c->x86_cache_alignment = c->x86_clflush_size; 469 } 470 } 471 } 472 473 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 474 { 475 u32 tfms, xlvl; 476 u32 ebx; 477 478 /* Intel-defined flags: level 0x00000001 */ 479 if (c->cpuid_level >= 0x00000001) { 480 u32 capability, excap; 481 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 482 c->x86_capability[0] = capability; 483 c->x86_capability[4] = excap; 484 } 485 486 /* AMD-defined flags: level 0x80000001 */ 487 xlvl = cpuid_eax(0x80000000); 488 c->extended_cpuid_level = xlvl; 489 if ((xlvl & 0xffff0000) == 0x80000000) { 490 if (xlvl >= 0x80000001) { 491 c->x86_capability[1] = cpuid_edx(0x80000001); 492 c->x86_capability[6] = cpuid_ecx(0x80000001); 493 } 494 } 495 496 #ifdef CONFIG_X86_64 497 if (c->extended_cpuid_level >= 0x80000008) { 498 u32 eax = cpuid_eax(0x80000008); 499 500 c->x86_virt_bits = (eax >> 8) & 0xff; 501 c->x86_phys_bits = eax & 0xff; 502 } 503 #endif 504 505 if (c->extended_cpuid_level >= 0x80000007) 506 c->x86_power = cpuid_edx(0x80000007); 507 508 } 509 510 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 511 { 512 #ifdef CONFIG_X86_32 513 int i; 514 515 /* 516 * First of all, decide if this is a 486 or higher 517 * It's a 486 if we can modify the AC flag 518 */ 519 if (flag_is_changeable_p(X86_EFLAGS_AC)) 520 c->x86 = 4; 521 else 522 c->x86 = 3; 523 524 for (i = 0; i < X86_VENDOR_NUM; i++) 525 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 526 c->x86_vendor_id[0] = 0; 527 cpu_devs[i]->c_identify(c); 528 if (c->x86_vendor_id[0]) { 529 get_cpu_vendor(c); 530 break; 531 } 532 } 533 #endif 534 } 535 536 /* 537 * Do minimum CPU detection early. 538 * Fields really needed: vendor, cpuid_level, family, model, mask, 539 * cache alignment. 540 * The others are not touched to avoid unwanted side effects. 541 * 542 * WARNING: this function is only called on the BP. Don't add code here 543 * that is supposed to run on all CPUs. 544 */ 545 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 546 { 547 #ifdef CONFIG_X86_64 548 c->x86_clflush_size = 64; 549 #else 550 c->x86_clflush_size = 32; 551 #endif 552 c->x86_cache_alignment = c->x86_clflush_size; 553 554 memset(&c->x86_capability, 0, sizeof c->x86_capability); 555 c->extended_cpuid_level = 0; 556 557 if (!have_cpuid_p()) 558 identify_cpu_without_cpuid(c); 559 560 /* cyrix could have cpuid enabled via c_identify()*/ 561 if (!have_cpuid_p()) 562 return; 563 564 cpu_detect(c); 565 566 get_cpu_vendor(c); 567 568 get_cpu_cap(c); 569 570 if (this_cpu->c_early_init) 571 this_cpu->c_early_init(c); 572 573 validate_pat_support(c); 574 575 #ifdef CONFIG_SMP 576 c->cpu_index = boot_cpu_id; 577 #endif 578 } 579 580 void __init early_cpu_init(void) 581 { 582 struct cpu_dev **cdev; 583 int count = 0; 584 585 printk("KERNEL supported cpus:\n"); 586 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 587 struct cpu_dev *cpudev = *cdev; 588 unsigned int j; 589 590 if (count >= X86_VENDOR_NUM) 591 break; 592 cpu_devs[count] = cpudev; 593 count++; 594 595 for (j = 0; j < 2; j++) { 596 if (!cpudev->c_ident[j]) 597 continue; 598 printk(" %s %s\n", cpudev->c_vendor, 599 cpudev->c_ident[j]); 600 } 601 } 602 603 early_identify_cpu(&boot_cpu_data); 604 } 605 606 /* 607 * The NOPL instruction is supposed to exist on all CPUs with 608 * family >= 6; unfortunately, that's not true in practice because 609 * of early VIA chips and (more importantly) broken virtualizers that 610 * are not easy to detect. In the latter case it doesn't even *fail* 611 * reliably, so probing for it doesn't even work. Disable it completely 612 * unless we can find a reliable way to detect all the broken cases. 613 */ 614 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 615 { 616 clear_cpu_cap(c, X86_FEATURE_NOPL); 617 } 618 619 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 620 { 621 c->extended_cpuid_level = 0; 622 623 if (!have_cpuid_p()) 624 identify_cpu_without_cpuid(c); 625 626 /* cyrix could have cpuid enabled via c_identify()*/ 627 if (!have_cpuid_p()) 628 return; 629 630 cpu_detect(c); 631 632 get_cpu_vendor(c); 633 634 get_cpu_cap(c); 635 636 if (c->cpuid_level >= 0x00000001) { 637 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 638 #ifdef CONFIG_X86_32 639 # ifdef CONFIG_X86_HT 640 c->apicid = phys_pkg_id(c->initial_apicid, 0); 641 # else 642 c->apicid = c->initial_apicid; 643 # endif 644 #endif 645 646 #ifdef CONFIG_X86_HT 647 c->phys_proc_id = c->initial_apicid; 648 #endif 649 } 650 651 get_model_name(c); /* Default name */ 652 653 init_scattered_cpuid_features(c); 654 detect_nopl(c); 655 } 656 657 /* 658 * This does the hard work of actually picking apart the CPU stuff... 659 */ 660 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 661 { 662 int i; 663 664 c->loops_per_jiffy = loops_per_jiffy; 665 c->x86_cache_size = -1; 666 c->x86_vendor = X86_VENDOR_UNKNOWN; 667 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 668 c->x86_vendor_id[0] = '\0'; /* Unset */ 669 c->x86_model_id[0] = '\0'; /* Unset */ 670 c->x86_max_cores = 1; 671 c->x86_coreid_bits = 0; 672 #ifdef CONFIG_X86_64 673 c->x86_clflush_size = 64; 674 #else 675 c->cpuid_level = -1; /* CPUID not detected */ 676 c->x86_clflush_size = 32; 677 #endif 678 c->x86_cache_alignment = c->x86_clflush_size; 679 memset(&c->x86_capability, 0, sizeof c->x86_capability); 680 681 generic_identify(c); 682 683 if (this_cpu->c_identify) 684 this_cpu->c_identify(c); 685 686 #ifdef CONFIG_X86_64 687 c->apicid = phys_pkg_id(0); 688 #endif 689 690 /* 691 * Vendor-specific initialization. In this section we 692 * canonicalize the feature flags, meaning if there are 693 * features a certain CPU supports which CPUID doesn't 694 * tell us, CPUID claiming incorrect flags, or other bugs, 695 * we handle them here. 696 * 697 * At the end of this section, c->x86_capability better 698 * indicate the features this CPU genuinely supports! 699 */ 700 if (this_cpu->c_init) 701 this_cpu->c_init(c); 702 703 /* Disable the PN if appropriate */ 704 squash_the_stupid_serial_number(c); 705 706 /* 707 * The vendor-specific functions might have changed features. Now 708 * we do "generic changes." 709 */ 710 711 /* If the model name is still unset, do table lookup. */ 712 if (!c->x86_model_id[0]) { 713 char *p; 714 p = table_lookup_model(c); 715 if (p) 716 strcpy(c->x86_model_id, p); 717 else 718 /* Last resort... */ 719 sprintf(c->x86_model_id, "%02x/%02x", 720 c->x86, c->x86_model); 721 } 722 723 #ifdef CONFIG_X86_64 724 detect_ht(c); 725 #endif 726 727 init_hypervisor(c); 728 /* 729 * On SMP, boot_cpu_data holds the common feature set between 730 * all CPUs; so make sure that we indicate which features are 731 * common between the CPUs. The first time this routine gets 732 * executed, c == &boot_cpu_data. 733 */ 734 if (c != &boot_cpu_data) { 735 /* AND the already accumulated flags with these */ 736 for (i = 0; i < NCAPINTS; i++) 737 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 738 } 739 740 /* Clear all flags overriden by options */ 741 for (i = 0; i < NCAPINTS; i++) 742 c->x86_capability[i] &= ~cleared_cpu_caps[i]; 743 744 #ifdef CONFIG_X86_MCE 745 /* Init Machine Check Exception if available. */ 746 mcheck_init(c); 747 #endif 748 749 select_idle_routine(c); 750 751 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 752 numa_add_cpu(smp_processor_id()); 753 #endif 754 } 755 756 #ifdef CONFIG_X86_64 757 static void vgetcpu_set_mode(void) 758 { 759 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 760 vgetcpu_mode = VGETCPU_RDTSCP; 761 else 762 vgetcpu_mode = VGETCPU_LSL; 763 } 764 #endif 765 766 void __init identify_boot_cpu(void) 767 { 768 identify_cpu(&boot_cpu_data); 769 #ifdef CONFIG_X86_32 770 sysenter_setup(); 771 enable_sep_cpu(); 772 #else 773 vgetcpu_set_mode(); 774 #endif 775 } 776 777 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 778 { 779 BUG_ON(c == &boot_cpu_data); 780 identify_cpu(c); 781 #ifdef CONFIG_X86_32 782 enable_sep_cpu(); 783 #endif 784 mtrr_ap_init(); 785 } 786 787 struct msr_range { 788 unsigned min; 789 unsigned max; 790 }; 791 792 static struct msr_range msr_range_array[] __cpuinitdata = { 793 { 0x00000000, 0x00000418}, 794 { 0xc0000000, 0xc000040b}, 795 { 0xc0010000, 0xc0010142}, 796 { 0xc0011000, 0xc001103b}, 797 }; 798 799 static void __cpuinit print_cpu_msr(void) 800 { 801 unsigned index; 802 u64 val; 803 int i; 804 unsigned index_min, index_max; 805 806 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 807 index_min = msr_range_array[i].min; 808 index_max = msr_range_array[i].max; 809 for (index = index_min; index < index_max; index++) { 810 if (rdmsrl_amd_safe(index, &val)) 811 continue; 812 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 813 } 814 } 815 } 816 817 static int show_msr __cpuinitdata; 818 static __init int setup_show_msr(char *arg) 819 { 820 int num; 821 822 get_option(&arg, &num); 823 824 if (num > 0) 825 show_msr = num; 826 return 1; 827 } 828 __setup("show_msr=", setup_show_msr); 829 830 static __init int setup_noclflush(char *arg) 831 { 832 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 833 return 1; 834 } 835 __setup("noclflush", setup_noclflush); 836 837 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 838 { 839 char *vendor = NULL; 840 841 if (c->x86_vendor < X86_VENDOR_NUM) 842 vendor = this_cpu->c_vendor; 843 else if (c->cpuid_level >= 0) 844 vendor = c->x86_vendor_id; 845 846 if (vendor && !strstr(c->x86_model_id, vendor)) 847 printk(KERN_CONT "%s ", vendor); 848 849 if (c->x86_model_id[0]) 850 printk(KERN_CONT "%s", c->x86_model_id); 851 else 852 printk(KERN_CONT "%d86", c->x86); 853 854 if (c->x86_mask || c->cpuid_level >= 0) 855 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 856 else 857 printk(KERN_CONT "\n"); 858 859 #ifdef CONFIG_SMP 860 if (c->cpu_index < show_msr) 861 print_cpu_msr(); 862 #else 863 if (show_msr) 864 print_cpu_msr(); 865 #endif 866 } 867 868 static __init int setup_disablecpuid(char *arg) 869 { 870 int bit; 871 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 872 setup_clear_cpu_cap(bit); 873 else 874 return 0; 875 return 1; 876 } 877 __setup("clearcpuid=", setup_disablecpuid); 878 879 #ifdef CONFIG_X86_64 880 struct x8664_pda **_cpu_pda __read_mostly; 881 EXPORT_SYMBOL(_cpu_pda); 882 883 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; 884 885 static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; 886 887 void __cpuinit pda_init(int cpu) 888 { 889 struct x8664_pda *pda = cpu_pda(cpu); 890 891 /* Setup up data that may be needed in __get_free_pages early */ 892 loadsegment(fs, 0); 893 loadsegment(gs, 0); 894 /* Memory clobbers used to order PDA accessed */ 895 mb(); 896 wrmsrl(MSR_GS_BASE, pda); 897 mb(); 898 899 pda->cpunumber = cpu; 900 pda->irqcount = -1; 901 pda->kernelstack = (unsigned long)stack_thread_info() - 902 PDA_STACKOFFSET + THREAD_SIZE; 903 pda->active_mm = &init_mm; 904 pda->mmu_state = 0; 905 906 if (cpu == 0) { 907 /* others are initialized in smpboot.c */ 908 pda->pcurrent = &init_task; 909 pda->irqstackptr = boot_cpu_stack; 910 pda->irqstackptr += IRQSTACKSIZE - 64; 911 } else { 912 if (!pda->irqstackptr) { 913 pda->irqstackptr = (char *) 914 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); 915 if (!pda->irqstackptr) 916 panic("cannot allocate irqstack for cpu %d", 917 cpu); 918 pda->irqstackptr += IRQSTACKSIZE - 64; 919 } 920 921 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) 922 pda->nodenumber = cpu_to_node(cpu); 923 } 924 } 925 926 static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + 927 DEBUG_STKSZ] __page_aligned_bss; 928 929 extern asmlinkage void ignore_sysret(void); 930 931 /* May not be marked __init: used by software suspend */ 932 void syscall_init(void) 933 { 934 /* 935 * LSTAR and STAR live in a bit strange symbiosis. 936 * They both write to the same internal register. STAR allows to 937 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 938 */ 939 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 940 wrmsrl(MSR_LSTAR, system_call); 941 wrmsrl(MSR_CSTAR, ignore_sysret); 942 943 #ifdef CONFIG_IA32_EMULATION 944 syscall32_cpu_init(); 945 #endif 946 947 /* Flags to clear on syscall */ 948 wrmsrl(MSR_SYSCALL_MASK, 949 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 950 } 951 952 unsigned long kernel_eflags; 953 954 /* 955 * Copies of the original ist values from the tss are only accessed during 956 * debugging, no special alignment required. 957 */ 958 DEFINE_PER_CPU(struct orig_ist, orig_ist); 959 960 #else 961 962 /* Make sure %fs is initialized properly in idle threads */ 963 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 964 { 965 memset(regs, 0, sizeof(struct pt_regs)); 966 regs->fs = __KERNEL_PERCPU; 967 return regs; 968 } 969 #endif 970 971 /* 972 * cpu_init() initializes state that is per-CPU. Some data is already 973 * initialized (naturally) in the bootstrap process, such as the GDT 974 * and IDT. We reload them nevertheless, this function acts as a 975 * 'CPU state barrier', nothing should get across. 976 * A lot of state is already set up in PDA init for 64 bit 977 */ 978 #ifdef CONFIG_X86_64 979 void __cpuinit cpu_init(void) 980 { 981 int cpu = stack_smp_processor_id(); 982 struct tss_struct *t = &per_cpu(init_tss, cpu); 983 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); 984 unsigned long v; 985 char *estacks = NULL; 986 struct task_struct *me; 987 int i; 988 989 /* CPU 0 is initialised in head64.c */ 990 if (cpu != 0) 991 pda_init(cpu); 992 else 993 estacks = boot_exception_stacks; 994 995 me = current; 996 997 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 998 panic("CPU#%d already initialized!\n", cpu); 999 1000 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1001 1002 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1003 1004 /* 1005 * Initialize the per-CPU GDT with the boot GDT, 1006 * and set up the GDT descriptor: 1007 */ 1008 1009 switch_to_new_gdt(); 1010 load_idt((const struct desc_ptr *)&idt_descr); 1011 1012 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1013 syscall_init(); 1014 1015 wrmsrl(MSR_FS_BASE, 0); 1016 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1017 barrier(); 1018 1019 check_efer(); 1020 if (cpu != 0 && x2apic) 1021 enable_x2apic(); 1022 1023 /* 1024 * set up and load the per-CPU TSS 1025 */ 1026 if (!orig_ist->ist[0]) { 1027 static const unsigned int order[N_EXCEPTION_STACKS] = { 1028 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, 1029 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER 1030 }; 1031 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1032 if (cpu) { 1033 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); 1034 if (!estacks) 1035 panic("Cannot allocate exception " 1036 "stack %ld %d\n", v, cpu); 1037 } 1038 estacks += PAGE_SIZE << order[v]; 1039 orig_ist->ist[v] = t->x86_tss.ist[v] = 1040 (unsigned long)estacks; 1041 } 1042 } 1043 1044 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1045 /* 1046 * <= is required because the CPU will access up to 1047 * 8 bits beyond the end of the IO permission bitmap. 1048 */ 1049 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1050 t->io_bitmap[i] = ~0UL; 1051 1052 atomic_inc(&init_mm.mm_count); 1053 me->active_mm = &init_mm; 1054 if (me->mm) 1055 BUG(); 1056 enter_lazy_tlb(&init_mm, me); 1057 1058 load_sp0(t, ¤t->thread); 1059 set_tss_desc(cpu, t); 1060 load_TR_desc(); 1061 load_LDT(&init_mm.context); 1062 1063 #ifdef CONFIG_KGDB 1064 /* 1065 * If the kgdb is connected no debug regs should be altered. This 1066 * is only applicable when KGDB and a KGDB I/O module are built 1067 * into the kernel and you are using early debugging with 1068 * kgdbwait. KGDB will control the kernel HW breakpoint registers. 1069 */ 1070 if (kgdb_connected && arch_kgdb_ops.correct_hw_break) 1071 arch_kgdb_ops.correct_hw_break(); 1072 else { 1073 #endif 1074 /* 1075 * Clear all 6 debug registers: 1076 */ 1077 1078 set_debugreg(0UL, 0); 1079 set_debugreg(0UL, 1); 1080 set_debugreg(0UL, 2); 1081 set_debugreg(0UL, 3); 1082 set_debugreg(0UL, 6); 1083 set_debugreg(0UL, 7); 1084 #ifdef CONFIG_KGDB 1085 /* If the kgdb is connected no debug regs should be altered. */ 1086 } 1087 #endif 1088 1089 fpu_init(); 1090 1091 raw_local_save_flags(kernel_eflags); 1092 1093 if (is_uv_system()) 1094 uv_cpu_init(); 1095 } 1096 1097 #else 1098 1099 void __cpuinit cpu_init(void) 1100 { 1101 int cpu = smp_processor_id(); 1102 struct task_struct *curr = current; 1103 struct tss_struct *t = &per_cpu(init_tss, cpu); 1104 struct thread_struct *thread = &curr->thread; 1105 1106 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1107 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1108 for (;;) local_irq_enable(); 1109 } 1110 1111 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1112 1113 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1114 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1115 1116 load_idt(&idt_descr); 1117 switch_to_new_gdt(); 1118 1119 /* 1120 * Set up and load the per-CPU TSS and LDT 1121 */ 1122 atomic_inc(&init_mm.mm_count); 1123 curr->active_mm = &init_mm; 1124 if (curr->mm) 1125 BUG(); 1126 enter_lazy_tlb(&init_mm, curr); 1127 1128 load_sp0(t, thread); 1129 set_tss_desc(cpu, t); 1130 load_TR_desc(); 1131 load_LDT(&init_mm.context); 1132 1133 #ifdef CONFIG_DOUBLEFAULT 1134 /* Set up doublefault TSS pointer in the GDT */ 1135 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1136 #endif 1137 1138 /* Clear %gs. */ 1139 asm volatile ("mov %0, %%gs" : : "r" (0)); 1140 1141 /* Clear all 6 debug registers: */ 1142 set_debugreg(0, 0); 1143 set_debugreg(0, 1); 1144 set_debugreg(0, 2); 1145 set_debugreg(0, 3); 1146 set_debugreg(0, 6); 1147 set_debugreg(0, 7); 1148 1149 /* 1150 * Force FPU initialization: 1151 */ 1152 if (cpu_has_xsave) 1153 current_thread_info()->status = TS_XSAVE; 1154 else 1155 current_thread_info()->status = 0; 1156 clear_used_math(); 1157 mxcsr_feature_mask_init(); 1158 1159 /* 1160 * Boot processor to setup the FP and extended state context info. 1161 */ 1162 if (smp_processor_id() == boot_cpu_id) 1163 init_thread_xstate(); 1164 1165 xsave_init(); 1166 } 1167 1168 1169 #endif 1170