1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_event.h> 17 #include <asm/mmu_context.h> 18 #include <asm/archrandom.h> 19 #include <asm/hypervisor.h> 20 #include <asm/processor.h> 21 #include <asm/sections.h> 22 #include <linux/topology.h> 23 #include <linux/cpumask.h> 24 #include <asm/pgtable.h> 25 #include <linux/atomic.h> 26 #include <asm/proto.h> 27 #include <asm/setup.h> 28 #include <asm/apic.h> 29 #include <asm/desc.h> 30 #include <asm/i387.h> 31 #include <asm/fpu-internal.h> 32 #include <asm/mtrr.h> 33 #include <linux/numa.h> 34 #include <asm/asm.h> 35 #include <asm/cpu.h> 36 #include <asm/mce.h> 37 #include <asm/msr.h> 38 #include <asm/pat.h> 39 40 #ifdef CONFIG_X86_LOCAL_APIC 41 #include <asm/uv/uv.h> 42 #endif 43 44 #include "cpu.h" 45 46 /* all of these masks are initialized in setup_cpu_local_masks() */ 47 cpumask_var_t cpu_initialized_mask; 48 cpumask_var_t cpu_callout_mask; 49 cpumask_var_t cpu_callin_mask; 50 51 /* representing cpus for which sibling maps can be computed */ 52 cpumask_var_t cpu_sibling_setup_mask; 53 54 /* correctly size the local cpu masks */ 55 void __init setup_cpu_local_masks(void) 56 { 57 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 58 alloc_bootmem_cpumask_var(&cpu_callin_mask); 59 alloc_bootmem_cpumask_var(&cpu_callout_mask); 60 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 61 } 62 63 static void __cpuinit default_init(struct cpuinfo_x86 *c) 64 { 65 #ifdef CONFIG_X86_64 66 cpu_detect_cache_sizes(c); 67 #else 68 /* Not much we can do here... */ 69 /* Check if at least it has cpuid */ 70 if (c->cpuid_level == -1) { 71 /* No cpuid. It must be an ancient CPU */ 72 if (c->x86 == 4) 73 strcpy(c->x86_model_id, "486"); 74 else if (c->x86 == 3) 75 strcpy(c->x86_model_id, "386"); 76 } 77 #endif 78 } 79 80 static const struct cpu_dev __cpuinitconst default_cpu = { 81 .c_init = default_init, 82 .c_vendor = "Unknown", 83 .c_x86_vendor = X86_VENDOR_UNKNOWN, 84 }; 85 86 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; 87 88 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 89 #ifdef CONFIG_X86_64 90 /* 91 * We need valid kernel segments for data and code in long mode too 92 * IRET will check the segment types kkeil 2000/10/28 93 * Also sysret mandates a special GDT layout 94 * 95 * TLS descriptors are currently at a different place compared to i386. 96 * Hopefully nobody expects them at a fixed place (Wine?) 97 */ 98 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 99 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 100 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 101 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 102 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 103 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 104 #else 105 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 106 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 107 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 109 /* 110 * Segments used for calling PnP BIOS have byte granularity. 111 * They code segments and data segments have fixed 64k limits, 112 * the transfer segment sizes are set at run time. 113 */ 114 /* 32-bit code */ 115 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 116 /* 16-bit code */ 117 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 118 /* 16-bit data */ 119 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 120 /* 16-bit data */ 121 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 122 /* 16-bit data */ 123 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 124 /* 125 * The APM segments have byte granularity and their bases 126 * are set at run time. All have 64k limits. 127 */ 128 /* 32-bit code */ 129 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 130 /* 16-bit code */ 131 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 132 /* data */ 133 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 134 135 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 136 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 137 GDT_STACK_CANARY_INIT 138 #endif 139 } }; 140 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 141 142 static int __init x86_xsave_setup(char *s) 143 { 144 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 145 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 146 return 1; 147 } 148 __setup("noxsave", x86_xsave_setup); 149 150 static int __init x86_xsaveopt_setup(char *s) 151 { 152 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 153 return 1; 154 } 155 __setup("noxsaveopt", x86_xsaveopt_setup); 156 157 #ifdef CONFIG_X86_32 158 static int cachesize_override __cpuinitdata = -1; 159 static int disable_x86_serial_nr __cpuinitdata = 1; 160 161 static int __init cachesize_setup(char *str) 162 { 163 get_option(&str, &cachesize_override); 164 return 1; 165 } 166 __setup("cachesize=", cachesize_setup); 167 168 static int __init x86_fxsr_setup(char *s) 169 { 170 setup_clear_cpu_cap(X86_FEATURE_FXSR); 171 setup_clear_cpu_cap(X86_FEATURE_XMM); 172 return 1; 173 } 174 __setup("nofxsr", x86_fxsr_setup); 175 176 static int __init x86_sep_setup(char *s) 177 { 178 setup_clear_cpu_cap(X86_FEATURE_SEP); 179 return 1; 180 } 181 __setup("nosep", x86_sep_setup); 182 183 /* Standard macro to see if a specific flag is changeable */ 184 static inline int flag_is_changeable_p(u32 flag) 185 { 186 u32 f1, f2; 187 188 /* 189 * Cyrix and IDT cpus allow disabling of CPUID 190 * so the code below may return different results 191 * when it is executed before and after enabling 192 * the CPUID. Add "volatile" to not allow gcc to 193 * optimize the subsequent calls to this function. 194 */ 195 asm volatile ("pushfl \n\t" 196 "pushfl \n\t" 197 "popl %0 \n\t" 198 "movl %0, %1 \n\t" 199 "xorl %2, %0 \n\t" 200 "pushl %0 \n\t" 201 "popfl \n\t" 202 "pushfl \n\t" 203 "popl %0 \n\t" 204 "popfl \n\t" 205 206 : "=&r" (f1), "=&r" (f2) 207 : "ir" (flag)); 208 209 return ((f1^f2) & flag) != 0; 210 } 211 212 /* Probe for the CPUID instruction */ 213 static int __cpuinit have_cpuid_p(void) 214 { 215 return flag_is_changeable_p(X86_EFLAGS_ID); 216 } 217 218 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 219 { 220 unsigned long lo, hi; 221 222 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 223 return; 224 225 /* Disable processor serial number: */ 226 227 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 228 lo |= 0x200000; 229 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 230 231 printk(KERN_NOTICE "CPU serial number disabled.\n"); 232 clear_cpu_cap(c, X86_FEATURE_PN); 233 234 /* Disabling the serial number may affect the cpuid level */ 235 c->cpuid_level = cpuid_eax(0); 236 } 237 238 static int __init x86_serial_nr_setup(char *s) 239 { 240 disable_x86_serial_nr = 0; 241 return 1; 242 } 243 __setup("serialnumber", x86_serial_nr_setup); 244 #else 245 static inline int flag_is_changeable_p(u32 flag) 246 { 247 return 1; 248 } 249 /* Probe for the CPUID instruction */ 250 static inline int have_cpuid_p(void) 251 { 252 return 1; 253 } 254 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 255 { 256 } 257 #endif 258 259 static int disable_smep __cpuinitdata; 260 static __init int setup_disable_smep(char *arg) 261 { 262 disable_smep = 1; 263 return 1; 264 } 265 __setup("nosmep", setup_disable_smep); 266 267 static __cpuinit void setup_smep(struct cpuinfo_x86 *c) 268 { 269 if (cpu_has(c, X86_FEATURE_SMEP)) { 270 if (unlikely(disable_smep)) { 271 setup_clear_cpu_cap(X86_FEATURE_SMEP); 272 clear_in_cr4(X86_CR4_SMEP); 273 } else 274 set_in_cr4(X86_CR4_SMEP); 275 } 276 } 277 278 /* 279 * Some CPU features depend on higher CPUID levels, which may not always 280 * be available due to CPUID level capping or broken virtualization 281 * software. Add those features to this table to auto-disable them. 282 */ 283 struct cpuid_dependent_feature { 284 u32 feature; 285 u32 level; 286 }; 287 288 static const struct cpuid_dependent_feature __cpuinitconst 289 cpuid_dependent_features[] = { 290 { X86_FEATURE_MWAIT, 0x00000005 }, 291 { X86_FEATURE_DCA, 0x00000009 }, 292 { X86_FEATURE_XSAVE, 0x0000000d }, 293 { 0, 0 } 294 }; 295 296 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 297 { 298 const struct cpuid_dependent_feature *df; 299 300 for (df = cpuid_dependent_features; df->feature; df++) { 301 302 if (!cpu_has(c, df->feature)) 303 continue; 304 /* 305 * Note: cpuid_level is set to -1 if unavailable, but 306 * extended_extended_level is set to 0 if unavailable 307 * and the legitimate extended levels are all negative 308 * when signed; hence the weird messing around with 309 * signs here... 310 */ 311 if (!((s32)df->level < 0 ? 312 (u32)df->level > (u32)c->extended_cpuid_level : 313 (s32)df->level > (s32)c->cpuid_level)) 314 continue; 315 316 clear_cpu_cap(c, df->feature); 317 if (!warn) 318 continue; 319 320 printk(KERN_WARNING 321 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 322 x86_cap_flags[df->feature], df->level); 323 } 324 } 325 326 /* 327 * Naming convention should be: <Name> [(<Codename>)] 328 * This table only is used unless init_<vendor>() below doesn't set it; 329 * in particular, if CPUID levels 0x80000002..4 are supported, this 330 * isn't used 331 */ 332 333 /* Look up CPU names by table lookup. */ 334 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 335 { 336 const struct cpu_model_info *info; 337 338 if (c->x86_model >= 16) 339 return NULL; /* Range check */ 340 341 if (!this_cpu) 342 return NULL; 343 344 info = this_cpu->c_models; 345 346 while (info && info->family) { 347 if (info->family == c->x86) 348 return info->model_names[c->x86_model]; 349 info++; 350 } 351 return NULL; /* Not found */ 352 } 353 354 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; 355 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; 356 357 void load_percpu_segment(int cpu) 358 { 359 #ifdef CONFIG_X86_32 360 loadsegment(fs, __KERNEL_PERCPU); 361 #else 362 loadsegment(gs, 0); 363 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 364 #endif 365 load_stack_canary_segment(); 366 } 367 368 /* 369 * Current gdt points %fs at the "master" per-cpu area: after this, 370 * it's on the real one. 371 */ 372 void switch_to_new_gdt(int cpu) 373 { 374 struct desc_ptr gdt_descr; 375 376 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 377 gdt_descr.size = GDT_SIZE - 1; 378 load_gdt(&gdt_descr); 379 /* Reload the per-cpu base */ 380 381 load_percpu_segment(cpu); 382 } 383 384 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 385 386 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 387 { 388 unsigned int *v; 389 char *p, *q; 390 391 if (c->extended_cpuid_level < 0x80000004) 392 return; 393 394 v = (unsigned int *)c->x86_model_id; 395 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 396 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 397 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 398 c->x86_model_id[48] = 0; 399 400 /* 401 * Intel chips right-justify this string for some dumb reason; 402 * undo that brain damage: 403 */ 404 p = q = &c->x86_model_id[0]; 405 while (*p == ' ') 406 p++; 407 if (p != q) { 408 while (*p) 409 *q++ = *p++; 410 while (q <= &c->x86_model_id[48]) 411 *q++ = '\0'; /* Zero-pad the rest */ 412 } 413 } 414 415 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 416 { 417 unsigned int n, dummy, ebx, ecx, edx, l2size; 418 419 n = c->extended_cpuid_level; 420 421 if (n >= 0x80000005) { 422 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 423 c->x86_cache_size = (ecx>>24) + (edx>>24); 424 #ifdef CONFIG_X86_64 425 /* On K8 L1 TLB is inclusive, so don't count it */ 426 c->x86_tlbsize = 0; 427 #endif 428 } 429 430 if (n < 0x80000006) /* Some chips just has a large L1. */ 431 return; 432 433 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 434 l2size = ecx >> 16; 435 436 #ifdef CONFIG_X86_64 437 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 438 #else 439 /* do processor-specific cache resizing */ 440 if (this_cpu->c_size_cache) 441 l2size = this_cpu->c_size_cache(c, l2size); 442 443 /* Allow user to override all this if necessary. */ 444 if (cachesize_override != -1) 445 l2size = cachesize_override; 446 447 if (l2size == 0) 448 return; /* Again, no L2 cache is possible */ 449 #endif 450 451 c->x86_cache_size = l2size; 452 } 453 454 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 455 { 456 #ifdef CONFIG_X86_HT 457 u32 eax, ebx, ecx, edx; 458 int index_msb, core_bits; 459 static bool printed; 460 461 if (!cpu_has(c, X86_FEATURE_HT)) 462 return; 463 464 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 465 goto out; 466 467 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 468 return; 469 470 cpuid(1, &eax, &ebx, &ecx, &edx); 471 472 smp_num_siblings = (ebx & 0xff0000) >> 16; 473 474 if (smp_num_siblings == 1) { 475 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 476 goto out; 477 } 478 479 if (smp_num_siblings <= 1) 480 goto out; 481 482 index_msb = get_count_order(smp_num_siblings); 483 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 484 485 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 486 487 index_msb = get_count_order(smp_num_siblings); 488 489 core_bits = get_count_order(c->x86_max_cores); 490 491 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 492 ((1 << core_bits) - 1); 493 494 out: 495 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 496 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 497 c->phys_proc_id); 498 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 499 c->cpu_core_id); 500 printed = 1; 501 } 502 #endif 503 } 504 505 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 506 { 507 char *v = c->x86_vendor_id; 508 int i; 509 510 for (i = 0; i < X86_VENDOR_NUM; i++) { 511 if (!cpu_devs[i]) 512 break; 513 514 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 515 (cpu_devs[i]->c_ident[1] && 516 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 517 518 this_cpu = cpu_devs[i]; 519 c->x86_vendor = this_cpu->c_x86_vendor; 520 return; 521 } 522 } 523 524 printk_once(KERN_ERR 525 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 526 "CPU: Your system may be unstable.\n", v); 527 528 c->x86_vendor = X86_VENDOR_UNKNOWN; 529 this_cpu = &default_cpu; 530 } 531 532 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 533 { 534 /* Get vendor name */ 535 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 536 (unsigned int *)&c->x86_vendor_id[0], 537 (unsigned int *)&c->x86_vendor_id[8], 538 (unsigned int *)&c->x86_vendor_id[4]); 539 540 c->x86 = 4; 541 /* Intel-defined flags: level 0x00000001 */ 542 if (c->cpuid_level >= 0x00000001) { 543 u32 junk, tfms, cap0, misc; 544 545 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 546 c->x86 = (tfms >> 8) & 0xf; 547 c->x86_model = (tfms >> 4) & 0xf; 548 c->x86_mask = tfms & 0xf; 549 550 if (c->x86 == 0xf) 551 c->x86 += (tfms >> 20) & 0xff; 552 if (c->x86 >= 0x6) 553 c->x86_model += ((tfms >> 16) & 0xf) << 4; 554 555 if (cap0 & (1<<19)) { 556 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 557 c->x86_cache_alignment = c->x86_clflush_size; 558 } 559 } 560 } 561 562 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 563 { 564 u32 tfms, xlvl; 565 u32 ebx; 566 567 /* Intel-defined flags: level 0x00000001 */ 568 if (c->cpuid_level >= 0x00000001) { 569 u32 capability, excap; 570 571 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 572 c->x86_capability[0] = capability; 573 c->x86_capability[4] = excap; 574 } 575 576 /* Additional Intel-defined flags: level 0x00000007 */ 577 if (c->cpuid_level >= 0x00000007) { 578 u32 eax, ebx, ecx, edx; 579 580 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 581 582 c->x86_capability[9] = ebx; 583 } 584 585 /* AMD-defined flags: level 0x80000001 */ 586 xlvl = cpuid_eax(0x80000000); 587 c->extended_cpuid_level = xlvl; 588 589 if ((xlvl & 0xffff0000) == 0x80000000) { 590 if (xlvl >= 0x80000001) { 591 c->x86_capability[1] = cpuid_edx(0x80000001); 592 c->x86_capability[6] = cpuid_ecx(0x80000001); 593 } 594 } 595 596 if (c->extended_cpuid_level >= 0x80000008) { 597 u32 eax = cpuid_eax(0x80000008); 598 599 c->x86_virt_bits = (eax >> 8) & 0xff; 600 c->x86_phys_bits = eax & 0xff; 601 } 602 #ifdef CONFIG_X86_32 603 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 604 c->x86_phys_bits = 36; 605 #endif 606 607 if (c->extended_cpuid_level >= 0x80000007) 608 c->x86_power = cpuid_edx(0x80000007); 609 610 init_scattered_cpuid_features(c); 611 } 612 613 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 614 { 615 #ifdef CONFIG_X86_32 616 int i; 617 618 /* 619 * First of all, decide if this is a 486 or higher 620 * It's a 486 if we can modify the AC flag 621 */ 622 if (flag_is_changeable_p(X86_EFLAGS_AC)) 623 c->x86 = 4; 624 else 625 c->x86 = 3; 626 627 for (i = 0; i < X86_VENDOR_NUM; i++) 628 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 629 c->x86_vendor_id[0] = 0; 630 cpu_devs[i]->c_identify(c); 631 if (c->x86_vendor_id[0]) { 632 get_cpu_vendor(c); 633 break; 634 } 635 } 636 #endif 637 } 638 639 /* 640 * Do minimum CPU detection early. 641 * Fields really needed: vendor, cpuid_level, family, model, mask, 642 * cache alignment. 643 * The others are not touched to avoid unwanted side effects. 644 * 645 * WARNING: this function is only called on the BP. Don't add code here 646 * that is supposed to run on all CPUs. 647 */ 648 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 649 { 650 #ifdef CONFIG_X86_64 651 c->x86_clflush_size = 64; 652 c->x86_phys_bits = 36; 653 c->x86_virt_bits = 48; 654 #else 655 c->x86_clflush_size = 32; 656 c->x86_phys_bits = 32; 657 c->x86_virt_bits = 32; 658 #endif 659 c->x86_cache_alignment = c->x86_clflush_size; 660 661 memset(&c->x86_capability, 0, sizeof c->x86_capability); 662 c->extended_cpuid_level = 0; 663 664 if (!have_cpuid_p()) 665 identify_cpu_without_cpuid(c); 666 667 /* cyrix could have cpuid enabled via c_identify()*/ 668 if (!have_cpuid_p()) 669 return; 670 671 cpu_detect(c); 672 673 get_cpu_vendor(c); 674 675 get_cpu_cap(c); 676 677 if (this_cpu->c_early_init) 678 this_cpu->c_early_init(c); 679 680 c->cpu_index = 0; 681 filter_cpuid_features(c, false); 682 683 setup_smep(c); 684 685 if (this_cpu->c_bsp_init) 686 this_cpu->c_bsp_init(c); 687 } 688 689 void __init early_cpu_init(void) 690 { 691 const struct cpu_dev *const *cdev; 692 int count = 0; 693 694 #ifdef CONFIG_PROCESSOR_SELECT 695 printk(KERN_INFO "KERNEL supported cpus:\n"); 696 #endif 697 698 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 699 const struct cpu_dev *cpudev = *cdev; 700 701 if (count >= X86_VENDOR_NUM) 702 break; 703 cpu_devs[count] = cpudev; 704 count++; 705 706 #ifdef CONFIG_PROCESSOR_SELECT 707 { 708 unsigned int j; 709 710 for (j = 0; j < 2; j++) { 711 if (!cpudev->c_ident[j]) 712 continue; 713 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 714 cpudev->c_ident[j]); 715 } 716 } 717 #endif 718 } 719 early_identify_cpu(&boot_cpu_data); 720 } 721 722 /* 723 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 724 * unfortunately, that's not true in practice because of early VIA 725 * chips and (more importantly) broken virtualizers that are not easy 726 * to detect. In the latter case it doesn't even *fail* reliably, so 727 * probing for it doesn't even work. Disable it completely on 32-bit 728 * unless we can find a reliable way to detect all the broken cases. 729 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 730 */ 731 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 732 { 733 #ifdef CONFIG_X86_32 734 clear_cpu_cap(c, X86_FEATURE_NOPL); 735 #else 736 set_cpu_cap(c, X86_FEATURE_NOPL); 737 #endif 738 } 739 740 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 741 { 742 c->extended_cpuid_level = 0; 743 744 if (!have_cpuid_p()) 745 identify_cpu_without_cpuid(c); 746 747 /* cyrix could have cpuid enabled via c_identify()*/ 748 if (!have_cpuid_p()) 749 return; 750 751 cpu_detect(c); 752 753 get_cpu_vendor(c); 754 755 get_cpu_cap(c); 756 757 if (c->cpuid_level >= 0x00000001) { 758 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 759 #ifdef CONFIG_X86_32 760 # ifdef CONFIG_X86_HT 761 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 762 # else 763 c->apicid = c->initial_apicid; 764 # endif 765 #endif 766 c->phys_proc_id = c->initial_apicid; 767 } 768 769 setup_smep(c); 770 771 get_model_name(c); /* Default name */ 772 773 detect_nopl(c); 774 } 775 776 /* 777 * This does the hard work of actually picking apart the CPU stuff... 778 */ 779 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 780 { 781 int i; 782 783 c->loops_per_jiffy = loops_per_jiffy; 784 c->x86_cache_size = -1; 785 c->x86_vendor = X86_VENDOR_UNKNOWN; 786 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 787 c->x86_vendor_id[0] = '\0'; /* Unset */ 788 c->x86_model_id[0] = '\0'; /* Unset */ 789 c->x86_max_cores = 1; 790 c->x86_coreid_bits = 0; 791 #ifdef CONFIG_X86_64 792 c->x86_clflush_size = 64; 793 c->x86_phys_bits = 36; 794 c->x86_virt_bits = 48; 795 #else 796 c->cpuid_level = -1; /* CPUID not detected */ 797 c->x86_clflush_size = 32; 798 c->x86_phys_bits = 32; 799 c->x86_virt_bits = 32; 800 #endif 801 c->x86_cache_alignment = c->x86_clflush_size; 802 memset(&c->x86_capability, 0, sizeof c->x86_capability); 803 804 generic_identify(c); 805 806 if (this_cpu->c_identify) 807 this_cpu->c_identify(c); 808 809 /* Clear/Set all flags overriden by options, after probe */ 810 for (i = 0; i < NCAPINTS; i++) { 811 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 812 c->x86_capability[i] |= cpu_caps_set[i]; 813 } 814 815 #ifdef CONFIG_X86_64 816 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 817 #endif 818 819 /* 820 * Vendor-specific initialization. In this section we 821 * canonicalize the feature flags, meaning if there are 822 * features a certain CPU supports which CPUID doesn't 823 * tell us, CPUID claiming incorrect flags, or other bugs, 824 * we handle them here. 825 * 826 * At the end of this section, c->x86_capability better 827 * indicate the features this CPU genuinely supports! 828 */ 829 if (this_cpu->c_init) 830 this_cpu->c_init(c); 831 832 /* Disable the PN if appropriate */ 833 squash_the_stupid_serial_number(c); 834 835 /* 836 * The vendor-specific functions might have changed features. 837 * Now we do "generic changes." 838 */ 839 840 /* Filter out anything that depends on CPUID levels we don't have */ 841 filter_cpuid_features(c, true); 842 843 /* If the model name is still unset, do table lookup. */ 844 if (!c->x86_model_id[0]) { 845 const char *p; 846 p = table_lookup_model(c); 847 if (p) 848 strcpy(c->x86_model_id, p); 849 else 850 /* Last resort... */ 851 sprintf(c->x86_model_id, "%02x/%02x", 852 c->x86, c->x86_model); 853 } 854 855 #ifdef CONFIG_X86_64 856 detect_ht(c); 857 #endif 858 859 init_hypervisor(c); 860 x86_init_rdrand(c); 861 862 /* 863 * Clear/Set all flags overriden by options, need do it 864 * before following smp all cpus cap AND. 865 */ 866 for (i = 0; i < NCAPINTS; i++) { 867 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 868 c->x86_capability[i] |= cpu_caps_set[i]; 869 } 870 871 /* 872 * On SMP, boot_cpu_data holds the common feature set between 873 * all CPUs; so make sure that we indicate which features are 874 * common between the CPUs. The first time this routine gets 875 * executed, c == &boot_cpu_data. 876 */ 877 if (c != &boot_cpu_data) { 878 /* AND the already accumulated flags with these */ 879 for (i = 0; i < NCAPINTS; i++) 880 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 881 } 882 883 /* Init Machine Check Exception if available. */ 884 mcheck_cpu_init(c); 885 886 select_idle_routine(c); 887 888 #ifdef CONFIG_NUMA 889 numa_add_cpu(smp_processor_id()); 890 #endif 891 } 892 893 #ifdef CONFIG_X86_64 894 static void vgetcpu_set_mode(void) 895 { 896 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 897 vgetcpu_mode = VGETCPU_RDTSCP; 898 else 899 vgetcpu_mode = VGETCPU_LSL; 900 } 901 #endif 902 903 void __init identify_boot_cpu(void) 904 { 905 identify_cpu(&boot_cpu_data); 906 init_amd_e400_c1e_mask(); 907 #ifdef CONFIG_X86_32 908 sysenter_setup(); 909 enable_sep_cpu(); 910 #else 911 vgetcpu_set_mode(); 912 #endif 913 } 914 915 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 916 { 917 BUG_ON(c == &boot_cpu_data); 918 identify_cpu(c); 919 #ifdef CONFIG_X86_32 920 enable_sep_cpu(); 921 #endif 922 mtrr_ap_init(); 923 } 924 925 struct msr_range { 926 unsigned min; 927 unsigned max; 928 }; 929 930 static const struct msr_range msr_range_array[] __cpuinitconst = { 931 { 0x00000000, 0x00000418}, 932 { 0xc0000000, 0xc000040b}, 933 { 0xc0010000, 0xc0010142}, 934 { 0xc0011000, 0xc001103b}, 935 }; 936 937 static void __cpuinit __print_cpu_msr(void) 938 { 939 unsigned index_min, index_max; 940 unsigned index; 941 u64 val; 942 int i; 943 944 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 945 index_min = msr_range_array[i].min; 946 index_max = msr_range_array[i].max; 947 948 for (index = index_min; index < index_max; index++) { 949 if (rdmsrl_amd_safe(index, &val)) 950 continue; 951 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 952 } 953 } 954 } 955 956 static int show_msr __cpuinitdata; 957 958 static __init int setup_show_msr(char *arg) 959 { 960 int num; 961 962 get_option(&arg, &num); 963 964 if (num > 0) 965 show_msr = num; 966 return 1; 967 } 968 __setup("show_msr=", setup_show_msr); 969 970 static __init int setup_noclflush(char *arg) 971 { 972 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 973 return 1; 974 } 975 __setup("noclflush", setup_noclflush); 976 977 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 978 { 979 const char *vendor = NULL; 980 981 if (c->x86_vendor < X86_VENDOR_NUM) { 982 vendor = this_cpu->c_vendor; 983 } else { 984 if (c->cpuid_level >= 0) 985 vendor = c->x86_vendor_id; 986 } 987 988 if (vendor && !strstr(c->x86_model_id, vendor)) 989 printk(KERN_CONT "%s ", vendor); 990 991 if (c->x86_model_id[0]) 992 printk(KERN_CONT "%s", c->x86_model_id); 993 else 994 printk(KERN_CONT "%d86", c->x86); 995 996 if (c->x86_mask || c->cpuid_level >= 0) 997 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 998 else 999 printk(KERN_CONT "\n"); 1000 1001 __print_cpu_msr(); 1002 } 1003 1004 void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c) 1005 { 1006 if (c->cpu_index < show_msr) 1007 __print_cpu_msr(); 1008 } 1009 1010 static __init int setup_disablecpuid(char *arg) 1011 { 1012 int bit; 1013 1014 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1015 setup_clear_cpu_cap(bit); 1016 else 1017 return 0; 1018 1019 return 1; 1020 } 1021 __setup("clearcpuid=", setup_disablecpuid); 1022 1023 #ifdef CONFIG_X86_64 1024 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1025 struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1, 1026 (unsigned long) nmi_idt_table }; 1027 1028 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1029 irq_stack_union) __aligned(PAGE_SIZE); 1030 1031 /* 1032 * The following four percpu variables are hot. Align current_task to 1033 * cacheline size such that all four fall in the same cacheline. 1034 */ 1035 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1036 &init_task; 1037 EXPORT_PER_CPU_SYMBOL(current_task); 1038 1039 DEFINE_PER_CPU(unsigned long, kernel_stack) = 1040 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 1041 EXPORT_PER_CPU_SYMBOL(kernel_stack); 1042 1043 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1044 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1045 1046 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 1047 1048 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1049 1050 /* 1051 * Special IST stacks which the CPU switches to when it calls 1052 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1053 * limit), all of them are 4K, except the debug stack which 1054 * is 8K. 1055 */ 1056 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1057 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1058 [DEBUG_STACK - 1] = DEBUG_STKSZ 1059 }; 1060 1061 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1062 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1063 1064 /* May not be marked __init: used by software suspend */ 1065 void syscall_init(void) 1066 { 1067 /* 1068 * LSTAR and STAR live in a bit strange symbiosis. 1069 * They both write to the same internal register. STAR allows to 1070 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1071 */ 1072 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1073 wrmsrl(MSR_LSTAR, system_call); 1074 wrmsrl(MSR_CSTAR, ignore_sysret); 1075 1076 #ifdef CONFIG_IA32_EMULATION 1077 syscall32_cpu_init(); 1078 #endif 1079 1080 /* Flags to clear on syscall */ 1081 wrmsrl(MSR_SYSCALL_MASK, 1082 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 1083 } 1084 1085 unsigned long kernel_eflags; 1086 1087 /* 1088 * Copies of the original ist values from the tss are only accessed during 1089 * debugging, no special alignment required. 1090 */ 1091 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1092 1093 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1094 DEFINE_PER_CPU(int, debug_stack_usage); 1095 1096 int is_debug_stack(unsigned long addr) 1097 { 1098 return __get_cpu_var(debug_stack_usage) || 1099 (addr <= __get_cpu_var(debug_stack_addr) && 1100 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); 1101 } 1102 1103 void debug_stack_set_zero(void) 1104 { 1105 load_idt((const struct desc_ptr *)&nmi_idt_descr); 1106 } 1107 1108 void debug_stack_reset(void) 1109 { 1110 load_idt((const struct desc_ptr *)&idt_descr); 1111 } 1112 1113 #else /* CONFIG_X86_64 */ 1114 1115 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1116 EXPORT_PER_CPU_SYMBOL(current_task); 1117 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); 1118 1119 #ifdef CONFIG_CC_STACKPROTECTOR 1120 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1121 #endif 1122 1123 /* Make sure %fs and %gs are initialized properly in idle threads */ 1124 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 1125 { 1126 memset(regs, 0, sizeof(struct pt_regs)); 1127 regs->fs = __KERNEL_PERCPU; 1128 regs->gs = __KERNEL_STACK_CANARY; 1129 1130 return regs; 1131 } 1132 #endif /* CONFIG_X86_64 */ 1133 1134 /* 1135 * Clear all 6 debug registers: 1136 */ 1137 static void clear_all_debug_regs(void) 1138 { 1139 int i; 1140 1141 for (i = 0; i < 8; i++) { 1142 /* Ignore db4, db5 */ 1143 if ((i == 4) || (i == 5)) 1144 continue; 1145 1146 set_debugreg(0, i); 1147 } 1148 } 1149 1150 #ifdef CONFIG_KGDB 1151 /* 1152 * Restore debug regs if using kgdbwait and you have a kernel debugger 1153 * connection established. 1154 */ 1155 static void dbg_restore_debug_regs(void) 1156 { 1157 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1158 arch_kgdb_ops.correct_hw_break(); 1159 } 1160 #else /* ! CONFIG_KGDB */ 1161 #define dbg_restore_debug_regs() 1162 #endif /* ! CONFIG_KGDB */ 1163 1164 /* 1165 * Prints an error where the NUMA and configured core-number mismatch and the 1166 * platform didn't override this to fix it up 1167 */ 1168 void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node) 1169 { 1170 pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id); 1171 } 1172 1173 /* 1174 * cpu_init() initializes state that is per-CPU. Some data is already 1175 * initialized (naturally) in the bootstrap process, such as the GDT 1176 * and IDT. We reload them nevertheless, this function acts as a 1177 * 'CPU state barrier', nothing should get across. 1178 * A lot of state is already set up in PDA init for 64 bit 1179 */ 1180 #ifdef CONFIG_X86_64 1181 1182 void __cpuinit cpu_init(void) 1183 { 1184 struct orig_ist *oist; 1185 struct task_struct *me; 1186 struct tss_struct *t; 1187 unsigned long v; 1188 int cpu; 1189 int i; 1190 1191 cpu = stack_smp_processor_id(); 1192 t = &per_cpu(init_tss, cpu); 1193 oist = &per_cpu(orig_ist, cpu); 1194 1195 #ifdef CONFIG_NUMA 1196 if (cpu != 0 && percpu_read(numa_node) == 0 && 1197 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1198 set_numa_node(early_cpu_to_node(cpu)); 1199 #endif 1200 1201 me = current; 1202 1203 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1204 panic("CPU#%d already initialized!\n", cpu); 1205 1206 pr_debug("Initializing CPU#%d\n", cpu); 1207 1208 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1209 1210 /* 1211 * Initialize the per-CPU GDT with the boot GDT, 1212 * and set up the GDT descriptor: 1213 */ 1214 1215 switch_to_new_gdt(cpu); 1216 loadsegment(fs, 0); 1217 1218 load_idt((const struct desc_ptr *)&idt_descr); 1219 1220 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1221 syscall_init(); 1222 1223 wrmsrl(MSR_FS_BASE, 0); 1224 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1225 barrier(); 1226 1227 x86_configure_nx(); 1228 if (cpu != 0) 1229 enable_x2apic(); 1230 1231 /* 1232 * set up and load the per-CPU TSS 1233 */ 1234 if (!oist->ist[0]) { 1235 char *estacks = per_cpu(exception_stacks, cpu); 1236 1237 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1238 estacks += exception_stack_sizes[v]; 1239 oist->ist[v] = t->x86_tss.ist[v] = 1240 (unsigned long)estacks; 1241 if (v == DEBUG_STACK-1) 1242 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1243 } 1244 } 1245 1246 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1247 1248 /* 1249 * <= is required because the CPU will access up to 1250 * 8 bits beyond the end of the IO permission bitmap. 1251 */ 1252 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1253 t->io_bitmap[i] = ~0UL; 1254 1255 atomic_inc(&init_mm.mm_count); 1256 me->active_mm = &init_mm; 1257 BUG_ON(me->mm); 1258 enter_lazy_tlb(&init_mm, me); 1259 1260 load_sp0(t, ¤t->thread); 1261 set_tss_desc(cpu, t); 1262 load_TR_desc(); 1263 load_LDT(&init_mm.context); 1264 1265 clear_all_debug_regs(); 1266 dbg_restore_debug_regs(); 1267 1268 fpu_init(); 1269 xsave_init(); 1270 1271 raw_local_save_flags(kernel_eflags); 1272 1273 if (is_uv_system()) 1274 uv_cpu_init(); 1275 } 1276 1277 #else 1278 1279 void __cpuinit cpu_init(void) 1280 { 1281 int cpu = smp_processor_id(); 1282 struct task_struct *curr = current; 1283 struct tss_struct *t = &per_cpu(init_tss, cpu); 1284 struct thread_struct *thread = &curr->thread; 1285 1286 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1287 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1288 for (;;) 1289 local_irq_enable(); 1290 } 1291 1292 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1293 1294 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1295 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1296 1297 load_idt(&idt_descr); 1298 switch_to_new_gdt(cpu); 1299 1300 /* 1301 * Set up and load the per-CPU TSS and LDT 1302 */ 1303 atomic_inc(&init_mm.mm_count); 1304 curr->active_mm = &init_mm; 1305 BUG_ON(curr->mm); 1306 enter_lazy_tlb(&init_mm, curr); 1307 1308 load_sp0(t, thread); 1309 set_tss_desc(cpu, t); 1310 load_TR_desc(); 1311 load_LDT(&init_mm.context); 1312 1313 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1314 1315 #ifdef CONFIG_DOUBLEFAULT 1316 /* Set up doublefault TSS pointer in the GDT */ 1317 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1318 #endif 1319 1320 clear_all_debug_regs(); 1321 dbg_restore_debug_regs(); 1322 1323 fpu_init(); 1324 xsave_init(); 1325 } 1326 #endif 1327