1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched.h> 11 #include <linux/init.h> 12 #include <linux/kprobes.h> 13 #include <linux/kgdb.h> 14 #include <linux/smp.h> 15 #include <linux/io.h> 16 #include <linux/syscore_ops.h> 17 18 #include <asm/stackprotector.h> 19 #include <asm/perf_event.h> 20 #include <asm/mmu_context.h> 21 #include <asm/archrandom.h> 22 #include <asm/hypervisor.h> 23 #include <asm/processor.h> 24 #include <asm/tlbflush.h> 25 #include <asm/debugreg.h> 26 #include <asm/sections.h> 27 #include <asm/vsyscall.h> 28 #include <linux/topology.h> 29 #include <linux/cpumask.h> 30 #include <asm/pgtable.h> 31 #include <linux/atomic.h> 32 #include <asm/proto.h> 33 #include <asm/setup.h> 34 #include <asm/apic.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/mtrr.h> 38 #include <linux/numa.h> 39 #include <asm/asm.h> 40 #include <asm/cpu.h> 41 #include <asm/mce.h> 42 #include <asm/msr.h> 43 #include <asm/pat.h> 44 #include <asm/microcode.h> 45 #include <asm/microcode_intel.h> 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 #include <asm/uv/uv.h> 49 #endif 50 51 #include "cpu.h" 52 53 /* all of these masks are initialized in setup_cpu_local_masks() */ 54 cpumask_var_t cpu_initialized_mask; 55 cpumask_var_t cpu_callout_mask; 56 cpumask_var_t cpu_callin_mask; 57 58 /* representing cpus for which sibling maps can be computed */ 59 cpumask_var_t cpu_sibling_setup_mask; 60 61 /* correctly size the local cpu masks */ 62 void __init setup_cpu_local_masks(void) 63 { 64 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 65 alloc_bootmem_cpumask_var(&cpu_callin_mask); 66 alloc_bootmem_cpumask_var(&cpu_callout_mask); 67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 68 } 69 70 static void default_init(struct cpuinfo_x86 *c) 71 { 72 #ifdef CONFIG_X86_64 73 cpu_detect_cache_sizes(c); 74 #else 75 /* Not much we can do here... */ 76 /* Check if at least it has cpuid */ 77 if (c->cpuid_level == -1) { 78 /* No cpuid. It must be an ancient CPU */ 79 if (c->x86 == 4) 80 strcpy(c->x86_model_id, "486"); 81 else if (c->x86 == 3) 82 strcpy(c->x86_model_id, "386"); 83 } 84 #endif 85 } 86 87 static const struct cpu_dev default_cpu = { 88 .c_init = default_init, 89 .c_vendor = "Unknown", 90 .c_x86_vendor = X86_VENDOR_UNKNOWN, 91 }; 92 93 static const struct cpu_dev *this_cpu = &default_cpu; 94 95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 96 #ifdef CONFIG_X86_64 97 /* 98 * We need valid kernel segments for data and code in long mode too 99 * IRET will check the segment types kkeil 2000/10/28 100 * Also sysret mandates a special GDT layout 101 * 102 * TLS descriptors are currently at a different place compared to i386. 103 * Hopefully nobody expects them at a fixed place (Wine?) 104 */ 105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 111 #else 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 116 /* 117 * Segments used for calling PnP BIOS have byte granularity. 118 * They code segments and data segments have fixed 64k limits, 119 * the transfer segment sizes are set at run time. 120 */ 121 /* 32-bit code */ 122 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 123 /* 16-bit code */ 124 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 125 /* 16-bit data */ 126 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 127 /* 16-bit data */ 128 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 129 /* 16-bit data */ 130 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 131 /* 132 * The APM segments have byte granularity and their bases 133 * are set at run time. All have 64k limits. 134 */ 135 /* 32-bit code */ 136 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 137 /* 16-bit code */ 138 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 139 /* data */ 140 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 141 142 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 143 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 144 GDT_STACK_CANARY_INIT 145 #endif 146 } }; 147 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 148 149 static int __init x86_mpx_setup(char *s) 150 { 151 /* require an exact match without trailing characters */ 152 if (strlen(s)) 153 return 0; 154 155 /* do not emit a message if the feature is not present */ 156 if (!boot_cpu_has(X86_FEATURE_MPX)) 157 return 1; 158 159 setup_clear_cpu_cap(X86_FEATURE_MPX); 160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 161 return 1; 162 } 163 __setup("nompx", x86_mpx_setup); 164 165 #ifdef CONFIG_X86_32 166 static int cachesize_override = -1; 167 static int disable_x86_serial_nr = 1; 168 169 static int __init cachesize_setup(char *str) 170 { 171 get_option(&str, &cachesize_override); 172 return 1; 173 } 174 __setup("cachesize=", cachesize_setup); 175 176 static int __init x86_sep_setup(char *s) 177 { 178 setup_clear_cpu_cap(X86_FEATURE_SEP); 179 return 1; 180 } 181 __setup("nosep", x86_sep_setup); 182 183 /* Standard macro to see if a specific flag is changeable */ 184 static inline int flag_is_changeable_p(u32 flag) 185 { 186 u32 f1, f2; 187 188 /* 189 * Cyrix and IDT cpus allow disabling of CPUID 190 * so the code below may return different results 191 * when it is executed before and after enabling 192 * the CPUID. Add "volatile" to not allow gcc to 193 * optimize the subsequent calls to this function. 194 */ 195 asm volatile ("pushfl \n\t" 196 "pushfl \n\t" 197 "popl %0 \n\t" 198 "movl %0, %1 \n\t" 199 "xorl %2, %0 \n\t" 200 "pushl %0 \n\t" 201 "popfl \n\t" 202 "pushfl \n\t" 203 "popl %0 \n\t" 204 "popfl \n\t" 205 206 : "=&r" (f1), "=&r" (f2) 207 : "ir" (flag)); 208 209 return ((f1^f2) & flag) != 0; 210 } 211 212 /* Probe for the CPUID instruction */ 213 int have_cpuid_p(void) 214 { 215 return flag_is_changeable_p(X86_EFLAGS_ID); 216 } 217 218 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 219 { 220 unsigned long lo, hi; 221 222 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 223 return; 224 225 /* Disable processor serial number: */ 226 227 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 228 lo |= 0x200000; 229 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 230 231 printk(KERN_NOTICE "CPU serial number disabled.\n"); 232 clear_cpu_cap(c, X86_FEATURE_PN); 233 234 /* Disabling the serial number may affect the cpuid level */ 235 c->cpuid_level = cpuid_eax(0); 236 } 237 238 static int __init x86_serial_nr_setup(char *s) 239 { 240 disable_x86_serial_nr = 0; 241 return 1; 242 } 243 __setup("serialnumber", x86_serial_nr_setup); 244 #else 245 static inline int flag_is_changeable_p(u32 flag) 246 { 247 return 1; 248 } 249 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 250 { 251 } 252 #endif 253 254 static __init int setup_disable_smep(char *arg) 255 { 256 setup_clear_cpu_cap(X86_FEATURE_SMEP); 257 return 1; 258 } 259 __setup("nosmep", setup_disable_smep); 260 261 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 262 { 263 if (cpu_has(c, X86_FEATURE_SMEP)) 264 cr4_set_bits(X86_CR4_SMEP); 265 } 266 267 static __init int setup_disable_smap(char *arg) 268 { 269 setup_clear_cpu_cap(X86_FEATURE_SMAP); 270 return 1; 271 } 272 __setup("nosmap", setup_disable_smap); 273 274 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 275 { 276 unsigned long eflags; 277 278 /* This should have been cleared long ago */ 279 raw_local_save_flags(eflags); 280 BUG_ON(eflags & X86_EFLAGS_AC); 281 282 if (cpu_has(c, X86_FEATURE_SMAP)) { 283 #ifdef CONFIG_X86_SMAP 284 cr4_set_bits(X86_CR4_SMAP); 285 #else 286 cr4_clear_bits(X86_CR4_SMAP); 287 #endif 288 } 289 } 290 291 /* 292 * Some CPU features depend on higher CPUID levels, which may not always 293 * be available due to CPUID level capping or broken virtualization 294 * software. Add those features to this table to auto-disable them. 295 */ 296 struct cpuid_dependent_feature { 297 u32 feature; 298 u32 level; 299 }; 300 301 static const struct cpuid_dependent_feature 302 cpuid_dependent_features[] = { 303 { X86_FEATURE_MWAIT, 0x00000005 }, 304 { X86_FEATURE_DCA, 0x00000009 }, 305 { X86_FEATURE_XSAVE, 0x0000000d }, 306 { 0, 0 } 307 }; 308 309 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 310 { 311 const struct cpuid_dependent_feature *df; 312 313 for (df = cpuid_dependent_features; df->feature; df++) { 314 315 if (!cpu_has(c, df->feature)) 316 continue; 317 /* 318 * Note: cpuid_level is set to -1 if unavailable, but 319 * extended_extended_level is set to 0 if unavailable 320 * and the legitimate extended levels are all negative 321 * when signed; hence the weird messing around with 322 * signs here... 323 */ 324 if (!((s32)df->level < 0 ? 325 (u32)df->level > (u32)c->extended_cpuid_level : 326 (s32)df->level > (s32)c->cpuid_level)) 327 continue; 328 329 clear_cpu_cap(c, df->feature); 330 if (!warn) 331 continue; 332 333 printk(KERN_WARNING 334 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 335 x86_cap_flag(df->feature), df->level); 336 } 337 } 338 339 /* 340 * Naming convention should be: <Name> [(<Codename>)] 341 * This table only is used unless init_<vendor>() below doesn't set it; 342 * in particular, if CPUID levels 0x80000002..4 are supported, this 343 * isn't used 344 */ 345 346 /* Look up CPU names by table lookup. */ 347 static const char *table_lookup_model(struct cpuinfo_x86 *c) 348 { 349 #ifdef CONFIG_X86_32 350 const struct legacy_cpu_model_info *info; 351 352 if (c->x86_model >= 16) 353 return NULL; /* Range check */ 354 355 if (!this_cpu) 356 return NULL; 357 358 info = this_cpu->legacy_models; 359 360 while (info->family) { 361 if (info->family == c->x86) 362 return info->model_names[c->x86_model]; 363 info++; 364 } 365 #endif 366 return NULL; /* Not found */ 367 } 368 369 __u32 cpu_caps_cleared[NCAPINTS]; 370 __u32 cpu_caps_set[NCAPINTS]; 371 372 void load_percpu_segment(int cpu) 373 { 374 #ifdef CONFIG_X86_32 375 loadsegment(fs, __KERNEL_PERCPU); 376 #else 377 loadsegment(gs, 0); 378 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 379 #endif 380 load_stack_canary_segment(); 381 } 382 383 /* 384 * Current gdt points %fs at the "master" per-cpu area: after this, 385 * it's on the real one. 386 */ 387 void switch_to_new_gdt(int cpu) 388 { 389 struct desc_ptr gdt_descr; 390 391 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 392 gdt_descr.size = GDT_SIZE - 1; 393 load_gdt(&gdt_descr); 394 /* Reload the per-cpu base */ 395 396 load_percpu_segment(cpu); 397 } 398 399 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 400 401 static void get_model_name(struct cpuinfo_x86 *c) 402 { 403 unsigned int *v; 404 char *p, *q, *s; 405 406 if (c->extended_cpuid_level < 0x80000004) 407 return; 408 409 v = (unsigned int *)c->x86_model_id; 410 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 411 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 412 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 413 c->x86_model_id[48] = 0; 414 415 /* Trim whitespace */ 416 p = q = s = &c->x86_model_id[0]; 417 418 while (*p == ' ') 419 p++; 420 421 while (*p) { 422 /* Note the last non-whitespace index */ 423 if (!isspace(*p)) 424 s = q; 425 426 *q++ = *p++; 427 } 428 429 *(s + 1) = '\0'; 430 } 431 432 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 433 { 434 unsigned int n, dummy, ebx, ecx, edx, l2size; 435 436 n = c->extended_cpuid_level; 437 438 if (n >= 0x80000005) { 439 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 440 c->x86_cache_size = (ecx>>24) + (edx>>24); 441 #ifdef CONFIG_X86_64 442 /* On K8 L1 TLB is inclusive, so don't count it */ 443 c->x86_tlbsize = 0; 444 #endif 445 } 446 447 if (n < 0x80000006) /* Some chips just has a large L1. */ 448 return; 449 450 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 451 l2size = ecx >> 16; 452 453 #ifdef CONFIG_X86_64 454 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 455 #else 456 /* do processor-specific cache resizing */ 457 if (this_cpu->legacy_cache_size) 458 l2size = this_cpu->legacy_cache_size(c, l2size); 459 460 /* Allow user to override all this if necessary. */ 461 if (cachesize_override != -1) 462 l2size = cachesize_override; 463 464 if (l2size == 0) 465 return; /* Again, no L2 cache is possible */ 466 #endif 467 468 c->x86_cache_size = l2size; 469 } 470 471 u16 __read_mostly tlb_lli_4k[NR_INFO]; 472 u16 __read_mostly tlb_lli_2m[NR_INFO]; 473 u16 __read_mostly tlb_lli_4m[NR_INFO]; 474 u16 __read_mostly tlb_lld_4k[NR_INFO]; 475 u16 __read_mostly tlb_lld_2m[NR_INFO]; 476 u16 __read_mostly tlb_lld_4m[NR_INFO]; 477 u16 __read_mostly tlb_lld_1g[NR_INFO]; 478 479 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 480 { 481 if (this_cpu->c_detect_tlb) 482 this_cpu->c_detect_tlb(c); 483 484 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 485 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 486 tlb_lli_4m[ENTRIES]); 487 488 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 489 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 490 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 491 } 492 493 void detect_ht(struct cpuinfo_x86 *c) 494 { 495 #ifdef CONFIG_SMP 496 u32 eax, ebx, ecx, edx; 497 int index_msb, core_bits; 498 static bool printed; 499 500 if (!cpu_has(c, X86_FEATURE_HT)) 501 return; 502 503 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 504 goto out; 505 506 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 507 return; 508 509 cpuid(1, &eax, &ebx, &ecx, &edx); 510 511 smp_num_siblings = (ebx & 0xff0000) >> 16; 512 513 if (smp_num_siblings == 1) { 514 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); 515 goto out; 516 } 517 518 if (smp_num_siblings <= 1) 519 goto out; 520 521 index_msb = get_count_order(smp_num_siblings); 522 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 523 524 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 525 526 index_msb = get_count_order(smp_num_siblings); 527 528 core_bits = get_count_order(c->x86_max_cores); 529 530 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 531 ((1 << core_bits) - 1); 532 533 out: 534 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 535 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 536 c->phys_proc_id); 537 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 538 c->cpu_core_id); 539 printed = 1; 540 } 541 #endif 542 } 543 544 static void get_cpu_vendor(struct cpuinfo_x86 *c) 545 { 546 char *v = c->x86_vendor_id; 547 int i; 548 549 for (i = 0; i < X86_VENDOR_NUM; i++) { 550 if (!cpu_devs[i]) 551 break; 552 553 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 554 (cpu_devs[i]->c_ident[1] && 555 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 556 557 this_cpu = cpu_devs[i]; 558 c->x86_vendor = this_cpu->c_x86_vendor; 559 return; 560 } 561 } 562 563 printk_once(KERN_ERR 564 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 565 "CPU: Your system may be unstable.\n", v); 566 567 c->x86_vendor = X86_VENDOR_UNKNOWN; 568 this_cpu = &default_cpu; 569 } 570 571 void cpu_detect(struct cpuinfo_x86 *c) 572 { 573 /* Get vendor name */ 574 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 575 (unsigned int *)&c->x86_vendor_id[0], 576 (unsigned int *)&c->x86_vendor_id[8], 577 (unsigned int *)&c->x86_vendor_id[4]); 578 579 c->x86 = 4; 580 /* Intel-defined flags: level 0x00000001 */ 581 if (c->cpuid_level >= 0x00000001) { 582 u32 junk, tfms, cap0, misc; 583 584 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 585 c->x86 = (tfms >> 8) & 0xf; 586 c->x86_model = (tfms >> 4) & 0xf; 587 c->x86_mask = tfms & 0xf; 588 589 if (c->x86 == 0xf) 590 c->x86 += (tfms >> 20) & 0xff; 591 if (c->x86 >= 0x6) 592 c->x86_model += ((tfms >> 16) & 0xf) << 4; 593 594 if (cap0 & (1<<19)) { 595 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 596 c->x86_cache_alignment = c->x86_clflush_size; 597 } 598 } 599 } 600 601 void get_cpu_cap(struct cpuinfo_x86 *c) 602 { 603 u32 tfms, xlvl; 604 u32 ebx; 605 606 /* Intel-defined flags: level 0x00000001 */ 607 if (c->cpuid_level >= 0x00000001) { 608 u32 capability, excap; 609 610 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 611 c->x86_capability[0] = capability; 612 c->x86_capability[4] = excap; 613 } 614 615 /* Additional Intel-defined flags: level 0x00000007 */ 616 if (c->cpuid_level >= 0x00000007) { 617 u32 eax, ebx, ecx, edx; 618 619 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 620 621 c->x86_capability[9] = ebx; 622 } 623 624 /* Extended state features: level 0x0000000d */ 625 if (c->cpuid_level >= 0x0000000d) { 626 u32 eax, ebx, ecx, edx; 627 628 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 629 630 c->x86_capability[10] = eax; 631 } 632 633 /* Additional Intel-defined flags: level 0x0000000F */ 634 if (c->cpuid_level >= 0x0000000F) { 635 u32 eax, ebx, ecx, edx; 636 637 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 638 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 639 c->x86_capability[11] = edx; 640 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 641 /* will be overridden if occupancy monitoring exists */ 642 c->x86_cache_max_rmid = ebx; 643 644 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 645 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 646 c->x86_capability[12] = edx; 647 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { 648 c->x86_cache_max_rmid = ecx; 649 c->x86_cache_occ_scale = ebx; 650 } 651 } else { 652 c->x86_cache_max_rmid = -1; 653 c->x86_cache_occ_scale = -1; 654 } 655 } 656 657 /* AMD-defined flags: level 0x80000001 */ 658 xlvl = cpuid_eax(0x80000000); 659 c->extended_cpuid_level = xlvl; 660 661 if ((xlvl & 0xffff0000) == 0x80000000) { 662 if (xlvl >= 0x80000001) { 663 c->x86_capability[1] = cpuid_edx(0x80000001); 664 c->x86_capability[6] = cpuid_ecx(0x80000001); 665 } 666 } 667 668 if (c->extended_cpuid_level >= 0x80000008) { 669 u32 eax = cpuid_eax(0x80000008); 670 671 c->x86_virt_bits = (eax >> 8) & 0xff; 672 c->x86_phys_bits = eax & 0xff; 673 c->x86_capability[13] = cpuid_ebx(0x80000008); 674 } 675 #ifdef CONFIG_X86_32 676 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 677 c->x86_phys_bits = 36; 678 #endif 679 680 if (c->extended_cpuid_level >= 0x80000007) 681 c->x86_power = cpuid_edx(0x80000007); 682 683 init_scattered_cpuid_features(c); 684 } 685 686 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 687 { 688 #ifdef CONFIG_X86_32 689 int i; 690 691 /* 692 * First of all, decide if this is a 486 or higher 693 * It's a 486 if we can modify the AC flag 694 */ 695 if (flag_is_changeable_p(X86_EFLAGS_AC)) 696 c->x86 = 4; 697 else 698 c->x86 = 3; 699 700 for (i = 0; i < X86_VENDOR_NUM; i++) 701 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 702 c->x86_vendor_id[0] = 0; 703 cpu_devs[i]->c_identify(c); 704 if (c->x86_vendor_id[0]) { 705 get_cpu_vendor(c); 706 break; 707 } 708 } 709 #endif 710 } 711 712 /* 713 * Do minimum CPU detection early. 714 * Fields really needed: vendor, cpuid_level, family, model, mask, 715 * cache alignment. 716 * The others are not touched to avoid unwanted side effects. 717 * 718 * WARNING: this function is only called on the BP. Don't add code here 719 * that is supposed to run on all CPUs. 720 */ 721 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 722 { 723 #ifdef CONFIG_X86_64 724 c->x86_clflush_size = 64; 725 c->x86_phys_bits = 36; 726 c->x86_virt_bits = 48; 727 #else 728 c->x86_clflush_size = 32; 729 c->x86_phys_bits = 32; 730 c->x86_virt_bits = 32; 731 #endif 732 c->x86_cache_alignment = c->x86_clflush_size; 733 734 memset(&c->x86_capability, 0, sizeof c->x86_capability); 735 c->extended_cpuid_level = 0; 736 737 if (!have_cpuid_p()) 738 identify_cpu_without_cpuid(c); 739 740 /* cyrix could have cpuid enabled via c_identify()*/ 741 if (!have_cpuid_p()) 742 return; 743 744 cpu_detect(c); 745 get_cpu_vendor(c); 746 get_cpu_cap(c); 747 748 if (this_cpu->c_early_init) 749 this_cpu->c_early_init(c); 750 751 c->cpu_index = 0; 752 filter_cpuid_features(c, false); 753 754 if (this_cpu->c_bsp_init) 755 this_cpu->c_bsp_init(c); 756 757 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 758 fpu__init_system(c); 759 } 760 761 void __init early_cpu_init(void) 762 { 763 const struct cpu_dev *const *cdev; 764 int count = 0; 765 766 #ifdef CONFIG_PROCESSOR_SELECT 767 printk(KERN_INFO "KERNEL supported cpus:\n"); 768 #endif 769 770 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 771 const struct cpu_dev *cpudev = *cdev; 772 773 if (count >= X86_VENDOR_NUM) 774 break; 775 cpu_devs[count] = cpudev; 776 count++; 777 778 #ifdef CONFIG_PROCESSOR_SELECT 779 { 780 unsigned int j; 781 782 for (j = 0; j < 2; j++) { 783 if (!cpudev->c_ident[j]) 784 continue; 785 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 786 cpudev->c_ident[j]); 787 } 788 } 789 #endif 790 } 791 early_identify_cpu(&boot_cpu_data); 792 } 793 794 /* 795 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 796 * unfortunately, that's not true in practice because of early VIA 797 * chips and (more importantly) broken virtualizers that are not easy 798 * to detect. In the latter case it doesn't even *fail* reliably, so 799 * probing for it doesn't even work. Disable it completely on 32-bit 800 * unless we can find a reliable way to detect all the broken cases. 801 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 802 */ 803 static void detect_nopl(struct cpuinfo_x86 *c) 804 { 805 #ifdef CONFIG_X86_32 806 clear_cpu_cap(c, X86_FEATURE_NOPL); 807 #else 808 set_cpu_cap(c, X86_FEATURE_NOPL); 809 #endif 810 } 811 812 static void generic_identify(struct cpuinfo_x86 *c) 813 { 814 c->extended_cpuid_level = 0; 815 816 if (!have_cpuid_p()) 817 identify_cpu_without_cpuid(c); 818 819 /* cyrix could have cpuid enabled via c_identify()*/ 820 if (!have_cpuid_p()) 821 return; 822 823 cpu_detect(c); 824 825 get_cpu_vendor(c); 826 827 get_cpu_cap(c); 828 829 if (c->cpuid_level >= 0x00000001) { 830 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 831 #ifdef CONFIG_X86_32 832 # ifdef CONFIG_SMP 833 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 834 # else 835 c->apicid = c->initial_apicid; 836 # endif 837 #endif 838 c->phys_proc_id = c->initial_apicid; 839 } 840 841 get_model_name(c); /* Default name */ 842 843 detect_nopl(c); 844 } 845 846 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 847 { 848 /* 849 * The heavy lifting of max_rmid and cache_occ_scale are handled 850 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 851 * in case CQM bits really aren't there in this CPU. 852 */ 853 if (c != &boot_cpu_data) { 854 boot_cpu_data.x86_cache_max_rmid = 855 min(boot_cpu_data.x86_cache_max_rmid, 856 c->x86_cache_max_rmid); 857 } 858 } 859 860 /* 861 * This does the hard work of actually picking apart the CPU stuff... 862 */ 863 static void identify_cpu(struct cpuinfo_x86 *c) 864 { 865 int i; 866 867 c->loops_per_jiffy = loops_per_jiffy; 868 c->x86_cache_size = -1; 869 c->x86_vendor = X86_VENDOR_UNKNOWN; 870 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 871 c->x86_vendor_id[0] = '\0'; /* Unset */ 872 c->x86_model_id[0] = '\0'; /* Unset */ 873 c->x86_max_cores = 1; 874 c->x86_coreid_bits = 0; 875 #ifdef CONFIG_X86_64 876 c->x86_clflush_size = 64; 877 c->x86_phys_bits = 36; 878 c->x86_virt_bits = 48; 879 #else 880 c->cpuid_level = -1; /* CPUID not detected */ 881 c->x86_clflush_size = 32; 882 c->x86_phys_bits = 32; 883 c->x86_virt_bits = 32; 884 #endif 885 c->x86_cache_alignment = c->x86_clflush_size; 886 memset(&c->x86_capability, 0, sizeof c->x86_capability); 887 888 generic_identify(c); 889 890 if (this_cpu->c_identify) 891 this_cpu->c_identify(c); 892 893 /* Clear/Set all flags overriden by options, after probe */ 894 for (i = 0; i < NCAPINTS; i++) { 895 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 896 c->x86_capability[i] |= cpu_caps_set[i]; 897 } 898 899 #ifdef CONFIG_X86_64 900 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 901 #endif 902 903 /* 904 * Vendor-specific initialization. In this section we 905 * canonicalize the feature flags, meaning if there are 906 * features a certain CPU supports which CPUID doesn't 907 * tell us, CPUID claiming incorrect flags, or other bugs, 908 * we handle them here. 909 * 910 * At the end of this section, c->x86_capability better 911 * indicate the features this CPU genuinely supports! 912 */ 913 if (this_cpu->c_init) 914 this_cpu->c_init(c); 915 916 /* Disable the PN if appropriate */ 917 squash_the_stupid_serial_number(c); 918 919 /* Set up SMEP/SMAP */ 920 setup_smep(c); 921 setup_smap(c); 922 923 /* 924 * The vendor-specific functions might have changed features. 925 * Now we do "generic changes." 926 */ 927 928 /* Filter out anything that depends on CPUID levels we don't have */ 929 filter_cpuid_features(c, true); 930 931 /* If the model name is still unset, do table lookup. */ 932 if (!c->x86_model_id[0]) { 933 const char *p; 934 p = table_lookup_model(c); 935 if (p) 936 strcpy(c->x86_model_id, p); 937 else 938 /* Last resort... */ 939 sprintf(c->x86_model_id, "%02x/%02x", 940 c->x86, c->x86_model); 941 } 942 943 #ifdef CONFIG_X86_64 944 detect_ht(c); 945 #endif 946 947 init_hypervisor(c); 948 x86_init_rdrand(c); 949 x86_init_cache_qos(c); 950 951 /* 952 * Clear/Set all flags overriden by options, need do it 953 * before following smp all cpus cap AND. 954 */ 955 for (i = 0; i < NCAPINTS; i++) { 956 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 957 c->x86_capability[i] |= cpu_caps_set[i]; 958 } 959 960 /* 961 * On SMP, boot_cpu_data holds the common feature set between 962 * all CPUs; so make sure that we indicate which features are 963 * common between the CPUs. The first time this routine gets 964 * executed, c == &boot_cpu_data. 965 */ 966 if (c != &boot_cpu_data) { 967 /* AND the already accumulated flags with these */ 968 for (i = 0; i < NCAPINTS; i++) 969 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 970 971 /* OR, i.e. replicate the bug flags */ 972 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 973 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 974 } 975 976 /* Init Machine Check Exception if available. */ 977 mcheck_cpu_init(c); 978 979 select_idle_routine(c); 980 981 #ifdef CONFIG_NUMA 982 numa_add_cpu(smp_processor_id()); 983 #endif 984 } 985 986 /* 987 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 988 * on 32-bit kernels: 989 */ 990 #ifdef CONFIG_X86_32 991 void enable_sep_cpu(void) 992 { 993 struct tss_struct *tss; 994 int cpu; 995 996 cpu = get_cpu(); 997 tss = &per_cpu(cpu_tss, cpu); 998 999 if (!boot_cpu_has(X86_FEATURE_SEP)) 1000 goto out; 1001 1002 /* 1003 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1004 * see the big comment in struct x86_hw_tss's definition. 1005 */ 1006 1007 tss->x86_tss.ss1 = __KERNEL_CS; 1008 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1009 1010 wrmsr(MSR_IA32_SYSENTER_ESP, 1011 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1012 0); 1013 1014 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1015 1016 out: 1017 put_cpu(); 1018 } 1019 #endif 1020 1021 void __init identify_boot_cpu(void) 1022 { 1023 identify_cpu(&boot_cpu_data); 1024 init_amd_e400_c1e_mask(); 1025 #ifdef CONFIG_X86_32 1026 sysenter_setup(); 1027 enable_sep_cpu(); 1028 #endif 1029 cpu_detect_tlb(&boot_cpu_data); 1030 } 1031 1032 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1033 { 1034 BUG_ON(c == &boot_cpu_data); 1035 identify_cpu(c); 1036 #ifdef CONFIG_X86_32 1037 enable_sep_cpu(); 1038 #endif 1039 mtrr_ap_init(); 1040 } 1041 1042 struct msr_range { 1043 unsigned min; 1044 unsigned max; 1045 }; 1046 1047 static const struct msr_range msr_range_array[] = { 1048 { 0x00000000, 0x00000418}, 1049 { 0xc0000000, 0xc000040b}, 1050 { 0xc0010000, 0xc0010142}, 1051 { 0xc0011000, 0xc001103b}, 1052 }; 1053 1054 static void __print_cpu_msr(void) 1055 { 1056 unsigned index_min, index_max; 1057 unsigned index; 1058 u64 val; 1059 int i; 1060 1061 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 1062 index_min = msr_range_array[i].min; 1063 index_max = msr_range_array[i].max; 1064 1065 for (index = index_min; index < index_max; index++) { 1066 if (rdmsrl_safe(index, &val)) 1067 continue; 1068 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 1069 } 1070 } 1071 } 1072 1073 static int show_msr; 1074 1075 static __init int setup_show_msr(char *arg) 1076 { 1077 int num; 1078 1079 get_option(&arg, &num); 1080 1081 if (num > 0) 1082 show_msr = num; 1083 return 1; 1084 } 1085 __setup("show_msr=", setup_show_msr); 1086 1087 static __init int setup_noclflush(char *arg) 1088 { 1089 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1090 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1091 return 1; 1092 } 1093 __setup("noclflush", setup_noclflush); 1094 1095 void print_cpu_info(struct cpuinfo_x86 *c) 1096 { 1097 const char *vendor = NULL; 1098 1099 if (c->x86_vendor < X86_VENDOR_NUM) { 1100 vendor = this_cpu->c_vendor; 1101 } else { 1102 if (c->cpuid_level >= 0) 1103 vendor = c->x86_vendor_id; 1104 } 1105 1106 if (vendor && !strstr(c->x86_model_id, vendor)) 1107 printk(KERN_CONT "%s ", vendor); 1108 1109 if (c->x86_model_id[0]) 1110 printk(KERN_CONT "%s", c->x86_model_id); 1111 else 1112 printk(KERN_CONT "%d86", c->x86); 1113 1114 printk(KERN_CONT " (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1115 1116 if (c->x86_mask || c->cpuid_level >= 0) 1117 printk(KERN_CONT ", stepping: 0x%x)\n", c->x86_mask); 1118 else 1119 printk(KERN_CONT ")\n"); 1120 1121 print_cpu_msr(c); 1122 } 1123 1124 void print_cpu_msr(struct cpuinfo_x86 *c) 1125 { 1126 if (c->cpu_index < show_msr) 1127 __print_cpu_msr(); 1128 } 1129 1130 static __init int setup_disablecpuid(char *arg) 1131 { 1132 int bit; 1133 1134 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1135 setup_clear_cpu_cap(bit); 1136 else 1137 return 0; 1138 1139 return 1; 1140 } 1141 __setup("clearcpuid=", setup_disablecpuid); 1142 1143 #ifdef CONFIG_X86_64 1144 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1145 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1146 (unsigned long) debug_idt_table }; 1147 1148 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1149 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1150 1151 /* 1152 * The following percpu variables are hot. Align current_task to 1153 * cacheline size such that they fall in the same cacheline. 1154 */ 1155 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1156 &init_task; 1157 EXPORT_PER_CPU_SYMBOL(current_task); 1158 1159 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1160 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1161 1162 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1163 1164 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1165 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1166 1167 /* 1168 * Special IST stacks which the CPU switches to when it calls 1169 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1170 * limit), all of them are 4K, except the debug stack which 1171 * is 8K. 1172 */ 1173 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1174 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1175 [DEBUG_STACK - 1] = DEBUG_STKSZ 1176 }; 1177 1178 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1179 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1180 1181 /* May not be marked __init: used by software suspend */ 1182 void syscall_init(void) 1183 { 1184 /* 1185 * LSTAR and STAR live in a bit strange symbiosis. 1186 * They both write to the same internal register. STAR allows to 1187 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1188 */ 1189 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1190 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1191 1192 #ifdef CONFIG_IA32_EMULATION 1193 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1194 /* 1195 * This only works on Intel CPUs. 1196 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1197 * This does not cause SYSENTER to jump to the wrong location, because 1198 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1199 */ 1200 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1201 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1202 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1203 #else 1204 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1205 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1206 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1207 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1208 #endif 1209 1210 /* Flags to clear on syscall */ 1211 wrmsrl(MSR_SYSCALL_MASK, 1212 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1213 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1214 } 1215 1216 /* 1217 * Copies of the original ist values from the tss are only accessed during 1218 * debugging, no special alignment required. 1219 */ 1220 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1221 1222 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1223 DEFINE_PER_CPU(int, debug_stack_usage); 1224 1225 int is_debug_stack(unsigned long addr) 1226 { 1227 return __this_cpu_read(debug_stack_usage) || 1228 (addr <= __this_cpu_read(debug_stack_addr) && 1229 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1230 } 1231 NOKPROBE_SYMBOL(is_debug_stack); 1232 1233 DEFINE_PER_CPU(u32, debug_idt_ctr); 1234 1235 void debug_stack_set_zero(void) 1236 { 1237 this_cpu_inc(debug_idt_ctr); 1238 load_current_idt(); 1239 } 1240 NOKPROBE_SYMBOL(debug_stack_set_zero); 1241 1242 void debug_stack_reset(void) 1243 { 1244 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1245 return; 1246 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1247 load_current_idt(); 1248 } 1249 NOKPROBE_SYMBOL(debug_stack_reset); 1250 1251 #else /* CONFIG_X86_64 */ 1252 1253 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1254 EXPORT_PER_CPU_SYMBOL(current_task); 1255 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1256 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1257 1258 /* 1259 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1260 * the top of the kernel stack. Use an extra percpu variable to track the 1261 * top of the kernel stack directly. 1262 */ 1263 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1264 (unsigned long)&init_thread_union + THREAD_SIZE; 1265 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1266 1267 #ifdef CONFIG_CC_STACKPROTECTOR 1268 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1269 #endif 1270 1271 #endif /* CONFIG_X86_64 */ 1272 1273 /* 1274 * Clear all 6 debug registers: 1275 */ 1276 static void clear_all_debug_regs(void) 1277 { 1278 int i; 1279 1280 for (i = 0; i < 8; i++) { 1281 /* Ignore db4, db5 */ 1282 if ((i == 4) || (i == 5)) 1283 continue; 1284 1285 set_debugreg(0, i); 1286 } 1287 } 1288 1289 #ifdef CONFIG_KGDB 1290 /* 1291 * Restore debug regs if using kgdbwait and you have a kernel debugger 1292 * connection established. 1293 */ 1294 static void dbg_restore_debug_regs(void) 1295 { 1296 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1297 arch_kgdb_ops.correct_hw_break(); 1298 } 1299 #else /* ! CONFIG_KGDB */ 1300 #define dbg_restore_debug_regs() 1301 #endif /* ! CONFIG_KGDB */ 1302 1303 static void wait_for_master_cpu(int cpu) 1304 { 1305 #ifdef CONFIG_SMP 1306 /* 1307 * wait for ACK from master CPU before continuing 1308 * with AP initialization 1309 */ 1310 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1311 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1312 cpu_relax(); 1313 #endif 1314 } 1315 1316 /* 1317 * cpu_init() initializes state that is per-CPU. Some data is already 1318 * initialized (naturally) in the bootstrap process, such as the GDT 1319 * and IDT. We reload them nevertheless, this function acts as a 1320 * 'CPU state barrier', nothing should get across. 1321 * A lot of state is already set up in PDA init for 64 bit 1322 */ 1323 #ifdef CONFIG_X86_64 1324 1325 void cpu_init(void) 1326 { 1327 struct orig_ist *oist; 1328 struct task_struct *me; 1329 struct tss_struct *t; 1330 unsigned long v; 1331 int cpu = stack_smp_processor_id(); 1332 int i; 1333 1334 wait_for_master_cpu(cpu); 1335 1336 /* 1337 * Initialize the CR4 shadow before doing anything that could 1338 * try to read it. 1339 */ 1340 cr4_init_shadow(); 1341 1342 /* 1343 * Load microcode on this cpu if a valid microcode is available. 1344 * This is early microcode loading procedure. 1345 */ 1346 load_ucode_ap(); 1347 1348 t = &per_cpu(cpu_tss, cpu); 1349 oist = &per_cpu(orig_ist, cpu); 1350 1351 #ifdef CONFIG_NUMA 1352 if (this_cpu_read(numa_node) == 0 && 1353 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1354 set_numa_node(early_cpu_to_node(cpu)); 1355 #endif 1356 1357 me = current; 1358 1359 pr_debug("Initializing CPU#%d\n", cpu); 1360 1361 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1362 1363 /* 1364 * Initialize the per-CPU GDT with the boot GDT, 1365 * and set up the GDT descriptor: 1366 */ 1367 1368 switch_to_new_gdt(cpu); 1369 loadsegment(fs, 0); 1370 1371 load_current_idt(); 1372 1373 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1374 syscall_init(); 1375 1376 wrmsrl(MSR_FS_BASE, 0); 1377 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1378 barrier(); 1379 1380 x86_configure_nx(); 1381 x2apic_setup(); 1382 1383 /* 1384 * set up and load the per-CPU TSS 1385 */ 1386 if (!oist->ist[0]) { 1387 char *estacks = per_cpu(exception_stacks, cpu); 1388 1389 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1390 estacks += exception_stack_sizes[v]; 1391 oist->ist[v] = t->x86_tss.ist[v] = 1392 (unsigned long)estacks; 1393 if (v == DEBUG_STACK-1) 1394 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1395 } 1396 } 1397 1398 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1399 1400 /* 1401 * <= is required because the CPU will access up to 1402 * 8 bits beyond the end of the IO permission bitmap. 1403 */ 1404 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1405 t->io_bitmap[i] = ~0UL; 1406 1407 atomic_inc(&init_mm.mm_count); 1408 me->active_mm = &init_mm; 1409 BUG_ON(me->mm); 1410 enter_lazy_tlb(&init_mm, me); 1411 1412 load_sp0(t, ¤t->thread); 1413 set_tss_desc(cpu, t); 1414 load_TR_desc(); 1415 load_mm_ldt(&init_mm); 1416 1417 clear_all_debug_regs(); 1418 dbg_restore_debug_regs(); 1419 1420 fpu__init_cpu(); 1421 1422 if (is_uv_system()) 1423 uv_cpu_init(); 1424 } 1425 1426 #else 1427 1428 void cpu_init(void) 1429 { 1430 int cpu = smp_processor_id(); 1431 struct task_struct *curr = current; 1432 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1433 struct thread_struct *thread = &curr->thread; 1434 1435 wait_for_master_cpu(cpu); 1436 1437 /* 1438 * Initialize the CR4 shadow before doing anything that could 1439 * try to read it. 1440 */ 1441 cr4_init_shadow(); 1442 1443 show_ucode_info_early(); 1444 1445 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1446 1447 if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) 1448 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1449 1450 load_current_idt(); 1451 switch_to_new_gdt(cpu); 1452 1453 /* 1454 * Set up and load the per-CPU TSS and LDT 1455 */ 1456 atomic_inc(&init_mm.mm_count); 1457 curr->active_mm = &init_mm; 1458 BUG_ON(curr->mm); 1459 enter_lazy_tlb(&init_mm, curr); 1460 1461 load_sp0(t, thread); 1462 set_tss_desc(cpu, t); 1463 load_TR_desc(); 1464 load_mm_ldt(&init_mm); 1465 1466 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1467 1468 #ifdef CONFIG_DOUBLEFAULT 1469 /* Set up doublefault TSS pointer in the GDT */ 1470 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1471 #endif 1472 1473 clear_all_debug_regs(); 1474 dbg_restore_debug_regs(); 1475 1476 fpu__init_cpu(); 1477 } 1478 #endif 1479 1480 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS 1481 void warn_pre_alternatives(void) 1482 { 1483 WARN(1, "You're using static_cpu_has before alternatives have run!\n"); 1484 } 1485 EXPORT_SYMBOL_GPL(warn_pre_alternatives); 1486 #endif 1487 1488 inline bool __static_cpu_has_safe(u16 bit) 1489 { 1490 return boot_cpu_has(bit); 1491 } 1492 EXPORT_SYMBOL_GPL(__static_cpu_has_safe); 1493 1494 static void bsp_resume(void) 1495 { 1496 if (this_cpu->c_bsp_resume) 1497 this_cpu->c_bsp_resume(&boot_cpu_data); 1498 } 1499 1500 static struct syscore_ops cpu_syscore_ops = { 1501 .resume = bsp_resume, 1502 }; 1503 1504 static int __init init_cpu_syscore(void) 1505 { 1506 register_syscore_ops(&cpu_syscore_ops); 1507 return 0; 1508 } 1509 core_initcall(init_cpu_syscore); 1510