1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/mem_encrypt.h> 22 #include <linux/smp.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/pgtable.h> 27 #include <linux/stackprotector.h> 28 #include <linux/utsname.h> 29 30 #include <asm/alternative.h> 31 #include <asm/cmdline.h> 32 #include <asm/cpuid.h> 33 #include <asm/perf_event.h> 34 #include <asm/mmu_context.h> 35 #include <asm/doublefault.h> 36 #include <asm/archrandom.h> 37 #include <asm/hypervisor.h> 38 #include <asm/processor.h> 39 #include <asm/tlbflush.h> 40 #include <asm/debugreg.h> 41 #include <asm/sections.h> 42 #include <asm/vsyscall.h> 43 #include <linux/topology.h> 44 #include <linux/cpumask.h> 45 #include <linux/atomic.h> 46 #include <asm/proto.h> 47 #include <asm/setup.h> 48 #include <asm/apic.h> 49 #include <asm/desc.h> 50 #include <asm/fpu/api.h> 51 #include <asm/mtrr.h> 52 #include <asm/hwcap2.h> 53 #include <linux/numa.h> 54 #include <asm/numa.h> 55 #include <asm/asm.h> 56 #include <asm/bugs.h> 57 #include <asm/cpu.h> 58 #include <asm/mce.h> 59 #include <asm/msr.h> 60 #include <asm/cacheinfo.h> 61 #include <asm/memtype.h> 62 #include <asm/microcode.h> 63 #include <asm/intel-family.h> 64 #include <asm/cpu_device_id.h> 65 #include <asm/fred.h> 66 #include <asm/uv/uv.h> 67 #include <asm/ia32.h> 68 #include <asm/set_memory.h> 69 #include <asm/traps.h> 70 #include <asm/sev.h> 71 #include <asm/tdx.h> 72 #include <asm/posted_intr.h> 73 #include <asm/runtime-const.h> 74 75 #include "cpu.h" 76 77 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 78 EXPORT_PER_CPU_SYMBOL(cpu_info); 79 80 u32 elf_hwcap2 __read_mostly; 81 82 /* Number of siblings per CPU package */ 83 unsigned int __max_threads_per_core __ro_after_init = 1; 84 EXPORT_SYMBOL(__max_threads_per_core); 85 86 unsigned int __max_dies_per_package __ro_after_init = 1; 87 EXPORT_SYMBOL(__max_dies_per_package); 88 89 unsigned int __max_logical_packages __ro_after_init = 1; 90 EXPORT_SYMBOL(__max_logical_packages); 91 92 unsigned int __num_cores_per_package __ro_after_init = 1; 93 EXPORT_SYMBOL(__num_cores_per_package); 94 95 unsigned int __num_threads_per_package __ro_after_init = 1; 96 EXPORT_SYMBOL(__num_threads_per_package); 97 98 static struct ppin_info { 99 int feature; 100 int msr_ppin_ctl; 101 int msr_ppin; 102 } ppin_info[] = { 103 [X86_VENDOR_INTEL] = { 104 .feature = X86_FEATURE_INTEL_PPIN, 105 .msr_ppin_ctl = MSR_PPIN_CTL, 106 .msr_ppin = MSR_PPIN 107 }, 108 [X86_VENDOR_AMD] = { 109 .feature = X86_FEATURE_AMD_PPIN, 110 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 111 .msr_ppin = MSR_AMD_PPIN 112 }, 113 }; 114 115 static const struct x86_cpu_id ppin_cpuids[] = { 116 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 117 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 118 119 /* Legacy models without CPUID enumeration */ 120 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 125 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 126 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 127 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 128 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 129 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 130 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 131 132 {} 133 }; 134 135 static void ppin_init(struct cpuinfo_x86 *c) 136 { 137 const struct x86_cpu_id *id; 138 unsigned long long val; 139 struct ppin_info *info; 140 141 id = x86_match_cpu(ppin_cpuids); 142 if (!id) 143 return; 144 145 /* 146 * Testing the presence of the MSR is not enough. Need to check 147 * that the PPIN_CTL allows reading of the PPIN. 148 */ 149 info = (struct ppin_info *)id->driver_data; 150 151 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 152 goto clear_ppin; 153 154 if ((val & 3UL) == 1UL) { 155 /* PPIN locked in disabled mode */ 156 goto clear_ppin; 157 } 158 159 /* If PPIN is disabled, try to enable */ 160 if (!(val & 2UL)) { 161 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 162 rdmsrl_safe(info->msr_ppin_ctl, &val); 163 } 164 165 /* Is the enable bit set? */ 166 if (val & 2UL) { 167 c->ppin = __rdmsr(info->msr_ppin); 168 set_cpu_cap(c, info->feature); 169 return; 170 } 171 172 clear_ppin: 173 setup_clear_cpu_cap(info->feature); 174 } 175 176 static void default_init(struct cpuinfo_x86 *c) 177 { 178 #ifdef CONFIG_X86_64 179 cpu_detect_cache_sizes(c); 180 #else 181 /* Not much we can do here... */ 182 /* Check if at least it has cpuid */ 183 if (c->cpuid_level == -1) { 184 /* No cpuid. It must be an ancient CPU */ 185 if (c->x86 == 4) 186 strcpy(c->x86_model_id, "486"); 187 else if (c->x86 == 3) 188 strcpy(c->x86_model_id, "386"); 189 } 190 #endif 191 } 192 193 static const struct cpu_dev default_cpu = { 194 .c_init = default_init, 195 .c_vendor = "Unknown", 196 .c_x86_vendor = X86_VENDOR_UNKNOWN, 197 }; 198 199 static const struct cpu_dev *this_cpu = &default_cpu; 200 201 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 202 #ifdef CONFIG_X86_64 203 /* 204 * We need valid kernel segments for data and code in long mode too 205 * IRET will check the segment types kkeil 2000/10/28 206 * Also sysret mandates a special GDT layout 207 * 208 * TLS descriptors are currently at a different place compared to i386. 209 * Hopefully nobody expects them at a fixed place (Wine?) 210 */ 211 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 212 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 213 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff), 214 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 215 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff), 216 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff), 217 #else 218 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 219 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 220 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 221 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff), 222 /* 223 * Segments used for calling PnP BIOS have byte granularity. 224 * They code segments and data segments have fixed 64k limits, 225 * the transfer segment sizes are set at run time. 226 */ 227 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 228 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 229 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff), 230 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 231 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 232 /* 233 * The APM segments have byte granularity and their bases 234 * are set at run time. All have 64k limits. 235 */ 236 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 237 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 238 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff), 239 240 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 241 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 242 #endif 243 } }; 244 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 245 246 #ifdef CONFIG_X86_64 247 static int __init x86_nopcid_setup(char *s) 248 { 249 /* nopcid doesn't accept parameters */ 250 if (s) 251 return -EINVAL; 252 253 /* do not emit a message if the feature is not present */ 254 if (!boot_cpu_has(X86_FEATURE_PCID)) 255 return 0; 256 257 setup_clear_cpu_cap(X86_FEATURE_PCID); 258 pr_info("nopcid: PCID feature disabled\n"); 259 return 0; 260 } 261 early_param("nopcid", x86_nopcid_setup); 262 #endif 263 264 static int __init x86_noinvpcid_setup(char *s) 265 { 266 /* noinvpcid doesn't accept parameters */ 267 if (s) 268 return -EINVAL; 269 270 /* do not emit a message if the feature is not present */ 271 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 272 return 0; 273 274 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 275 pr_info("noinvpcid: INVPCID feature disabled\n"); 276 return 0; 277 } 278 early_param("noinvpcid", x86_noinvpcid_setup); 279 280 /* Standard macro to see if a specific flag is changeable */ 281 static inline bool flag_is_changeable_p(unsigned long flag) 282 { 283 unsigned long f1, f2; 284 285 if (!IS_ENABLED(CONFIG_X86_32)) 286 return true; 287 288 /* 289 * Cyrix and IDT cpus allow disabling of CPUID 290 * so the code below may return different results 291 * when it is executed before and after enabling 292 * the CPUID. Add "volatile" to not allow gcc to 293 * optimize the subsequent calls to this function. 294 */ 295 asm volatile ("pushfl \n\t" 296 "pushfl \n\t" 297 "popl %0 \n\t" 298 "movl %0, %1 \n\t" 299 "xorl %2, %0 \n\t" 300 "pushl %0 \n\t" 301 "popfl \n\t" 302 "pushfl \n\t" 303 "popl %0 \n\t" 304 "popfl \n\t" 305 306 : "=&r" (f1), "=&r" (f2) 307 : "ir" (flag)); 308 309 return (f1 ^ f2) & flag; 310 } 311 312 #ifdef CONFIG_X86_32 313 static int cachesize_override = -1; 314 static int disable_x86_serial_nr = 1; 315 316 static int __init cachesize_setup(char *str) 317 { 318 get_option(&str, &cachesize_override); 319 return 1; 320 } 321 __setup("cachesize=", cachesize_setup); 322 323 /* Probe for the CPUID instruction */ 324 bool have_cpuid_p(void) 325 { 326 return flag_is_changeable_p(X86_EFLAGS_ID); 327 } 328 329 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 330 { 331 unsigned long lo, hi; 332 333 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 334 return; 335 336 /* Disable processor serial number: */ 337 338 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 339 lo |= 0x200000; 340 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 341 342 pr_notice("CPU serial number disabled.\n"); 343 clear_cpu_cap(c, X86_FEATURE_PN); 344 345 /* Disabling the serial number may affect the cpuid level */ 346 c->cpuid_level = cpuid_eax(0); 347 } 348 349 static int __init x86_serial_nr_setup(char *s) 350 { 351 disable_x86_serial_nr = 0; 352 return 1; 353 } 354 __setup("serialnumber", x86_serial_nr_setup); 355 #else 356 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 357 { 358 } 359 #endif 360 361 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 362 { 363 if (cpu_has(c, X86_FEATURE_SMEP)) 364 cr4_set_bits(X86_CR4_SMEP); 365 } 366 367 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 368 { 369 unsigned long eflags = native_save_fl(); 370 371 /* This should have been cleared long ago */ 372 BUG_ON(eflags & X86_EFLAGS_AC); 373 374 if (cpu_has(c, X86_FEATURE_SMAP)) 375 cr4_set_bits(X86_CR4_SMAP); 376 } 377 378 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 379 { 380 /* Check the boot processor, plus build option for UMIP. */ 381 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 382 goto out; 383 384 /* Check the current processor's cpuid bits. */ 385 if (!cpu_has(c, X86_FEATURE_UMIP)) 386 goto out; 387 388 cr4_set_bits(X86_CR4_UMIP); 389 390 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 391 392 return; 393 394 out: 395 /* 396 * Make sure UMIP is disabled in case it was enabled in a 397 * previous boot (e.g., via kexec). 398 */ 399 cr4_clear_bits(X86_CR4_UMIP); 400 } 401 402 /* These bits should not change their value after CPU init is finished. */ 403 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 404 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; 405 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 406 static unsigned long cr4_pinned_bits __ro_after_init; 407 408 void native_write_cr0(unsigned long val) 409 { 410 unsigned long bits_missing = 0; 411 412 set_register: 413 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 414 415 if (static_branch_likely(&cr_pinning)) { 416 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 417 bits_missing = X86_CR0_WP; 418 val |= bits_missing; 419 goto set_register; 420 } 421 /* Warn after we've set the missing bits. */ 422 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 423 } 424 } 425 EXPORT_SYMBOL(native_write_cr0); 426 427 void __no_profile native_write_cr4(unsigned long val) 428 { 429 unsigned long bits_changed = 0; 430 431 set_register: 432 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 433 434 if (static_branch_likely(&cr_pinning)) { 435 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 436 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 437 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 438 goto set_register; 439 } 440 /* Warn after we've corrected the changed bits. */ 441 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 442 bits_changed); 443 } 444 } 445 #if IS_MODULE(CONFIG_LKDTM) 446 EXPORT_SYMBOL_GPL(native_write_cr4); 447 #endif 448 449 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 450 { 451 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 452 453 lockdep_assert_irqs_disabled(); 454 455 newval = (cr4 & ~clear) | set; 456 if (newval != cr4) { 457 this_cpu_write(cpu_tlbstate.cr4, newval); 458 __write_cr4(newval); 459 } 460 } 461 EXPORT_SYMBOL(cr4_update_irqsoff); 462 463 /* Read the CR4 shadow. */ 464 unsigned long cr4_read_shadow(void) 465 { 466 return this_cpu_read(cpu_tlbstate.cr4); 467 } 468 EXPORT_SYMBOL_GPL(cr4_read_shadow); 469 470 void cr4_init(void) 471 { 472 unsigned long cr4 = __read_cr4(); 473 474 if (boot_cpu_has(X86_FEATURE_PCID)) 475 cr4 |= X86_CR4_PCIDE; 476 if (static_branch_likely(&cr_pinning)) 477 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 478 479 __write_cr4(cr4); 480 481 /* Initialize cr4 shadow for this CPU. */ 482 this_cpu_write(cpu_tlbstate.cr4, cr4); 483 } 484 485 /* 486 * Once CPU feature detection is finished (and boot params have been 487 * parsed), record any of the sensitive CR bits that are set, and 488 * enable CR pinning. 489 */ 490 static void __init setup_cr_pinning(void) 491 { 492 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 493 static_key_enable(&cr_pinning.key); 494 } 495 496 static __init int x86_nofsgsbase_setup(char *arg) 497 { 498 /* Require an exact match without trailing characters. */ 499 if (strlen(arg)) 500 return 0; 501 502 /* Do not emit a message if the feature is not present. */ 503 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 504 return 1; 505 506 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 507 pr_info("FSGSBASE disabled via kernel command line\n"); 508 return 1; 509 } 510 __setup("nofsgsbase", x86_nofsgsbase_setup); 511 512 /* 513 * Protection Keys are not available in 32-bit mode. 514 */ 515 static bool pku_disabled; 516 517 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 518 { 519 if (c == &boot_cpu_data) { 520 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 521 return; 522 /* 523 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 524 * bit to be set. Enforce it. 525 */ 526 setup_force_cpu_cap(X86_FEATURE_OSPKE); 527 528 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 529 return; 530 } 531 532 cr4_set_bits(X86_CR4_PKE); 533 /* Load the default PKRU value */ 534 pkru_write_default(); 535 } 536 537 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 538 static __init int setup_disable_pku(char *arg) 539 { 540 /* 541 * Do not clear the X86_FEATURE_PKU bit. All of the 542 * runtime checks are against OSPKE so clearing the 543 * bit does nothing. 544 * 545 * This way, we will see "pku" in cpuinfo, but not 546 * "ospke", which is exactly what we want. It shows 547 * that the CPU has PKU, but the OS has not enabled it. 548 * This happens to be exactly how a system would look 549 * if we disabled the config option. 550 */ 551 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 552 pku_disabled = true; 553 return 1; 554 } 555 __setup("nopku", setup_disable_pku); 556 #endif 557 558 #ifdef CONFIG_X86_KERNEL_IBT 559 560 __noendbr u64 ibt_save(bool disable) 561 { 562 u64 msr = 0; 563 564 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 565 rdmsrl(MSR_IA32_S_CET, msr); 566 if (disable) 567 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 568 } 569 570 return msr; 571 } 572 573 __noendbr void ibt_restore(u64 save) 574 { 575 u64 msr; 576 577 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 578 rdmsrl(MSR_IA32_S_CET, msr); 579 msr &= ~CET_ENDBR_EN; 580 msr |= (save & CET_ENDBR_EN); 581 wrmsrl(MSR_IA32_S_CET, msr); 582 } 583 } 584 585 #endif 586 587 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 588 { 589 bool user_shstk, kernel_ibt; 590 591 if (!IS_ENABLED(CONFIG_X86_CET)) 592 return; 593 594 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 595 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 596 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 597 598 if (!kernel_ibt && !user_shstk) 599 return; 600 601 if (user_shstk) 602 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 603 604 if (kernel_ibt) 605 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN); 606 else 607 wrmsrl(MSR_IA32_S_CET, 0); 608 609 cr4_set_bits(X86_CR4_CET); 610 611 if (kernel_ibt && ibt_selftest()) { 612 pr_err("IBT selftest: Failed!\n"); 613 wrmsrl(MSR_IA32_S_CET, 0); 614 setup_clear_cpu_cap(X86_FEATURE_IBT); 615 } 616 } 617 618 __noendbr void cet_disable(void) 619 { 620 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 621 cpu_feature_enabled(X86_FEATURE_SHSTK))) 622 return; 623 624 wrmsrl(MSR_IA32_S_CET, 0); 625 wrmsrl(MSR_IA32_U_CET, 0); 626 } 627 628 /* 629 * Some CPU features depend on higher CPUID levels, which may not always 630 * be available due to CPUID level capping or broken virtualization 631 * software. Add those features to this table to auto-disable them. 632 */ 633 struct cpuid_dependent_feature { 634 u32 feature; 635 u32 level; 636 }; 637 638 static const struct cpuid_dependent_feature 639 cpuid_dependent_features[] = { 640 { X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT }, 641 { X86_FEATURE_DCA, CPUID_LEAF_DCA }, 642 { X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE }, 643 { 0, 0 } 644 }; 645 646 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 647 { 648 const struct cpuid_dependent_feature *df; 649 650 for (df = cpuid_dependent_features; df->feature; df++) { 651 652 if (!cpu_has(c, df->feature)) 653 continue; 654 /* 655 * Note: cpuid_level is set to -1 if unavailable, but 656 * extended_extended_level is set to 0 if unavailable 657 * and the legitimate extended levels are all negative 658 * when signed; hence the weird messing around with 659 * signs here... 660 */ 661 if (!((s32)df->level < 0 ? 662 (u32)df->level > (u32)c->extended_cpuid_level : 663 (s32)df->level > (s32)c->cpuid_level)) 664 continue; 665 666 clear_cpu_cap(c, df->feature); 667 if (!warn) 668 continue; 669 670 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 671 x86_cap_flag(df->feature), df->level); 672 } 673 } 674 675 /* 676 * Naming convention should be: <Name> [(<Codename>)] 677 * This table only is used unless init_<vendor>() below doesn't set it; 678 * in particular, if CPUID levels 0x80000002..4 are supported, this 679 * isn't used 680 */ 681 682 /* Look up CPU names by table lookup. */ 683 static const char *table_lookup_model(struct cpuinfo_x86 *c) 684 { 685 #ifdef CONFIG_X86_32 686 const struct legacy_cpu_model_info *info; 687 688 if (c->x86_model >= 16) 689 return NULL; /* Range check */ 690 691 if (!this_cpu) 692 return NULL; 693 694 info = this_cpu->legacy_models; 695 696 while (info->family) { 697 if (info->family == c->x86) 698 return info->model_names[c->x86_model]; 699 info++; 700 } 701 #endif 702 return NULL; /* Not found */ 703 } 704 705 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 706 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 707 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 708 709 #ifdef CONFIG_X86_32 710 /* The 32-bit entry code needs to find cpu_entry_area. */ 711 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 712 #endif 713 714 /* Load the original GDT from the per-cpu structure */ 715 void load_direct_gdt(int cpu) 716 { 717 struct desc_ptr gdt_descr; 718 719 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 720 gdt_descr.size = GDT_SIZE - 1; 721 load_gdt(&gdt_descr); 722 } 723 EXPORT_SYMBOL_GPL(load_direct_gdt); 724 725 /* Load a fixmap remapping of the per-cpu GDT */ 726 void load_fixmap_gdt(int cpu) 727 { 728 struct desc_ptr gdt_descr; 729 730 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 731 gdt_descr.size = GDT_SIZE - 1; 732 load_gdt(&gdt_descr); 733 } 734 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 735 736 /** 737 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 738 * @cpu: The CPU number for which this is invoked 739 * 740 * Invoked during early boot to switch from early GDT and early per CPU to 741 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 742 * switch is implicit by loading the direct GDT. On 64bit this requires 743 * to update GSBASE. 744 */ 745 void __init switch_gdt_and_percpu_base(int cpu) 746 { 747 load_direct_gdt(cpu); 748 749 #ifdef CONFIG_X86_64 750 /* 751 * No need to load %gs. It is already correct. 752 * 753 * Writing %gs on 64bit would zero GSBASE which would make any per 754 * CPU operation up to the point of the wrmsrl() fault. 755 * 756 * Set GSBASE to the new offset. Until the wrmsrl() happens the 757 * early mapping is still valid. That means the GSBASE update will 758 * lose any prior per CPU data which was not copied over in 759 * setup_per_cpu_areas(). 760 * 761 * This works even with stackprotector enabled because the 762 * per CPU stack canary is 0 in both per CPU areas. 763 */ 764 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 765 #else 766 /* 767 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 768 * it is required to load FS again so that the 'hidden' part is 769 * updated from the new GDT. Up to this point the early per CPU 770 * translation is active. Any content of the early per CPU data 771 * which was not copied over in setup_per_cpu_areas() is lost. 772 */ 773 loadsegment(fs, __KERNEL_PERCPU); 774 #endif 775 } 776 777 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 778 779 static void get_model_name(struct cpuinfo_x86 *c) 780 { 781 unsigned int *v; 782 char *p, *q, *s; 783 784 if (c->extended_cpuid_level < 0x80000004) 785 return; 786 787 v = (unsigned int *)c->x86_model_id; 788 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 789 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 790 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 791 c->x86_model_id[48] = 0; 792 793 /* Trim whitespace */ 794 p = q = s = &c->x86_model_id[0]; 795 796 while (*p == ' ') 797 p++; 798 799 while (*p) { 800 /* Note the last non-whitespace index */ 801 if (!isspace(*p)) 802 s = q; 803 804 *q++ = *p++; 805 } 806 807 *(s + 1) = '\0'; 808 } 809 810 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 811 { 812 unsigned int n, dummy, ebx, ecx, edx, l2size; 813 814 n = c->extended_cpuid_level; 815 816 if (n >= 0x80000005) { 817 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 818 c->x86_cache_size = (ecx>>24) + (edx>>24); 819 #ifdef CONFIG_X86_64 820 /* On K8 L1 TLB is inclusive, so don't count it */ 821 c->x86_tlbsize = 0; 822 #endif 823 } 824 825 if (n < 0x80000006) /* Some chips just has a large L1. */ 826 return; 827 828 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 829 l2size = ecx >> 16; 830 831 #ifdef CONFIG_X86_64 832 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 833 #else 834 /* do processor-specific cache resizing */ 835 if (this_cpu->legacy_cache_size) 836 l2size = this_cpu->legacy_cache_size(c, l2size); 837 838 /* Allow user to override all this if necessary. */ 839 if (cachesize_override != -1) 840 l2size = cachesize_override; 841 842 if (l2size == 0) 843 return; /* Again, no L2 cache is possible */ 844 #endif 845 846 c->x86_cache_size = l2size; 847 } 848 849 u16 __read_mostly tlb_lli_4k[NR_INFO]; 850 u16 __read_mostly tlb_lli_2m[NR_INFO]; 851 u16 __read_mostly tlb_lli_4m[NR_INFO]; 852 u16 __read_mostly tlb_lld_4k[NR_INFO]; 853 u16 __read_mostly tlb_lld_2m[NR_INFO]; 854 u16 __read_mostly tlb_lld_4m[NR_INFO]; 855 u16 __read_mostly tlb_lld_1g[NR_INFO]; 856 857 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 858 { 859 if (this_cpu->c_detect_tlb) 860 this_cpu->c_detect_tlb(c); 861 862 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 863 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 864 tlb_lli_4m[ENTRIES]); 865 866 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 867 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 868 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 869 } 870 871 void get_cpu_vendor(struct cpuinfo_x86 *c) 872 { 873 char *v = c->x86_vendor_id; 874 int i; 875 876 for (i = 0; i < X86_VENDOR_NUM; i++) { 877 if (!cpu_devs[i]) 878 break; 879 880 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 881 (cpu_devs[i]->c_ident[1] && 882 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 883 884 this_cpu = cpu_devs[i]; 885 c->x86_vendor = this_cpu->c_x86_vendor; 886 return; 887 } 888 } 889 890 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 891 "CPU: Your system may be unstable.\n", v); 892 893 c->x86_vendor = X86_VENDOR_UNKNOWN; 894 this_cpu = &default_cpu; 895 } 896 897 void cpu_detect(struct cpuinfo_x86 *c) 898 { 899 /* Get vendor name */ 900 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 901 (unsigned int *)&c->x86_vendor_id[0], 902 (unsigned int *)&c->x86_vendor_id[8], 903 (unsigned int *)&c->x86_vendor_id[4]); 904 905 c->x86 = 4; 906 /* Intel-defined flags: level 0x00000001 */ 907 if (c->cpuid_level >= 0x00000001) { 908 u32 junk, tfms, cap0, misc; 909 910 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 911 c->x86 = x86_family(tfms); 912 c->x86_model = x86_model(tfms); 913 c->x86_stepping = x86_stepping(tfms); 914 915 if (cap0 & (1<<19)) { 916 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 917 c->x86_cache_alignment = c->x86_clflush_size; 918 } 919 } 920 } 921 922 static void apply_forced_caps(struct cpuinfo_x86 *c) 923 { 924 int i; 925 926 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 927 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 928 c->x86_capability[i] |= cpu_caps_set[i]; 929 } 930 } 931 932 static void init_speculation_control(struct cpuinfo_x86 *c) 933 { 934 /* 935 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 936 * and they also have a different bit for STIBP support. Also, 937 * a hypervisor might have set the individual AMD bits even on 938 * Intel CPUs, for finer-grained selection of what's available. 939 */ 940 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 941 set_cpu_cap(c, X86_FEATURE_IBRS); 942 set_cpu_cap(c, X86_FEATURE_IBPB); 943 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 944 } 945 946 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 947 set_cpu_cap(c, X86_FEATURE_STIBP); 948 949 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 950 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 951 set_cpu_cap(c, X86_FEATURE_SSBD); 952 953 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 954 set_cpu_cap(c, X86_FEATURE_IBRS); 955 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 956 } 957 958 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 959 set_cpu_cap(c, X86_FEATURE_IBPB); 960 961 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 962 set_cpu_cap(c, X86_FEATURE_STIBP); 963 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 964 } 965 966 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 967 set_cpu_cap(c, X86_FEATURE_SSBD); 968 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 969 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 970 } 971 } 972 973 void get_cpu_cap(struct cpuinfo_x86 *c) 974 { 975 u32 eax, ebx, ecx, edx; 976 977 /* Intel-defined flags: level 0x00000001 */ 978 if (c->cpuid_level >= 0x00000001) { 979 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 980 981 c->x86_capability[CPUID_1_ECX] = ecx; 982 c->x86_capability[CPUID_1_EDX] = edx; 983 } 984 985 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 986 if (c->cpuid_level >= 0x00000006) 987 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 988 989 /* Additional Intel-defined flags: level 0x00000007 */ 990 if (c->cpuid_level >= 0x00000007) { 991 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 992 c->x86_capability[CPUID_7_0_EBX] = ebx; 993 c->x86_capability[CPUID_7_ECX] = ecx; 994 c->x86_capability[CPUID_7_EDX] = edx; 995 996 /* Check valid sub-leaf index before accessing it */ 997 if (eax >= 1) { 998 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 999 c->x86_capability[CPUID_7_1_EAX] = eax; 1000 } 1001 } 1002 1003 /* Extended state features: level 0x0000000d */ 1004 if (c->cpuid_level >= 0x0000000d) { 1005 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1006 1007 c->x86_capability[CPUID_D_1_EAX] = eax; 1008 } 1009 1010 /* AMD-defined flags: level 0x80000001 */ 1011 eax = cpuid_eax(0x80000000); 1012 c->extended_cpuid_level = eax; 1013 1014 if ((eax & 0xffff0000) == 0x80000000) { 1015 if (eax >= 0x80000001) { 1016 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1017 1018 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1019 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1020 } 1021 } 1022 1023 if (c->extended_cpuid_level >= 0x80000007) { 1024 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1025 1026 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1027 c->x86_power = edx; 1028 } 1029 1030 if (c->extended_cpuid_level >= 0x80000008) { 1031 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1032 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1033 } 1034 1035 if (c->extended_cpuid_level >= 0x8000000a) 1036 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1037 1038 if (c->extended_cpuid_level >= 0x8000001f) 1039 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1040 1041 if (c->extended_cpuid_level >= 0x80000021) 1042 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1043 1044 init_scattered_cpuid_features(c); 1045 init_speculation_control(c); 1046 1047 /* 1048 * Clear/Set all flags overridden by options, after probe. 1049 * This needs to happen each time we re-probe, which may happen 1050 * several times during CPU initialization. 1051 */ 1052 apply_forced_caps(c); 1053 } 1054 1055 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1056 { 1057 u32 eax, ebx, ecx, edx; 1058 1059 if (!cpu_has(c, X86_FEATURE_CPUID) || 1060 (c->extended_cpuid_level < 0x80000008)) { 1061 if (IS_ENABLED(CONFIG_X86_64)) { 1062 c->x86_clflush_size = 64; 1063 c->x86_phys_bits = 36; 1064 c->x86_virt_bits = 48; 1065 } else { 1066 c->x86_clflush_size = 32; 1067 c->x86_virt_bits = 32; 1068 c->x86_phys_bits = 32; 1069 1070 if (cpu_has(c, X86_FEATURE_PAE) || 1071 cpu_has(c, X86_FEATURE_PSE36)) 1072 c->x86_phys_bits = 36; 1073 } 1074 } else { 1075 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1076 1077 c->x86_virt_bits = (eax >> 8) & 0xff; 1078 c->x86_phys_bits = eax & 0xff; 1079 1080 /* Provide a sane default if not enumerated: */ 1081 if (!c->x86_clflush_size) 1082 c->x86_clflush_size = 32; 1083 } 1084 1085 c->x86_cache_bits = c->x86_phys_bits; 1086 c->x86_cache_alignment = c->x86_clflush_size; 1087 } 1088 1089 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1090 { 1091 int i; 1092 1093 /* 1094 * First of all, decide if this is a 486 or higher 1095 * It's a 486 if we can modify the AC flag 1096 */ 1097 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1098 c->x86 = 4; 1099 else 1100 c->x86 = 3; 1101 1102 for (i = 0; i < X86_VENDOR_NUM; i++) 1103 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1104 c->x86_vendor_id[0] = 0; 1105 cpu_devs[i]->c_identify(c); 1106 if (c->x86_vendor_id[0]) { 1107 get_cpu_vendor(c); 1108 break; 1109 } 1110 } 1111 } 1112 1113 #define NO_SPECULATION BIT(0) 1114 #define NO_MELTDOWN BIT(1) 1115 #define NO_SSB BIT(2) 1116 #define NO_L1TF BIT(3) 1117 #define NO_MDS BIT(4) 1118 #define MSBDS_ONLY BIT(5) 1119 #define NO_SWAPGS BIT(6) 1120 #define NO_ITLB_MULTIHIT BIT(7) 1121 #define NO_SPECTRE_V2 BIT(8) 1122 #define NO_MMIO BIT(9) 1123 #define NO_EIBRS_PBRSB BIT(10) 1124 #define NO_BHI BIT(11) 1125 1126 #define VULNWL(vendor, family, model, whitelist) \ 1127 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1128 1129 #define VULNWL_INTEL(vfm, whitelist) \ 1130 X86_MATCH_VFM(vfm, whitelist) 1131 1132 #define VULNWL_AMD(family, whitelist) \ 1133 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1134 1135 #define VULNWL_HYGON(family, whitelist) \ 1136 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1137 1138 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1139 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1140 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1141 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1142 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1143 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1144 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1145 1146 /* Intel Family 6 */ 1147 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), 1148 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), 1149 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), 1150 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), 1151 1152 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1153 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1154 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1155 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1156 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1157 1158 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1159 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1160 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1161 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1162 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1163 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1164 1165 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), 1166 1167 VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY), 1168 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1169 1170 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1171 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1172 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1173 1174 /* 1175 * Technically, swapgs isn't serializing on AMD (despite it previously 1176 * being documented as such in the APM). But according to AMD, %gs is 1177 * updated non-speculatively, and the issuing of %gs-relative memory 1178 * operands will be blocked until the %gs update completes, which is 1179 * good enough for our purposes. 1180 */ 1181 1182 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), 1183 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1184 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1185 1186 /* AMD Family 0xf - 0x12 */ 1187 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1188 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1189 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1190 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1191 1192 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1193 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1194 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1195 1196 /* Zhaoxin Family 7 */ 1197 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1198 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1199 {} 1200 }; 1201 1202 #define VULNBL(vendor, family, model, blacklist) \ 1203 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1204 1205 #define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \ 1206 X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues) 1207 1208 #define VULNBL_AMD(family, blacklist) \ 1209 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1210 1211 #define VULNBL_HYGON(family, blacklist) \ 1212 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1213 1214 #define SRBDS BIT(0) 1215 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1216 #define MMIO BIT(1) 1217 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1218 #define MMIO_SBDS BIT(2) 1219 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1220 #define RETBLEED BIT(3) 1221 /* CPU is affected by SMT (cross-thread) return predictions */ 1222 #define SMT_RSB BIT(4) 1223 /* CPU is affected by SRSO */ 1224 #define SRSO BIT(5) 1225 /* CPU is affected by GDS */ 1226 #define GDS BIT(6) 1227 /* CPU is affected by Register File Data Sampling */ 1228 #define RFDS BIT(7) 1229 1230 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1231 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS), 1232 VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS), 1233 VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS), 1234 VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS), 1235 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO), 1236 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO), 1237 VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS), 1238 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO), 1239 VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS), 1240 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS), 1241 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS), 1242 VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS), 1243 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS), 1244 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS), 1245 VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED), 1246 VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS), 1247 VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS), 1248 VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS), 1249 VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS), 1250 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED), 1251 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS), 1252 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS), 1253 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS), 1254 VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED), 1255 VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS), 1256 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE, X86_STEP_MAX, RFDS), 1257 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS), 1258 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE, X86_STEP_MAX, RFDS), 1259 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS), 1260 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS), 1261 VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS), 1262 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1263 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS), 1264 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1265 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS), 1266 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS), 1267 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS), 1268 1269 VULNBL_AMD(0x15, RETBLEED), 1270 VULNBL_AMD(0x16, RETBLEED), 1271 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), 1272 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), 1273 VULNBL_AMD(0x19, SRSO), 1274 VULNBL_AMD(0x1a, SRSO), 1275 {} 1276 }; 1277 1278 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1279 { 1280 const struct x86_cpu_id *m = x86_match_cpu(table); 1281 1282 return m && !!(m->driver_data & which); 1283 } 1284 1285 u64 x86_read_arch_cap_msr(void) 1286 { 1287 u64 x86_arch_cap_msr = 0; 1288 1289 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1290 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1291 1292 return x86_arch_cap_msr; 1293 } 1294 1295 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr) 1296 { 1297 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO && 1298 x86_arch_cap_msr & ARCH_CAP_PSDP_NO && 1299 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO); 1300 } 1301 1302 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr) 1303 { 1304 /* The "immunity" bit trumps everything else: */ 1305 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO) 1306 return false; 1307 1308 /* 1309 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to 1310 * indicate that mitigation is needed because guest is running on a 1311 * vulnerable hardware or may migrate to such hardware: 1312 */ 1313 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 1314 return true; 1315 1316 /* Only consult the blacklist when there is no enumeration: */ 1317 return cpu_matches(cpu_vuln_blacklist, RFDS); 1318 } 1319 1320 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1321 { 1322 u64 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1323 1324 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1325 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1326 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO)) 1327 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1328 1329 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1330 return; 1331 1332 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1333 1334 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1335 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1336 1337 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1338 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) && 1339 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1340 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1341 1342 /* 1343 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1344 * flag and protect from vendor-specific bugs via the whitelist. 1345 * 1346 * Don't use AutoIBRS when SNP is enabled because it degrades host 1347 * userspace indirect branch performance. 1348 */ 1349 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || 1350 (cpu_has(c, X86_FEATURE_AUTOIBRS) && 1351 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { 1352 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1353 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1354 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO)) 1355 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1356 } 1357 1358 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1359 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) { 1360 setup_force_cpu_bug(X86_BUG_MDS); 1361 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1362 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1363 } 1364 1365 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1366 setup_force_cpu_bug(X86_BUG_SWAPGS); 1367 1368 /* 1369 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1370 * - TSX is supported or 1371 * - TSX_CTRL is present 1372 * 1373 * TSX_CTRL check is needed for cases when TSX could be disabled before 1374 * the kernel boot e.g. kexec. 1375 * TSX_CTRL check alone is not sufficient for cases when the microcode 1376 * update is not present or running as guest that don't get TSX_CTRL. 1377 */ 1378 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) && 1379 (cpu_has(c, X86_FEATURE_RTM) || 1380 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))) 1381 setup_force_cpu_bug(X86_BUG_TAA); 1382 1383 /* 1384 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1385 * in the vulnerability blacklist. 1386 * 1387 * Some of the implications and mitigation of Shared Buffers Data 1388 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1389 * SRBDS. 1390 */ 1391 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1392 cpu_has(c, X86_FEATURE_RDSEED)) && 1393 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1394 setup_force_cpu_bug(X86_BUG_SRBDS); 1395 1396 /* 1397 * Processor MMIO Stale Data bug enumeration 1398 * 1399 * Affected CPU list is generally enough to enumerate the vulnerability, 1400 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1401 * not want the guest to enumerate the bug. 1402 * 1403 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1404 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1405 */ 1406 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { 1407 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1408 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1409 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1410 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1411 } 1412 1413 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1414 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA)) 1415 setup_force_cpu_bug(X86_BUG_RETBLEED); 1416 } 1417 1418 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1419 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1420 1421 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1422 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1423 setup_force_cpu_bug(X86_BUG_SRSO); 1424 } 1425 1426 /* 1427 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1428 * an affected processor, the VMM may have disabled the use of GATHER by 1429 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1430 * which means that AVX will be disabled. 1431 */ 1432 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) && 1433 boot_cpu_has(X86_FEATURE_AVX)) 1434 setup_force_cpu_bug(X86_BUG_GDS); 1435 1436 if (vulnerable_to_rfds(x86_arch_cap_msr)) 1437 setup_force_cpu_bug(X86_BUG_RFDS); 1438 1439 /* When virtualized, eIBRS could be hidden, assume vulnerable */ 1440 if (!(x86_arch_cap_msr & ARCH_CAP_BHI_NO) && 1441 !cpu_matches(cpu_vuln_whitelist, NO_BHI) && 1442 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) || 1443 boot_cpu_has(X86_FEATURE_HYPERVISOR))) 1444 setup_force_cpu_bug(X86_BUG_BHI); 1445 1446 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET)) 1447 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET); 1448 1449 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1450 return; 1451 1452 /* Rogue Data Cache Load? No! */ 1453 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO) 1454 return; 1455 1456 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1457 1458 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1459 return; 1460 1461 setup_force_cpu_bug(X86_BUG_L1TF); 1462 } 1463 1464 /* 1465 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1466 * unfortunately, that's not true in practice because of early VIA 1467 * chips and (more importantly) broken virtualizers that are not easy 1468 * to detect. In the latter case it doesn't even *fail* reliably, so 1469 * probing for it doesn't even work. Disable it completely on 32-bit 1470 * unless we can find a reliable way to detect all the broken cases. 1471 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1472 */ 1473 static void detect_nopl(void) 1474 { 1475 #ifdef CONFIG_X86_32 1476 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1477 #else 1478 setup_force_cpu_cap(X86_FEATURE_NOPL); 1479 #endif 1480 } 1481 1482 /* 1483 * We parse cpu parameters early because fpu__init_system() is executed 1484 * before parse_early_param(). 1485 */ 1486 static void __init cpu_parse_early_param(void) 1487 { 1488 char arg[128]; 1489 char *argptr = arg, *opt; 1490 int arglen, taint = 0; 1491 1492 #ifdef CONFIG_X86_32 1493 if (cmdline_find_option_bool(boot_command_line, "no387")) 1494 #ifdef CONFIG_MATH_EMULATION 1495 setup_clear_cpu_cap(X86_FEATURE_FPU); 1496 #else 1497 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1498 #endif 1499 1500 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1501 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1502 #endif 1503 1504 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1505 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1506 1507 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1508 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1509 1510 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1511 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1512 1513 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1514 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1515 1516 /* Minimize the gap between FRED is available and available but disabled. */ 1517 arglen = cmdline_find_option(boot_command_line, "fred", arg, sizeof(arg)); 1518 if (arglen != 2 || strncmp(arg, "on", 2)) 1519 setup_clear_cpu_cap(X86_FEATURE_FRED); 1520 1521 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1522 if (arglen <= 0) 1523 return; 1524 1525 pr_info("Clearing CPUID bits:"); 1526 1527 while (argptr) { 1528 bool found __maybe_unused = false; 1529 unsigned int bit; 1530 1531 opt = strsep(&argptr, ","); 1532 1533 /* 1534 * Handle naked numbers first for feature flags which don't 1535 * have names. 1536 */ 1537 if (!kstrtouint(opt, 10, &bit)) { 1538 if (bit < NCAPINTS * 32) { 1539 1540 /* empty-string, i.e., ""-defined feature flags */ 1541 if (!x86_cap_flags[bit]) 1542 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1543 else 1544 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1545 1546 setup_clear_cpu_cap(bit); 1547 taint++; 1548 } 1549 /* 1550 * The assumption is that there are no feature names with only 1551 * numbers in the name thus go to the next argument. 1552 */ 1553 continue; 1554 } 1555 1556 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1557 if (!x86_cap_flag(bit)) 1558 continue; 1559 1560 if (strcmp(x86_cap_flag(bit), opt)) 1561 continue; 1562 1563 pr_cont(" %s", opt); 1564 setup_clear_cpu_cap(bit); 1565 taint++; 1566 found = true; 1567 break; 1568 } 1569 1570 if (!found) 1571 pr_cont(" (unknown: %s)", opt); 1572 } 1573 pr_cont("\n"); 1574 1575 if (taint) 1576 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1577 } 1578 1579 /* 1580 * Do minimum CPU detection early. 1581 * Fields really needed: vendor, cpuid_level, family, model, mask, 1582 * cache alignment. 1583 * The others are not touched to avoid unwanted side effects. 1584 * 1585 * WARNING: this function is only called on the boot CPU. Don't add code 1586 * here that is supposed to run on all CPUs. 1587 */ 1588 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1589 { 1590 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1591 c->extended_cpuid_level = 0; 1592 1593 if (!have_cpuid_p()) 1594 identify_cpu_without_cpuid(c); 1595 1596 /* cyrix could have cpuid enabled via c_identify()*/ 1597 if (have_cpuid_p()) { 1598 cpu_detect(c); 1599 get_cpu_vendor(c); 1600 intel_unlock_cpuid_leafs(c); 1601 get_cpu_cap(c); 1602 setup_force_cpu_cap(X86_FEATURE_CPUID); 1603 get_cpu_address_sizes(c); 1604 cpu_parse_early_param(); 1605 1606 cpu_init_topology(c); 1607 1608 if (this_cpu->c_early_init) 1609 this_cpu->c_early_init(c); 1610 1611 c->cpu_index = 0; 1612 filter_cpuid_features(c, false); 1613 1614 if (this_cpu->c_bsp_init) 1615 this_cpu->c_bsp_init(c); 1616 } else { 1617 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1618 get_cpu_address_sizes(c); 1619 cpu_init_topology(c); 1620 } 1621 1622 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1623 1624 cpu_set_bug_bits(c); 1625 1626 sld_setup(c); 1627 1628 #ifdef CONFIG_X86_32 1629 /* 1630 * Regardless of whether PCID is enumerated, the SDM says 1631 * that it can't be enabled in 32-bit mode. 1632 */ 1633 setup_clear_cpu_cap(X86_FEATURE_PCID); 1634 #endif 1635 1636 /* 1637 * Later in the boot process pgtable_l5_enabled() relies on 1638 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1639 * enabled by this point we need to clear the feature bit to avoid 1640 * false-positives at the later stage. 1641 * 1642 * pgtable_l5_enabled() can be false here for several reasons: 1643 * - 5-level paging is disabled compile-time; 1644 * - it's 32-bit kernel; 1645 * - machine doesn't support 5-level paging; 1646 * - user specified 'no5lvl' in kernel command line. 1647 */ 1648 if (!pgtable_l5_enabled()) 1649 setup_clear_cpu_cap(X86_FEATURE_LA57); 1650 1651 detect_nopl(); 1652 } 1653 1654 void __init init_cpu_devs(void) 1655 { 1656 const struct cpu_dev *const *cdev; 1657 int count = 0; 1658 1659 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1660 const struct cpu_dev *cpudev = *cdev; 1661 1662 if (count >= X86_VENDOR_NUM) 1663 break; 1664 cpu_devs[count] = cpudev; 1665 count++; 1666 } 1667 } 1668 1669 void __init early_cpu_init(void) 1670 { 1671 #ifdef CONFIG_PROCESSOR_SELECT 1672 unsigned int i, j; 1673 1674 pr_info("KERNEL supported cpus:\n"); 1675 #endif 1676 1677 init_cpu_devs(); 1678 1679 #ifdef CONFIG_PROCESSOR_SELECT 1680 for (i = 0; i < X86_VENDOR_NUM && cpu_devs[i]; i++) { 1681 for (j = 0; j < 2; j++) { 1682 if (!cpu_devs[i]->c_ident[j]) 1683 continue; 1684 pr_info(" %s %s\n", cpu_devs[i]->c_vendor, 1685 cpu_devs[i]->c_ident[j]); 1686 } 1687 } 1688 #endif 1689 1690 early_identify_cpu(&boot_cpu_data); 1691 } 1692 1693 static bool detect_null_seg_behavior(void) 1694 { 1695 /* 1696 * Empirically, writing zero to a segment selector on AMD does 1697 * not clear the base, whereas writing zero to a segment 1698 * selector on Intel does clear the base. Intel's behavior 1699 * allows slightly faster context switches in the common case 1700 * where GS is unused by the prev and next threads. 1701 * 1702 * Since neither vendor documents this anywhere that I can see, 1703 * detect it directly instead of hard-coding the choice by 1704 * vendor. 1705 * 1706 * I've designated AMD's behavior as the "bug" because it's 1707 * counterintuitive and less friendly. 1708 */ 1709 1710 unsigned long old_base, tmp; 1711 rdmsrl(MSR_FS_BASE, old_base); 1712 wrmsrl(MSR_FS_BASE, 1); 1713 loadsegment(fs, 0); 1714 rdmsrl(MSR_FS_BASE, tmp); 1715 wrmsrl(MSR_FS_BASE, old_base); 1716 return tmp == 0; 1717 } 1718 1719 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1720 { 1721 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1722 if (!IS_ENABLED(CONFIG_X86_64)) 1723 return; 1724 1725 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1726 return; 1727 1728 /* 1729 * CPUID bit above wasn't set. If this kernel is still running 1730 * as a HV guest, then the HV has decided not to advertize 1731 * that CPUID bit for whatever reason. For example, one 1732 * member of the migration pool might be vulnerable. Which 1733 * means, the bug is present: set the BUG flag and return. 1734 */ 1735 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1736 set_cpu_bug(c, X86_BUG_NULL_SEG); 1737 return; 1738 } 1739 1740 /* 1741 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1742 * 0x18 is the respective family for Hygon. 1743 */ 1744 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1745 detect_null_seg_behavior()) 1746 return; 1747 1748 /* All the remaining ones are affected */ 1749 set_cpu_bug(c, X86_BUG_NULL_SEG); 1750 } 1751 1752 static void generic_identify(struct cpuinfo_x86 *c) 1753 { 1754 c->extended_cpuid_level = 0; 1755 1756 if (!have_cpuid_p()) 1757 identify_cpu_without_cpuid(c); 1758 1759 /* cyrix could have cpuid enabled via c_identify()*/ 1760 if (!have_cpuid_p()) 1761 return; 1762 1763 cpu_detect(c); 1764 1765 get_cpu_vendor(c); 1766 intel_unlock_cpuid_leafs(c); 1767 get_cpu_cap(c); 1768 1769 get_cpu_address_sizes(c); 1770 1771 get_model_name(c); /* Default name */ 1772 1773 /* 1774 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1775 * systems that run Linux at CPL > 0 may or may not have the 1776 * issue, but, even if they have the issue, there's absolutely 1777 * nothing we can do about it because we can't use the real IRET 1778 * instruction. 1779 * 1780 * NB: For the time being, only 32-bit kernels support 1781 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1782 * whether to apply espfix using paravirt hooks. If any 1783 * non-paravirt system ever shows up that does *not* have the 1784 * ESPFIX issue, we can change this. 1785 */ 1786 #ifdef CONFIG_X86_32 1787 set_cpu_bug(c, X86_BUG_ESPFIX); 1788 #endif 1789 } 1790 1791 /* 1792 * This does the hard work of actually picking apart the CPU stuff... 1793 */ 1794 static void identify_cpu(struct cpuinfo_x86 *c) 1795 { 1796 int i; 1797 1798 c->loops_per_jiffy = loops_per_jiffy; 1799 c->x86_cache_size = 0; 1800 c->x86_vendor = X86_VENDOR_UNKNOWN; 1801 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1802 c->x86_vendor_id[0] = '\0'; /* Unset */ 1803 c->x86_model_id[0] = '\0'; /* Unset */ 1804 #ifdef CONFIG_X86_64 1805 c->x86_clflush_size = 64; 1806 c->x86_phys_bits = 36; 1807 c->x86_virt_bits = 48; 1808 #else 1809 c->cpuid_level = -1; /* CPUID not detected */ 1810 c->x86_clflush_size = 32; 1811 c->x86_phys_bits = 32; 1812 c->x86_virt_bits = 32; 1813 #endif 1814 c->x86_cache_alignment = c->x86_clflush_size; 1815 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1816 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1817 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1818 #endif 1819 1820 generic_identify(c); 1821 1822 cpu_parse_topology(c); 1823 1824 if (this_cpu->c_identify) 1825 this_cpu->c_identify(c); 1826 1827 /* Clear/Set all flags overridden by options, after probe */ 1828 apply_forced_caps(c); 1829 1830 /* 1831 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 1832 * Hygon will clear it in ->c_init() below. 1833 */ 1834 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1835 1836 /* 1837 * Vendor-specific initialization. In this section we 1838 * canonicalize the feature flags, meaning if there are 1839 * features a certain CPU supports which CPUID doesn't 1840 * tell us, CPUID claiming incorrect flags, or other bugs, 1841 * we handle them here. 1842 * 1843 * At the end of this section, c->x86_capability better 1844 * indicate the features this CPU genuinely supports! 1845 */ 1846 if (this_cpu->c_init) 1847 this_cpu->c_init(c); 1848 1849 bus_lock_init(); 1850 1851 /* Disable the PN if appropriate */ 1852 squash_the_stupid_serial_number(c); 1853 1854 /* Set up SMEP/SMAP/UMIP */ 1855 setup_smep(c); 1856 setup_smap(c); 1857 setup_umip(c); 1858 1859 /* Enable FSGSBASE instructions if available. */ 1860 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1861 cr4_set_bits(X86_CR4_FSGSBASE); 1862 elf_hwcap2 |= HWCAP2_FSGSBASE; 1863 } 1864 1865 /* 1866 * The vendor-specific functions might have changed features. 1867 * Now we do "generic changes." 1868 */ 1869 1870 /* Filter out anything that depends on CPUID levels we don't have */ 1871 filter_cpuid_features(c, true); 1872 1873 /* If the model name is still unset, do table lookup. */ 1874 if (!c->x86_model_id[0]) { 1875 const char *p; 1876 p = table_lookup_model(c); 1877 if (p) 1878 strcpy(c->x86_model_id, p); 1879 else 1880 /* Last resort... */ 1881 sprintf(c->x86_model_id, "%02x/%02x", 1882 c->x86, c->x86_model); 1883 } 1884 1885 x86_init_rdrand(c); 1886 setup_pku(c); 1887 setup_cet(c); 1888 1889 /* 1890 * Clear/Set all flags overridden by options, need do it 1891 * before following smp all cpus cap AND. 1892 */ 1893 apply_forced_caps(c); 1894 1895 /* 1896 * On SMP, boot_cpu_data holds the common feature set between 1897 * all CPUs; so make sure that we indicate which features are 1898 * common between the CPUs. The first time this routine gets 1899 * executed, c == &boot_cpu_data. 1900 */ 1901 if (c != &boot_cpu_data) { 1902 /* AND the already accumulated flags with these */ 1903 for (i = 0; i < NCAPINTS; i++) 1904 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1905 1906 /* OR, i.e. replicate the bug flags */ 1907 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1908 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1909 } 1910 1911 ppin_init(c); 1912 1913 /* Init Machine Check Exception if available. */ 1914 mcheck_cpu_init(c); 1915 1916 numa_add_cpu(smp_processor_id()); 1917 } 1918 1919 /* 1920 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1921 * on 32-bit kernels: 1922 */ 1923 #ifdef CONFIG_X86_32 1924 void enable_sep_cpu(void) 1925 { 1926 struct tss_struct *tss; 1927 int cpu; 1928 1929 if (!boot_cpu_has(X86_FEATURE_SEP)) 1930 return; 1931 1932 cpu = get_cpu(); 1933 tss = &per_cpu(cpu_tss_rw, cpu); 1934 1935 /* 1936 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1937 * see the big comment in struct x86_hw_tss's definition. 1938 */ 1939 1940 tss->x86_tss.ss1 = __KERNEL_CS; 1941 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1942 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1943 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1944 1945 put_cpu(); 1946 } 1947 #endif 1948 1949 static __init void identify_boot_cpu(void) 1950 { 1951 identify_cpu(&boot_cpu_data); 1952 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1953 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1954 #ifdef CONFIG_X86_32 1955 enable_sep_cpu(); 1956 #endif 1957 cpu_detect_tlb(&boot_cpu_data); 1958 setup_cr_pinning(); 1959 1960 tsx_init(); 1961 tdx_init(); 1962 lkgs_init(); 1963 } 1964 1965 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1966 { 1967 BUG_ON(c == &boot_cpu_data); 1968 identify_cpu(c); 1969 #ifdef CONFIG_X86_32 1970 enable_sep_cpu(); 1971 #endif 1972 x86_spec_ctrl_setup_ap(); 1973 update_srbds_msr(); 1974 if (boot_cpu_has_bug(X86_BUG_GDS)) 1975 update_gds_msr(); 1976 1977 tsx_ap_init(); 1978 } 1979 1980 void print_cpu_info(struct cpuinfo_x86 *c) 1981 { 1982 const char *vendor = NULL; 1983 1984 if (c->x86_vendor < X86_VENDOR_NUM) { 1985 vendor = this_cpu->c_vendor; 1986 } else { 1987 if (c->cpuid_level >= 0) 1988 vendor = c->x86_vendor_id; 1989 } 1990 1991 if (vendor && !strstr(c->x86_model_id, vendor)) 1992 pr_cont("%s ", vendor); 1993 1994 if (c->x86_model_id[0]) 1995 pr_cont("%s", c->x86_model_id); 1996 else 1997 pr_cont("%d86", c->x86); 1998 1999 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2000 2001 if (c->x86_stepping || c->cpuid_level >= 0) 2002 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2003 else 2004 pr_cont(")\n"); 2005 } 2006 2007 /* 2008 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 2009 * function prevents it from becoming an environment variable for init. 2010 */ 2011 static __init int setup_clearcpuid(char *arg) 2012 { 2013 return 1; 2014 } 2015 __setup("clearcpuid=", setup_clearcpuid); 2016 2017 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = { 2018 .current_task = &init_task, 2019 .preempt_count = INIT_PREEMPT_COUNT, 2020 .top_of_stack = TOP_OF_INIT_STACK, 2021 }; 2022 EXPORT_PER_CPU_SYMBOL(pcpu_hot); 2023 EXPORT_PER_CPU_SYMBOL(const_pcpu_hot); 2024 2025 #ifdef CONFIG_X86_64 2026 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 2027 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 2028 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2029 2030 static void wrmsrl_cstar(unsigned long val) 2031 { 2032 /* 2033 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2034 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2035 * guest. Avoid the pointless write on all Intel CPUs. 2036 */ 2037 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2038 wrmsrl(MSR_CSTAR, val); 2039 } 2040 2041 static inline void idt_syscall_init(void) 2042 { 2043 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2044 2045 if (ia32_enabled()) { 2046 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2047 /* 2048 * This only works on Intel CPUs. 2049 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2050 * This does not cause SYSENTER to jump to the wrong location, because 2051 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2052 */ 2053 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2054 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2055 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2056 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2057 } else { 2058 wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore); 2059 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2060 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2061 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2062 } 2063 2064 /* 2065 * Flags to clear on syscall; clear as much as possible 2066 * to minimize user space-kernel interference. 2067 */ 2068 wrmsrl(MSR_SYSCALL_MASK, 2069 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2070 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2071 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2072 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2073 X86_EFLAGS_AC|X86_EFLAGS_ID); 2074 } 2075 2076 /* May not be marked __init: used by software suspend */ 2077 void syscall_init(void) 2078 { 2079 /* The default user and kernel segments */ 2080 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2081 2082 /* 2083 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and 2084 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED 2085 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit 2086 * instruction to return to ring 3 (both sysexit and sysret cause 2087 * #UD when FRED is enabled). 2088 */ 2089 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2090 idt_syscall_init(); 2091 } 2092 2093 #else /* CONFIG_X86_64 */ 2094 2095 #ifdef CONFIG_STACKPROTECTOR 2096 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2097 #ifndef CONFIG_SMP 2098 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2099 #endif 2100 #endif 2101 2102 #endif /* CONFIG_X86_64 */ 2103 2104 /* 2105 * Clear all 6 debug registers: 2106 */ 2107 static void clear_all_debug_regs(void) 2108 { 2109 int i; 2110 2111 for (i = 0; i < 8; i++) { 2112 /* Ignore db4, db5 */ 2113 if ((i == 4) || (i == 5)) 2114 continue; 2115 2116 set_debugreg(0, i); 2117 } 2118 } 2119 2120 #ifdef CONFIG_KGDB 2121 /* 2122 * Restore debug regs if using kgdbwait and you have a kernel debugger 2123 * connection established. 2124 */ 2125 static void dbg_restore_debug_regs(void) 2126 { 2127 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2128 arch_kgdb_ops.correct_hw_break(); 2129 } 2130 #else /* ! CONFIG_KGDB */ 2131 #define dbg_restore_debug_regs() 2132 #endif /* ! CONFIG_KGDB */ 2133 2134 static inline void setup_getcpu(int cpu) 2135 { 2136 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2137 struct desc_struct d = { }; 2138 2139 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2140 wrmsr(MSR_TSC_AUX, cpudata, 0); 2141 2142 /* Store CPU and node number in limit. */ 2143 d.limit0 = cpudata; 2144 d.limit1 = cpudata >> 16; 2145 2146 d.type = 5; /* RO data, expand down, accessed */ 2147 d.dpl = 3; /* Visible to user code */ 2148 d.s = 1; /* Not a system segment */ 2149 d.p = 1; /* Present */ 2150 d.d = 1; /* 32-bit */ 2151 2152 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2153 } 2154 2155 #ifdef CONFIG_X86_64 2156 static inline void tss_setup_ist(struct tss_struct *tss) 2157 { 2158 /* Set up the per-CPU TSS IST stacks */ 2159 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2160 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2161 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2162 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2163 /* Only mapped when SEV-ES is active */ 2164 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2165 } 2166 #else /* CONFIG_X86_64 */ 2167 static inline void tss_setup_ist(struct tss_struct *tss) { } 2168 #endif /* !CONFIG_X86_64 */ 2169 2170 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2171 { 2172 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2173 2174 #ifdef CONFIG_X86_IOPL_IOPERM 2175 tss->io_bitmap.prev_max = 0; 2176 tss->io_bitmap.prev_sequence = 0; 2177 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2178 /* 2179 * Invalidate the extra array entry past the end of the all 2180 * permission bitmap as required by the hardware. 2181 */ 2182 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2183 #endif 2184 } 2185 2186 /* 2187 * Setup everything needed to handle exceptions from the IDT, including the IST 2188 * exceptions which use paranoid_entry(). 2189 */ 2190 void cpu_init_exception_handling(bool boot_cpu) 2191 { 2192 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2193 int cpu = raw_smp_processor_id(); 2194 2195 /* paranoid_entry() gets the CPU number from the GDT */ 2196 setup_getcpu(cpu); 2197 2198 /* For IDT mode, IST vectors need to be set in TSS. */ 2199 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2200 tss_setup_ist(tss); 2201 tss_setup_io_bitmap(tss); 2202 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2203 2204 load_TR_desc(); 2205 2206 /* GHCB needs to be setup to handle #VC. */ 2207 setup_ghcb(); 2208 2209 if (cpu_feature_enabled(X86_FEATURE_FRED)) { 2210 /* The boot CPU has enabled FRED during early boot */ 2211 if (!boot_cpu) 2212 cpu_init_fred_exceptions(); 2213 2214 cpu_init_fred_rsps(); 2215 } else { 2216 load_current_idt(); 2217 } 2218 } 2219 2220 void __init cpu_init_replace_early_idt(void) 2221 { 2222 if (cpu_feature_enabled(X86_FEATURE_FRED)) 2223 cpu_init_fred_exceptions(); 2224 else 2225 idt_setup_early_pf(); 2226 } 2227 2228 /* 2229 * cpu_init() initializes state that is per-CPU. Some data is already 2230 * initialized (naturally) in the bootstrap process, such as the GDT. We 2231 * reload it nevertheless, this function acts as a 'CPU state barrier', 2232 * nothing should get across. 2233 */ 2234 void cpu_init(void) 2235 { 2236 struct task_struct *cur = current; 2237 int cpu = raw_smp_processor_id(); 2238 2239 #ifdef CONFIG_NUMA 2240 if (this_cpu_read(numa_node) == 0 && 2241 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2242 set_numa_node(early_cpu_to_node(cpu)); 2243 #endif 2244 pr_debug("Initializing CPU#%d\n", cpu); 2245 2246 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2247 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2248 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2249 2250 if (IS_ENABLED(CONFIG_X86_64)) { 2251 loadsegment(fs, 0); 2252 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2253 syscall_init(); 2254 2255 wrmsrl(MSR_FS_BASE, 0); 2256 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2257 barrier(); 2258 2259 x2apic_setup(); 2260 2261 intel_posted_msi_init(); 2262 } 2263 2264 mmgrab(&init_mm); 2265 cur->active_mm = &init_mm; 2266 BUG_ON(cur->mm); 2267 initialize_tlbstate_and_flush(); 2268 enter_lazy_tlb(&init_mm, cur); 2269 2270 /* 2271 * sp0 points to the entry trampoline stack regardless of what task 2272 * is running. 2273 */ 2274 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2275 2276 load_mm_ldt(&init_mm); 2277 2278 clear_all_debug_regs(); 2279 dbg_restore_debug_regs(); 2280 2281 doublefault_init_cpu_tss(); 2282 2283 if (is_uv_system()) 2284 uv_cpu_init(); 2285 2286 load_fixmap_gdt(cpu); 2287 } 2288 2289 #ifdef CONFIG_MICROCODE_LATE_LOADING 2290 /** 2291 * store_cpu_caps() - Store a snapshot of CPU capabilities 2292 * @curr_info: Pointer where to store it 2293 * 2294 * Returns: None 2295 */ 2296 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2297 { 2298 /* Reload CPUID max function as it might've changed. */ 2299 curr_info->cpuid_level = cpuid_eax(0); 2300 2301 /* Copy all capability leafs and pick up the synthetic ones. */ 2302 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2303 sizeof(curr_info->x86_capability)); 2304 2305 /* Get the hardware CPUID leafs */ 2306 get_cpu_cap(curr_info); 2307 } 2308 2309 /** 2310 * microcode_check() - Check if any CPU capabilities changed after an update. 2311 * @prev_info: CPU capabilities stored before an update. 2312 * 2313 * The microcode loader calls this upon late microcode load to recheck features, 2314 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2315 * 2316 * Return: None 2317 */ 2318 void microcode_check(struct cpuinfo_x86 *prev_info) 2319 { 2320 struct cpuinfo_x86 curr_info; 2321 2322 perf_check_microcode(); 2323 2324 amd_check_microcode(); 2325 2326 store_cpu_caps(&curr_info); 2327 2328 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2329 sizeof(prev_info->x86_capability))) 2330 return; 2331 2332 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2333 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2334 } 2335 #endif 2336 2337 /* 2338 * Invoked from core CPU hotplug code after hotplug operations 2339 */ 2340 void arch_smt_update(void) 2341 { 2342 /* Handle the speculative execution misfeatures */ 2343 cpu_bugs_smt_update(); 2344 /* Check whether IPI broadcasting can be enabled */ 2345 apic_smt_update(); 2346 } 2347 2348 void __init arch_cpu_finalize_init(void) 2349 { 2350 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 2351 2352 identify_boot_cpu(); 2353 2354 select_idle_routine(); 2355 2356 /* 2357 * identify_boot_cpu() initialized SMT support information, let the 2358 * core code know. 2359 */ 2360 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core); 2361 2362 if (!IS_ENABLED(CONFIG_SMP)) { 2363 pr_info("CPU: "); 2364 print_cpu_info(&boot_cpu_data); 2365 } 2366 2367 cpu_select_mitigations(); 2368 2369 arch_smt_update(); 2370 2371 if (IS_ENABLED(CONFIG_X86_32)) { 2372 /* 2373 * Check whether this is a real i386 which is not longer 2374 * supported and fixup the utsname. 2375 */ 2376 if (boot_cpu_data.x86 < 4) 2377 panic("Kernel requires i486+ for 'invlpg' and other features"); 2378 2379 init_utsname()->machine[1] = 2380 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2381 } 2382 2383 /* 2384 * Must be before alternatives because it might set or clear 2385 * feature bits. 2386 */ 2387 fpu__init_system(); 2388 fpu__init_cpu(); 2389 2390 /* 2391 * Ensure that access to the per CPU representation has the initial 2392 * boot CPU configuration. 2393 */ 2394 *c = boot_cpu_data; 2395 c->initialized = true; 2396 2397 alternative_instructions(); 2398 2399 if (IS_ENABLED(CONFIG_X86_64)) { 2400 unsigned long USER_PTR_MAX = TASK_SIZE_MAX; 2401 2402 /* 2403 * Enable this when LAM is gated on LASS support 2404 if (cpu_feature_enabled(X86_FEATURE_LAM)) 2405 USER_PTR_MAX = (1ul << 63) - PAGE_SIZE; 2406 */ 2407 runtime_const_init(ptr, USER_PTR_MAX); 2408 2409 /* 2410 * Make sure the first 2MB area is not mapped by huge pages 2411 * There are typically fixed size MTRRs in there and overlapping 2412 * MTRRs into large pages causes slow downs. 2413 * 2414 * Right now we don't do that with gbpages because there seems 2415 * very little benefit for that case. 2416 */ 2417 if (!direct_gbpages) 2418 set_memory_4k((unsigned long)__va(0), 1); 2419 } else { 2420 fpu__init_check_bugs(); 2421 } 2422 2423 /* 2424 * This needs to be called before any devices perform DMA 2425 * operations that might use the SWIOTLB bounce buffers. It will 2426 * mark the bounce buffers as decrypted so that their usage will 2427 * not cause "plain-text" data to be decrypted when accessed. It 2428 * must be called after late_time_init() so that Hyper-V x86/x64 2429 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2430 */ 2431 mem_encrypt_init(); 2432 } 2433