1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 51 #ifdef CONFIG_X86_LOCAL_APIC 52 #include <asm/uv/uv.h> 53 #endif 54 55 #include "cpu.h" 56 57 u32 elf_hwcap2 __read_mostly; 58 59 /* all of these masks are initialized in setup_cpu_local_masks() */ 60 cpumask_var_t cpu_initialized_mask; 61 cpumask_var_t cpu_callout_mask; 62 cpumask_var_t cpu_callin_mask; 63 64 /* representing cpus for which sibling maps can be computed */ 65 cpumask_var_t cpu_sibling_setup_mask; 66 67 /* correctly size the local cpu masks */ 68 void __init setup_cpu_local_masks(void) 69 { 70 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 71 alloc_bootmem_cpumask_var(&cpu_callin_mask); 72 alloc_bootmem_cpumask_var(&cpu_callout_mask); 73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 74 } 75 76 static void default_init(struct cpuinfo_x86 *c) 77 { 78 #ifdef CONFIG_X86_64 79 cpu_detect_cache_sizes(c); 80 #else 81 /* Not much we can do here... */ 82 /* Check if at least it has cpuid */ 83 if (c->cpuid_level == -1) { 84 /* No cpuid. It must be an ancient CPU */ 85 if (c->x86 == 4) 86 strcpy(c->x86_model_id, "486"); 87 else if (c->x86 == 3) 88 strcpy(c->x86_model_id, "386"); 89 } 90 #endif 91 } 92 93 static const struct cpu_dev default_cpu = { 94 .c_init = default_init, 95 .c_vendor = "Unknown", 96 .c_x86_vendor = X86_VENDOR_UNKNOWN, 97 }; 98 99 static const struct cpu_dev *this_cpu = &default_cpu; 100 101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 102 #ifdef CONFIG_X86_64 103 /* 104 * We need valid kernel segments for data and code in long mode too 105 * IRET will check the segment types kkeil 2000/10/28 106 * Also sysret mandates a special GDT layout 107 * 108 * TLS descriptors are currently at a different place compared to i386. 109 * Hopefully nobody expects them at a fixed place (Wine?) 110 */ 111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 117 #else 118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 122 /* 123 * Segments used for calling PnP BIOS have byte granularity. 124 * They code segments and data segments have fixed 64k limits, 125 * the transfer segment sizes are set at run time. 126 */ 127 /* 32-bit code */ 128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 129 /* 16-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 131 /* 16-bit data */ 132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 138 * The APM segments have byte granularity and their bases 139 * are set at run time. All have 64k limits. 140 */ 141 /* 32-bit code */ 142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 143 /* 16-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 145 /* data */ 146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 147 148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 150 GDT_STACK_CANARY_INIT 151 #endif 152 } }; 153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 154 155 static int __init x86_mpx_setup(char *s) 156 { 157 /* require an exact match without trailing characters */ 158 if (strlen(s)) 159 return 0; 160 161 /* do not emit a message if the feature is not present */ 162 if (!boot_cpu_has(X86_FEATURE_MPX)) 163 return 1; 164 165 setup_clear_cpu_cap(X86_FEATURE_MPX); 166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 167 return 1; 168 } 169 __setup("nompx", x86_mpx_setup); 170 171 #ifdef CONFIG_X86_64 172 static int __init x86_nopcid_setup(char *s) 173 { 174 /* nopcid doesn't accept parameters */ 175 if (s) 176 return -EINVAL; 177 178 /* do not emit a message if the feature is not present */ 179 if (!boot_cpu_has(X86_FEATURE_PCID)) 180 return 0; 181 182 setup_clear_cpu_cap(X86_FEATURE_PCID); 183 pr_info("nopcid: PCID feature disabled\n"); 184 return 0; 185 } 186 early_param("nopcid", x86_nopcid_setup); 187 #endif 188 189 static int __init x86_noinvpcid_setup(char *s) 190 { 191 /* noinvpcid doesn't accept parameters */ 192 if (s) 193 return -EINVAL; 194 195 /* do not emit a message if the feature is not present */ 196 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 197 return 0; 198 199 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 200 pr_info("noinvpcid: INVPCID feature disabled\n"); 201 return 0; 202 } 203 early_param("noinvpcid", x86_noinvpcid_setup); 204 205 #ifdef CONFIG_X86_32 206 static int cachesize_override = -1; 207 static int disable_x86_serial_nr = 1; 208 209 static int __init cachesize_setup(char *str) 210 { 211 get_option(&str, &cachesize_override); 212 return 1; 213 } 214 __setup("cachesize=", cachesize_setup); 215 216 static int __init x86_sep_setup(char *s) 217 { 218 setup_clear_cpu_cap(X86_FEATURE_SEP); 219 return 1; 220 } 221 __setup("nosep", x86_sep_setup); 222 223 /* Standard macro to see if a specific flag is changeable */ 224 static inline int flag_is_changeable_p(u32 flag) 225 { 226 u32 f1, f2; 227 228 /* 229 * Cyrix and IDT cpus allow disabling of CPUID 230 * so the code below may return different results 231 * when it is executed before and after enabling 232 * the CPUID. Add "volatile" to not allow gcc to 233 * optimize the subsequent calls to this function. 234 */ 235 asm volatile ("pushfl \n\t" 236 "pushfl \n\t" 237 "popl %0 \n\t" 238 "movl %0, %1 \n\t" 239 "xorl %2, %0 \n\t" 240 "pushl %0 \n\t" 241 "popfl \n\t" 242 "pushfl \n\t" 243 "popl %0 \n\t" 244 "popfl \n\t" 245 246 : "=&r" (f1), "=&r" (f2) 247 : "ir" (flag)); 248 249 return ((f1^f2) & flag) != 0; 250 } 251 252 /* Probe for the CPUID instruction */ 253 int have_cpuid_p(void) 254 { 255 return flag_is_changeable_p(X86_EFLAGS_ID); 256 } 257 258 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 259 { 260 unsigned long lo, hi; 261 262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 263 return; 264 265 /* Disable processor serial number: */ 266 267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 268 lo |= 0x200000; 269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 270 271 pr_notice("CPU serial number disabled.\n"); 272 clear_cpu_cap(c, X86_FEATURE_PN); 273 274 /* Disabling the serial number may affect the cpuid level */ 275 c->cpuid_level = cpuid_eax(0); 276 } 277 278 static int __init x86_serial_nr_setup(char *s) 279 { 280 disable_x86_serial_nr = 0; 281 return 1; 282 } 283 __setup("serialnumber", x86_serial_nr_setup); 284 #else 285 static inline int flag_is_changeable_p(u32 flag) 286 { 287 return 1; 288 } 289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 290 { 291 } 292 #endif 293 294 static __init int setup_disable_smep(char *arg) 295 { 296 setup_clear_cpu_cap(X86_FEATURE_SMEP); 297 /* Check for things that depend on SMEP being enabled: */ 298 check_mpx_erratum(&boot_cpu_data); 299 return 1; 300 } 301 __setup("nosmep", setup_disable_smep); 302 303 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 304 { 305 if (cpu_has(c, X86_FEATURE_SMEP)) 306 cr4_set_bits(X86_CR4_SMEP); 307 } 308 309 static __init int setup_disable_smap(char *arg) 310 { 311 setup_clear_cpu_cap(X86_FEATURE_SMAP); 312 return 1; 313 } 314 __setup("nosmap", setup_disable_smap); 315 316 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 317 { 318 unsigned long eflags = native_save_fl(); 319 320 /* This should have been cleared long ago */ 321 BUG_ON(eflags & X86_EFLAGS_AC); 322 323 if (cpu_has(c, X86_FEATURE_SMAP)) { 324 #ifdef CONFIG_X86_SMAP 325 cr4_set_bits(X86_CR4_SMAP); 326 #else 327 cr4_clear_bits(X86_CR4_SMAP); 328 #endif 329 } 330 } 331 332 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 333 { 334 /* Check the boot processor, plus build option for UMIP. */ 335 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 336 goto out; 337 338 /* Check the current processor's cpuid bits. */ 339 if (!cpu_has(c, X86_FEATURE_UMIP)) 340 goto out; 341 342 cr4_set_bits(X86_CR4_UMIP); 343 344 return; 345 346 out: 347 /* 348 * Make sure UMIP is disabled in case it was enabled in a 349 * previous boot (e.g., via kexec). 350 */ 351 cr4_clear_bits(X86_CR4_UMIP); 352 } 353 354 /* 355 * Protection Keys are not available in 32-bit mode. 356 */ 357 static bool pku_disabled; 358 359 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 360 { 361 /* check the boot processor, plus compile options for PKU: */ 362 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 363 return; 364 /* checks the actual processor's cpuid bits: */ 365 if (!cpu_has(c, X86_FEATURE_PKU)) 366 return; 367 if (pku_disabled) 368 return; 369 370 cr4_set_bits(X86_CR4_PKE); 371 /* 372 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 373 * cpuid bit to be set. We need to ensure that we 374 * update that bit in this CPU's "cpu_info". 375 */ 376 get_cpu_cap(c); 377 } 378 379 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 380 static __init int setup_disable_pku(char *arg) 381 { 382 /* 383 * Do not clear the X86_FEATURE_PKU bit. All of the 384 * runtime checks are against OSPKE so clearing the 385 * bit does nothing. 386 * 387 * This way, we will see "pku" in cpuinfo, but not 388 * "ospke", which is exactly what we want. It shows 389 * that the CPU has PKU, but the OS has not enabled it. 390 * This happens to be exactly how a system would look 391 * if we disabled the config option. 392 */ 393 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 394 pku_disabled = true; 395 return 1; 396 } 397 __setup("nopku", setup_disable_pku); 398 #endif /* CONFIG_X86_64 */ 399 400 /* 401 * Some CPU features depend on higher CPUID levels, which may not always 402 * be available due to CPUID level capping or broken virtualization 403 * software. Add those features to this table to auto-disable them. 404 */ 405 struct cpuid_dependent_feature { 406 u32 feature; 407 u32 level; 408 }; 409 410 static const struct cpuid_dependent_feature 411 cpuid_dependent_features[] = { 412 { X86_FEATURE_MWAIT, 0x00000005 }, 413 { X86_FEATURE_DCA, 0x00000009 }, 414 { X86_FEATURE_XSAVE, 0x0000000d }, 415 { 0, 0 } 416 }; 417 418 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 419 { 420 const struct cpuid_dependent_feature *df; 421 422 for (df = cpuid_dependent_features; df->feature; df++) { 423 424 if (!cpu_has(c, df->feature)) 425 continue; 426 /* 427 * Note: cpuid_level is set to -1 if unavailable, but 428 * extended_extended_level is set to 0 if unavailable 429 * and the legitimate extended levels are all negative 430 * when signed; hence the weird messing around with 431 * signs here... 432 */ 433 if (!((s32)df->level < 0 ? 434 (u32)df->level > (u32)c->extended_cpuid_level : 435 (s32)df->level > (s32)c->cpuid_level)) 436 continue; 437 438 clear_cpu_cap(c, df->feature); 439 if (!warn) 440 continue; 441 442 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 443 x86_cap_flag(df->feature), df->level); 444 } 445 } 446 447 /* 448 * Naming convention should be: <Name> [(<Codename>)] 449 * This table only is used unless init_<vendor>() below doesn't set it; 450 * in particular, if CPUID levels 0x80000002..4 are supported, this 451 * isn't used 452 */ 453 454 /* Look up CPU names by table lookup. */ 455 static const char *table_lookup_model(struct cpuinfo_x86 *c) 456 { 457 #ifdef CONFIG_X86_32 458 const struct legacy_cpu_model_info *info; 459 460 if (c->x86_model >= 16) 461 return NULL; /* Range check */ 462 463 if (!this_cpu) 464 return NULL; 465 466 info = this_cpu->legacy_models; 467 468 while (info->family) { 469 if (info->family == c->x86) 470 return info->model_names[c->x86_model]; 471 info++; 472 } 473 #endif 474 return NULL; /* Not found */ 475 } 476 477 __u32 cpu_caps_cleared[NCAPINTS]; 478 __u32 cpu_caps_set[NCAPINTS]; 479 480 void load_percpu_segment(int cpu) 481 { 482 #ifdef CONFIG_X86_32 483 loadsegment(fs, __KERNEL_PERCPU); 484 #else 485 __loadsegment_simple(gs, 0); 486 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 487 #endif 488 load_stack_canary_segment(); 489 } 490 491 /* Setup the fixmap mapping only once per-processor */ 492 static inline void setup_fixmap_gdt(int cpu) 493 { 494 #ifdef CONFIG_X86_64 495 /* On 64-bit systems, we use a read-only fixmap GDT. */ 496 pgprot_t prot = PAGE_KERNEL_RO; 497 #else 498 /* 499 * On native 32-bit systems, the GDT cannot be read-only because 500 * our double fault handler uses a task gate, and entering through 501 * a task gate needs to change an available TSS to busy. If the GDT 502 * is read-only, that will triple fault. 503 * 504 * On Xen PV, the GDT must be read-only because the hypervisor requires 505 * it. 506 */ 507 pgprot_t prot = boot_cpu_has(X86_FEATURE_XENPV) ? 508 PAGE_KERNEL_RO : PAGE_KERNEL; 509 #endif 510 511 __set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot); 512 } 513 514 /* Load the original GDT from the per-cpu structure */ 515 void load_direct_gdt(int cpu) 516 { 517 struct desc_ptr gdt_descr; 518 519 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 520 gdt_descr.size = GDT_SIZE - 1; 521 load_gdt(&gdt_descr); 522 } 523 EXPORT_SYMBOL_GPL(load_direct_gdt); 524 525 /* Load a fixmap remapping of the per-cpu GDT */ 526 void load_fixmap_gdt(int cpu) 527 { 528 struct desc_ptr gdt_descr; 529 530 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 531 gdt_descr.size = GDT_SIZE - 1; 532 load_gdt(&gdt_descr); 533 } 534 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 535 536 /* 537 * Current gdt points %fs at the "master" per-cpu area: after this, 538 * it's on the real one. 539 */ 540 void switch_to_new_gdt(int cpu) 541 { 542 /* Load the original GDT */ 543 load_direct_gdt(cpu); 544 /* Reload the per-cpu base */ 545 load_percpu_segment(cpu); 546 } 547 548 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 549 550 static void get_model_name(struct cpuinfo_x86 *c) 551 { 552 unsigned int *v; 553 char *p, *q, *s; 554 555 if (c->extended_cpuid_level < 0x80000004) 556 return; 557 558 v = (unsigned int *)c->x86_model_id; 559 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 560 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 561 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 562 c->x86_model_id[48] = 0; 563 564 /* Trim whitespace */ 565 p = q = s = &c->x86_model_id[0]; 566 567 while (*p == ' ') 568 p++; 569 570 while (*p) { 571 /* Note the last non-whitespace index */ 572 if (!isspace(*p)) 573 s = q; 574 575 *q++ = *p++; 576 } 577 578 *(s + 1) = '\0'; 579 } 580 581 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 582 { 583 unsigned int n, dummy, ebx, ecx, edx, l2size; 584 585 n = c->extended_cpuid_level; 586 587 if (n >= 0x80000005) { 588 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 589 c->x86_cache_size = (ecx>>24) + (edx>>24); 590 #ifdef CONFIG_X86_64 591 /* On K8 L1 TLB is inclusive, so don't count it */ 592 c->x86_tlbsize = 0; 593 #endif 594 } 595 596 if (n < 0x80000006) /* Some chips just has a large L1. */ 597 return; 598 599 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 600 l2size = ecx >> 16; 601 602 #ifdef CONFIG_X86_64 603 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 604 #else 605 /* do processor-specific cache resizing */ 606 if (this_cpu->legacy_cache_size) 607 l2size = this_cpu->legacy_cache_size(c, l2size); 608 609 /* Allow user to override all this if necessary. */ 610 if (cachesize_override != -1) 611 l2size = cachesize_override; 612 613 if (l2size == 0) 614 return; /* Again, no L2 cache is possible */ 615 #endif 616 617 c->x86_cache_size = l2size; 618 } 619 620 u16 __read_mostly tlb_lli_4k[NR_INFO]; 621 u16 __read_mostly tlb_lli_2m[NR_INFO]; 622 u16 __read_mostly tlb_lli_4m[NR_INFO]; 623 u16 __read_mostly tlb_lld_4k[NR_INFO]; 624 u16 __read_mostly tlb_lld_2m[NR_INFO]; 625 u16 __read_mostly tlb_lld_4m[NR_INFO]; 626 u16 __read_mostly tlb_lld_1g[NR_INFO]; 627 628 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 629 { 630 if (this_cpu->c_detect_tlb) 631 this_cpu->c_detect_tlb(c); 632 633 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 634 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 635 tlb_lli_4m[ENTRIES]); 636 637 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 638 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 639 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 640 } 641 642 void detect_ht(struct cpuinfo_x86 *c) 643 { 644 #ifdef CONFIG_SMP 645 u32 eax, ebx, ecx, edx; 646 int index_msb, core_bits; 647 static bool printed; 648 649 if (!cpu_has(c, X86_FEATURE_HT)) 650 return; 651 652 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 653 goto out; 654 655 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 656 return; 657 658 cpuid(1, &eax, &ebx, &ecx, &edx); 659 660 smp_num_siblings = (ebx & 0xff0000) >> 16; 661 662 if (smp_num_siblings == 1) { 663 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 664 goto out; 665 } 666 667 if (smp_num_siblings <= 1) 668 goto out; 669 670 index_msb = get_count_order(smp_num_siblings); 671 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 672 673 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 674 675 index_msb = get_count_order(smp_num_siblings); 676 677 core_bits = get_count_order(c->x86_max_cores); 678 679 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 680 ((1 << core_bits) - 1); 681 682 out: 683 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 684 pr_info("CPU: Physical Processor ID: %d\n", 685 c->phys_proc_id); 686 pr_info("CPU: Processor Core ID: %d\n", 687 c->cpu_core_id); 688 printed = 1; 689 } 690 #endif 691 } 692 693 static void get_cpu_vendor(struct cpuinfo_x86 *c) 694 { 695 char *v = c->x86_vendor_id; 696 int i; 697 698 for (i = 0; i < X86_VENDOR_NUM; i++) { 699 if (!cpu_devs[i]) 700 break; 701 702 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 703 (cpu_devs[i]->c_ident[1] && 704 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 705 706 this_cpu = cpu_devs[i]; 707 c->x86_vendor = this_cpu->c_x86_vendor; 708 return; 709 } 710 } 711 712 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 713 "CPU: Your system may be unstable.\n", v); 714 715 c->x86_vendor = X86_VENDOR_UNKNOWN; 716 this_cpu = &default_cpu; 717 } 718 719 void cpu_detect(struct cpuinfo_x86 *c) 720 { 721 /* Get vendor name */ 722 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 723 (unsigned int *)&c->x86_vendor_id[0], 724 (unsigned int *)&c->x86_vendor_id[8], 725 (unsigned int *)&c->x86_vendor_id[4]); 726 727 c->x86 = 4; 728 /* Intel-defined flags: level 0x00000001 */ 729 if (c->cpuid_level >= 0x00000001) { 730 u32 junk, tfms, cap0, misc; 731 732 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 733 c->x86 = x86_family(tfms); 734 c->x86_model = x86_model(tfms); 735 c->x86_mask = x86_stepping(tfms); 736 737 if (cap0 & (1<<19)) { 738 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 739 c->x86_cache_alignment = c->x86_clflush_size; 740 } 741 } 742 } 743 744 static void apply_forced_caps(struct cpuinfo_x86 *c) 745 { 746 int i; 747 748 for (i = 0; i < NCAPINTS; i++) { 749 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 750 c->x86_capability[i] |= cpu_caps_set[i]; 751 } 752 } 753 754 void get_cpu_cap(struct cpuinfo_x86 *c) 755 { 756 u32 eax, ebx, ecx, edx; 757 758 /* Intel-defined flags: level 0x00000001 */ 759 if (c->cpuid_level >= 0x00000001) { 760 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 761 762 c->x86_capability[CPUID_1_ECX] = ecx; 763 c->x86_capability[CPUID_1_EDX] = edx; 764 } 765 766 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 767 if (c->cpuid_level >= 0x00000006) 768 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 769 770 /* Additional Intel-defined flags: level 0x00000007 */ 771 if (c->cpuid_level >= 0x00000007) { 772 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 773 c->x86_capability[CPUID_7_0_EBX] = ebx; 774 c->x86_capability[CPUID_7_ECX] = ecx; 775 } 776 777 /* Extended state features: level 0x0000000d */ 778 if (c->cpuid_level >= 0x0000000d) { 779 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 780 781 c->x86_capability[CPUID_D_1_EAX] = eax; 782 } 783 784 /* Additional Intel-defined flags: level 0x0000000F */ 785 if (c->cpuid_level >= 0x0000000F) { 786 787 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 788 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 789 c->x86_capability[CPUID_F_0_EDX] = edx; 790 791 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 792 /* will be overridden if occupancy monitoring exists */ 793 c->x86_cache_max_rmid = ebx; 794 795 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 796 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 797 c->x86_capability[CPUID_F_1_EDX] = edx; 798 799 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 800 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 801 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 802 c->x86_cache_max_rmid = ecx; 803 c->x86_cache_occ_scale = ebx; 804 } 805 } else { 806 c->x86_cache_max_rmid = -1; 807 c->x86_cache_occ_scale = -1; 808 } 809 } 810 811 /* AMD-defined flags: level 0x80000001 */ 812 eax = cpuid_eax(0x80000000); 813 c->extended_cpuid_level = eax; 814 815 if ((eax & 0xffff0000) == 0x80000000) { 816 if (eax >= 0x80000001) { 817 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 818 819 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 820 c->x86_capability[CPUID_8000_0001_EDX] = edx; 821 } 822 } 823 824 if (c->extended_cpuid_level >= 0x80000007) { 825 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 826 827 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 828 c->x86_power = edx; 829 } 830 831 if (c->extended_cpuid_level >= 0x80000008) { 832 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 833 834 c->x86_virt_bits = (eax >> 8) & 0xff; 835 c->x86_phys_bits = eax & 0xff; 836 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 837 } 838 #ifdef CONFIG_X86_32 839 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 840 c->x86_phys_bits = 36; 841 #endif 842 843 if (c->extended_cpuid_level >= 0x8000000a) 844 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 845 846 init_scattered_cpuid_features(c); 847 848 /* 849 * Clear/Set all flags overridden by options, after probe. 850 * This needs to happen each time we re-probe, which may happen 851 * several times during CPU initialization. 852 */ 853 apply_forced_caps(c); 854 } 855 856 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 857 { 858 #ifdef CONFIG_X86_32 859 int i; 860 861 /* 862 * First of all, decide if this is a 486 or higher 863 * It's a 486 if we can modify the AC flag 864 */ 865 if (flag_is_changeable_p(X86_EFLAGS_AC)) 866 c->x86 = 4; 867 else 868 c->x86 = 3; 869 870 for (i = 0; i < X86_VENDOR_NUM; i++) 871 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 872 c->x86_vendor_id[0] = 0; 873 cpu_devs[i]->c_identify(c); 874 if (c->x86_vendor_id[0]) { 875 get_cpu_vendor(c); 876 break; 877 } 878 } 879 #endif 880 } 881 882 /* 883 * Do minimum CPU detection early. 884 * Fields really needed: vendor, cpuid_level, family, model, mask, 885 * cache alignment. 886 * The others are not touched to avoid unwanted side effects. 887 * 888 * WARNING: this function is only called on the boot CPU. Don't add code 889 * here that is supposed to run on all CPUs. 890 */ 891 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 892 { 893 #ifdef CONFIG_X86_64 894 c->x86_clflush_size = 64; 895 c->x86_phys_bits = 36; 896 c->x86_virt_bits = 48; 897 #else 898 c->x86_clflush_size = 32; 899 c->x86_phys_bits = 32; 900 c->x86_virt_bits = 32; 901 #endif 902 c->x86_cache_alignment = c->x86_clflush_size; 903 904 memset(&c->x86_capability, 0, sizeof c->x86_capability); 905 c->extended_cpuid_level = 0; 906 907 /* cyrix could have cpuid enabled via c_identify()*/ 908 if (have_cpuid_p()) { 909 cpu_detect(c); 910 get_cpu_vendor(c); 911 get_cpu_cap(c); 912 setup_force_cpu_cap(X86_FEATURE_CPUID); 913 914 if (this_cpu->c_early_init) 915 this_cpu->c_early_init(c); 916 917 c->cpu_index = 0; 918 filter_cpuid_features(c, false); 919 920 if (this_cpu->c_bsp_init) 921 this_cpu->c_bsp_init(c); 922 } else { 923 identify_cpu_without_cpuid(c); 924 setup_clear_cpu_cap(X86_FEATURE_CPUID); 925 } 926 927 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 928 fpu__init_system(c); 929 930 #ifdef CONFIG_X86_32 931 /* 932 * Regardless of whether PCID is enumerated, the SDM says 933 * that it can't be enabled in 32-bit mode. 934 */ 935 setup_clear_cpu_cap(X86_FEATURE_PCID); 936 #endif 937 } 938 939 void __init early_cpu_init(void) 940 { 941 const struct cpu_dev *const *cdev; 942 int count = 0; 943 944 #ifdef CONFIG_PROCESSOR_SELECT 945 pr_info("KERNEL supported cpus:\n"); 946 #endif 947 948 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 949 const struct cpu_dev *cpudev = *cdev; 950 951 if (count >= X86_VENDOR_NUM) 952 break; 953 cpu_devs[count] = cpudev; 954 count++; 955 956 #ifdef CONFIG_PROCESSOR_SELECT 957 { 958 unsigned int j; 959 960 for (j = 0; j < 2; j++) { 961 if (!cpudev->c_ident[j]) 962 continue; 963 pr_info(" %s %s\n", cpudev->c_vendor, 964 cpudev->c_ident[j]); 965 } 966 } 967 #endif 968 } 969 early_identify_cpu(&boot_cpu_data); 970 } 971 972 /* 973 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 974 * unfortunately, that's not true in practice because of early VIA 975 * chips and (more importantly) broken virtualizers that are not easy 976 * to detect. In the latter case it doesn't even *fail* reliably, so 977 * probing for it doesn't even work. Disable it completely on 32-bit 978 * unless we can find a reliable way to detect all the broken cases. 979 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 980 */ 981 static void detect_nopl(struct cpuinfo_x86 *c) 982 { 983 #ifdef CONFIG_X86_32 984 clear_cpu_cap(c, X86_FEATURE_NOPL); 985 #else 986 set_cpu_cap(c, X86_FEATURE_NOPL); 987 #endif 988 } 989 990 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 991 { 992 #ifdef CONFIG_X86_64 993 /* 994 * Empirically, writing zero to a segment selector on AMD does 995 * not clear the base, whereas writing zero to a segment 996 * selector on Intel does clear the base. Intel's behavior 997 * allows slightly faster context switches in the common case 998 * where GS is unused by the prev and next threads. 999 * 1000 * Since neither vendor documents this anywhere that I can see, 1001 * detect it directly instead of hardcoding the choice by 1002 * vendor. 1003 * 1004 * I've designated AMD's behavior as the "bug" because it's 1005 * counterintuitive and less friendly. 1006 */ 1007 1008 unsigned long old_base, tmp; 1009 rdmsrl(MSR_FS_BASE, old_base); 1010 wrmsrl(MSR_FS_BASE, 1); 1011 loadsegment(fs, 0); 1012 rdmsrl(MSR_FS_BASE, tmp); 1013 if (tmp != 0) 1014 set_cpu_bug(c, X86_BUG_NULL_SEG); 1015 wrmsrl(MSR_FS_BASE, old_base); 1016 #endif 1017 } 1018 1019 static void generic_identify(struct cpuinfo_x86 *c) 1020 { 1021 c->extended_cpuid_level = 0; 1022 1023 if (!have_cpuid_p()) 1024 identify_cpu_without_cpuid(c); 1025 1026 /* cyrix could have cpuid enabled via c_identify()*/ 1027 if (!have_cpuid_p()) 1028 return; 1029 1030 cpu_detect(c); 1031 1032 get_cpu_vendor(c); 1033 1034 get_cpu_cap(c); 1035 1036 if (c->cpuid_level >= 0x00000001) { 1037 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1038 #ifdef CONFIG_X86_32 1039 # ifdef CONFIG_SMP 1040 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1041 # else 1042 c->apicid = c->initial_apicid; 1043 # endif 1044 #endif 1045 c->phys_proc_id = c->initial_apicid; 1046 } 1047 1048 get_model_name(c); /* Default name */ 1049 1050 detect_nopl(c); 1051 1052 detect_null_seg_behavior(c); 1053 1054 /* 1055 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1056 * systems that run Linux at CPL > 0 may or may not have the 1057 * issue, but, even if they have the issue, there's absolutely 1058 * nothing we can do about it because we can't use the real IRET 1059 * instruction. 1060 * 1061 * NB: For the time being, only 32-bit kernels support 1062 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1063 * whether to apply espfix using paravirt hooks. If any 1064 * non-paravirt system ever shows up that does *not* have the 1065 * ESPFIX issue, we can change this. 1066 */ 1067 #ifdef CONFIG_X86_32 1068 # ifdef CONFIG_PARAVIRT 1069 do { 1070 extern void native_iret(void); 1071 if (pv_cpu_ops.iret == native_iret) 1072 set_cpu_bug(c, X86_BUG_ESPFIX); 1073 } while (0); 1074 # else 1075 set_cpu_bug(c, X86_BUG_ESPFIX); 1076 # endif 1077 #endif 1078 } 1079 1080 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1081 { 1082 /* 1083 * The heavy lifting of max_rmid and cache_occ_scale are handled 1084 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1085 * in case CQM bits really aren't there in this CPU. 1086 */ 1087 if (c != &boot_cpu_data) { 1088 boot_cpu_data.x86_cache_max_rmid = 1089 min(boot_cpu_data.x86_cache_max_rmid, 1090 c->x86_cache_max_rmid); 1091 } 1092 } 1093 1094 /* 1095 * Validate that ACPI/mptables have the same information about the 1096 * effective APIC id and update the package map. 1097 */ 1098 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1099 { 1100 #ifdef CONFIG_SMP 1101 unsigned int apicid, cpu = smp_processor_id(); 1102 1103 apicid = apic->cpu_present_to_apicid(cpu); 1104 1105 if (apicid != c->apicid) { 1106 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1107 cpu, apicid, c->initial_apicid); 1108 } 1109 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1110 #else 1111 c->logical_proc_id = 0; 1112 #endif 1113 } 1114 1115 /* 1116 * This does the hard work of actually picking apart the CPU stuff... 1117 */ 1118 static void identify_cpu(struct cpuinfo_x86 *c) 1119 { 1120 int i; 1121 1122 c->loops_per_jiffy = loops_per_jiffy; 1123 c->x86_cache_size = -1; 1124 c->x86_vendor = X86_VENDOR_UNKNOWN; 1125 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 1126 c->x86_vendor_id[0] = '\0'; /* Unset */ 1127 c->x86_model_id[0] = '\0'; /* Unset */ 1128 c->x86_max_cores = 1; 1129 c->x86_coreid_bits = 0; 1130 c->cu_id = 0xff; 1131 #ifdef CONFIG_X86_64 1132 c->x86_clflush_size = 64; 1133 c->x86_phys_bits = 36; 1134 c->x86_virt_bits = 48; 1135 #else 1136 c->cpuid_level = -1; /* CPUID not detected */ 1137 c->x86_clflush_size = 32; 1138 c->x86_phys_bits = 32; 1139 c->x86_virt_bits = 32; 1140 #endif 1141 c->x86_cache_alignment = c->x86_clflush_size; 1142 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1143 1144 generic_identify(c); 1145 1146 if (this_cpu->c_identify) 1147 this_cpu->c_identify(c); 1148 1149 /* Clear/Set all flags overridden by options, after probe */ 1150 apply_forced_caps(c); 1151 1152 #ifdef CONFIG_X86_64 1153 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1154 #endif 1155 1156 /* 1157 * Vendor-specific initialization. In this section we 1158 * canonicalize the feature flags, meaning if there are 1159 * features a certain CPU supports which CPUID doesn't 1160 * tell us, CPUID claiming incorrect flags, or other bugs, 1161 * we handle them here. 1162 * 1163 * At the end of this section, c->x86_capability better 1164 * indicate the features this CPU genuinely supports! 1165 */ 1166 if (this_cpu->c_init) 1167 this_cpu->c_init(c); 1168 1169 /* Disable the PN if appropriate */ 1170 squash_the_stupid_serial_number(c); 1171 1172 /* Set up SMEP/SMAP/UMIP */ 1173 setup_smep(c); 1174 setup_smap(c); 1175 setup_umip(c); 1176 1177 /* 1178 * The vendor-specific functions might have changed features. 1179 * Now we do "generic changes." 1180 */ 1181 1182 /* Filter out anything that depends on CPUID levels we don't have */ 1183 filter_cpuid_features(c, true); 1184 1185 /* If the model name is still unset, do table lookup. */ 1186 if (!c->x86_model_id[0]) { 1187 const char *p; 1188 p = table_lookup_model(c); 1189 if (p) 1190 strcpy(c->x86_model_id, p); 1191 else 1192 /* Last resort... */ 1193 sprintf(c->x86_model_id, "%02x/%02x", 1194 c->x86, c->x86_model); 1195 } 1196 1197 #ifdef CONFIG_X86_64 1198 detect_ht(c); 1199 #endif 1200 1201 x86_init_rdrand(c); 1202 x86_init_cache_qos(c); 1203 setup_pku(c); 1204 1205 /* 1206 * Clear/Set all flags overridden by options, need do it 1207 * before following smp all cpus cap AND. 1208 */ 1209 apply_forced_caps(c); 1210 1211 /* 1212 * On SMP, boot_cpu_data holds the common feature set between 1213 * all CPUs; so make sure that we indicate which features are 1214 * common between the CPUs. The first time this routine gets 1215 * executed, c == &boot_cpu_data. 1216 */ 1217 if (c != &boot_cpu_data) { 1218 /* AND the already accumulated flags with these */ 1219 for (i = 0; i < NCAPINTS; i++) 1220 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1221 1222 /* OR, i.e. replicate the bug flags */ 1223 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1224 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1225 } 1226 1227 /* Init Machine Check Exception if available. */ 1228 mcheck_cpu_init(c); 1229 1230 select_idle_routine(c); 1231 1232 #ifdef CONFIG_NUMA 1233 numa_add_cpu(smp_processor_id()); 1234 #endif 1235 } 1236 1237 /* 1238 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1239 * on 32-bit kernels: 1240 */ 1241 #ifdef CONFIG_X86_32 1242 void enable_sep_cpu(void) 1243 { 1244 struct tss_struct *tss; 1245 int cpu; 1246 1247 if (!boot_cpu_has(X86_FEATURE_SEP)) 1248 return; 1249 1250 cpu = get_cpu(); 1251 tss = &per_cpu(cpu_tss, cpu); 1252 1253 /* 1254 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1255 * see the big comment in struct x86_hw_tss's definition. 1256 */ 1257 1258 tss->x86_tss.ss1 = __KERNEL_CS; 1259 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1260 1261 wrmsr(MSR_IA32_SYSENTER_ESP, 1262 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1263 0); 1264 1265 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1266 1267 put_cpu(); 1268 } 1269 #endif 1270 1271 void __init identify_boot_cpu(void) 1272 { 1273 identify_cpu(&boot_cpu_data); 1274 #ifdef CONFIG_X86_32 1275 sysenter_setup(); 1276 enable_sep_cpu(); 1277 #endif 1278 cpu_detect_tlb(&boot_cpu_data); 1279 } 1280 1281 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1282 { 1283 BUG_ON(c == &boot_cpu_data); 1284 identify_cpu(c); 1285 #ifdef CONFIG_X86_32 1286 enable_sep_cpu(); 1287 #endif 1288 mtrr_ap_init(); 1289 validate_apic_and_package_id(c); 1290 } 1291 1292 static __init int setup_noclflush(char *arg) 1293 { 1294 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1295 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1296 return 1; 1297 } 1298 __setup("noclflush", setup_noclflush); 1299 1300 void print_cpu_info(struct cpuinfo_x86 *c) 1301 { 1302 const char *vendor = NULL; 1303 1304 if (c->x86_vendor < X86_VENDOR_NUM) { 1305 vendor = this_cpu->c_vendor; 1306 } else { 1307 if (c->cpuid_level >= 0) 1308 vendor = c->x86_vendor_id; 1309 } 1310 1311 if (vendor && !strstr(c->x86_model_id, vendor)) 1312 pr_cont("%s ", vendor); 1313 1314 if (c->x86_model_id[0]) 1315 pr_cont("%s", c->x86_model_id); 1316 else 1317 pr_cont("%d86", c->x86); 1318 1319 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1320 1321 if (c->x86_mask || c->cpuid_level >= 0) 1322 pr_cont(", stepping: 0x%x)\n", c->x86_mask); 1323 else 1324 pr_cont(")\n"); 1325 } 1326 1327 /* 1328 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1329 * But we need to keep a dummy __setup around otherwise it would 1330 * show up as an environment variable for init. 1331 */ 1332 static __init int setup_clearcpuid(char *arg) 1333 { 1334 return 1; 1335 } 1336 __setup("clearcpuid=", setup_clearcpuid); 1337 1338 #ifdef CONFIG_X86_64 1339 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1340 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1341 1342 /* 1343 * The following percpu variables are hot. Align current_task to 1344 * cacheline size such that they fall in the same cacheline. 1345 */ 1346 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1347 &init_task; 1348 EXPORT_PER_CPU_SYMBOL(current_task); 1349 1350 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1351 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1352 1353 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1354 1355 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1356 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1357 1358 /* 1359 * Special IST stacks which the CPU switches to when it calls 1360 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1361 * limit), all of them are 4K, except the debug stack which 1362 * is 8K. 1363 */ 1364 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1365 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1366 [DEBUG_STACK - 1] = DEBUG_STKSZ 1367 }; 1368 1369 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1370 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1371 1372 /* May not be marked __init: used by software suspend */ 1373 void syscall_init(void) 1374 { 1375 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1376 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1377 1378 #ifdef CONFIG_IA32_EMULATION 1379 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1380 /* 1381 * This only works on Intel CPUs. 1382 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1383 * This does not cause SYSENTER to jump to the wrong location, because 1384 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1385 */ 1386 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1387 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1388 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1389 #else 1390 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1391 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1392 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1393 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1394 #endif 1395 1396 /* Flags to clear on syscall */ 1397 wrmsrl(MSR_SYSCALL_MASK, 1398 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1399 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1400 } 1401 1402 /* 1403 * Copies of the original ist values from the tss are only accessed during 1404 * debugging, no special alignment required. 1405 */ 1406 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1407 1408 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1409 DEFINE_PER_CPU(int, debug_stack_usage); 1410 1411 int is_debug_stack(unsigned long addr) 1412 { 1413 return __this_cpu_read(debug_stack_usage) || 1414 (addr <= __this_cpu_read(debug_stack_addr) && 1415 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1416 } 1417 NOKPROBE_SYMBOL(is_debug_stack); 1418 1419 DEFINE_PER_CPU(u32, debug_idt_ctr); 1420 1421 void debug_stack_set_zero(void) 1422 { 1423 this_cpu_inc(debug_idt_ctr); 1424 load_current_idt(); 1425 } 1426 NOKPROBE_SYMBOL(debug_stack_set_zero); 1427 1428 void debug_stack_reset(void) 1429 { 1430 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1431 return; 1432 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1433 load_current_idt(); 1434 } 1435 NOKPROBE_SYMBOL(debug_stack_reset); 1436 1437 #else /* CONFIG_X86_64 */ 1438 1439 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1440 EXPORT_PER_CPU_SYMBOL(current_task); 1441 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1442 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1443 1444 /* 1445 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1446 * the top of the kernel stack. Use an extra percpu variable to track the 1447 * top of the kernel stack directly. 1448 */ 1449 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1450 (unsigned long)&init_thread_union + THREAD_SIZE; 1451 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1452 1453 #ifdef CONFIG_CC_STACKPROTECTOR 1454 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1455 #endif 1456 1457 #endif /* CONFIG_X86_64 */ 1458 1459 /* 1460 * Clear all 6 debug registers: 1461 */ 1462 static void clear_all_debug_regs(void) 1463 { 1464 int i; 1465 1466 for (i = 0; i < 8; i++) { 1467 /* Ignore db4, db5 */ 1468 if ((i == 4) || (i == 5)) 1469 continue; 1470 1471 set_debugreg(0, i); 1472 } 1473 } 1474 1475 #ifdef CONFIG_KGDB 1476 /* 1477 * Restore debug regs if using kgdbwait and you have a kernel debugger 1478 * connection established. 1479 */ 1480 static void dbg_restore_debug_regs(void) 1481 { 1482 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1483 arch_kgdb_ops.correct_hw_break(); 1484 } 1485 #else /* ! CONFIG_KGDB */ 1486 #define dbg_restore_debug_regs() 1487 #endif /* ! CONFIG_KGDB */ 1488 1489 static void wait_for_master_cpu(int cpu) 1490 { 1491 #ifdef CONFIG_SMP 1492 /* 1493 * wait for ACK from master CPU before continuing 1494 * with AP initialization 1495 */ 1496 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1497 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1498 cpu_relax(); 1499 #endif 1500 } 1501 1502 /* 1503 * cpu_init() initializes state that is per-CPU. Some data is already 1504 * initialized (naturally) in the bootstrap process, such as the GDT 1505 * and IDT. We reload them nevertheless, this function acts as a 1506 * 'CPU state barrier', nothing should get across. 1507 * A lot of state is already set up in PDA init for 64 bit 1508 */ 1509 #ifdef CONFIG_X86_64 1510 1511 void cpu_init(void) 1512 { 1513 struct orig_ist *oist; 1514 struct task_struct *me; 1515 struct tss_struct *t; 1516 unsigned long v; 1517 int cpu = raw_smp_processor_id(); 1518 int i; 1519 1520 wait_for_master_cpu(cpu); 1521 1522 /* 1523 * Initialize the CR4 shadow before doing anything that could 1524 * try to read it. 1525 */ 1526 cr4_init_shadow(); 1527 1528 if (cpu) 1529 load_ucode_ap(); 1530 1531 t = &per_cpu(cpu_tss, cpu); 1532 oist = &per_cpu(orig_ist, cpu); 1533 1534 #ifdef CONFIG_NUMA 1535 if (this_cpu_read(numa_node) == 0 && 1536 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1537 set_numa_node(early_cpu_to_node(cpu)); 1538 #endif 1539 1540 me = current; 1541 1542 pr_debug("Initializing CPU#%d\n", cpu); 1543 1544 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1545 1546 /* 1547 * Initialize the per-CPU GDT with the boot GDT, 1548 * and set up the GDT descriptor: 1549 */ 1550 1551 switch_to_new_gdt(cpu); 1552 loadsegment(fs, 0); 1553 1554 load_current_idt(); 1555 1556 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1557 syscall_init(); 1558 1559 wrmsrl(MSR_FS_BASE, 0); 1560 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1561 barrier(); 1562 1563 x86_configure_nx(); 1564 x2apic_setup(); 1565 1566 /* 1567 * set up and load the per-CPU TSS 1568 */ 1569 if (!oist->ist[0]) { 1570 char *estacks = per_cpu(exception_stacks, cpu); 1571 1572 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1573 estacks += exception_stack_sizes[v]; 1574 oist->ist[v] = t->x86_tss.ist[v] = 1575 (unsigned long)estacks; 1576 if (v == DEBUG_STACK-1) 1577 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1578 } 1579 } 1580 1581 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1582 1583 /* 1584 * <= is required because the CPU will access up to 1585 * 8 bits beyond the end of the IO permission bitmap. 1586 */ 1587 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1588 t->io_bitmap[i] = ~0UL; 1589 1590 mmgrab(&init_mm); 1591 me->active_mm = &init_mm; 1592 BUG_ON(me->mm); 1593 initialize_tlbstate_and_flush(); 1594 enter_lazy_tlb(&init_mm, me); 1595 1596 /* 1597 * Initialize the TSS. Don't bother initializing sp0, as the initial 1598 * task never enters user mode. 1599 */ 1600 set_tss_desc(cpu, t); 1601 load_TR_desc(); 1602 1603 load_mm_ldt(&init_mm); 1604 1605 clear_all_debug_regs(); 1606 dbg_restore_debug_regs(); 1607 1608 fpu__init_cpu(); 1609 1610 if (is_uv_system()) 1611 uv_cpu_init(); 1612 1613 setup_fixmap_gdt(cpu); 1614 load_fixmap_gdt(cpu); 1615 } 1616 1617 #else 1618 1619 void cpu_init(void) 1620 { 1621 int cpu = smp_processor_id(); 1622 struct task_struct *curr = current; 1623 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1624 1625 wait_for_master_cpu(cpu); 1626 1627 /* 1628 * Initialize the CR4 shadow before doing anything that could 1629 * try to read it. 1630 */ 1631 cr4_init_shadow(); 1632 1633 show_ucode_info_early(); 1634 1635 pr_info("Initializing CPU#%d\n", cpu); 1636 1637 if (cpu_feature_enabled(X86_FEATURE_VME) || 1638 boot_cpu_has(X86_FEATURE_TSC) || 1639 boot_cpu_has(X86_FEATURE_DE)) 1640 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1641 1642 load_current_idt(); 1643 switch_to_new_gdt(cpu); 1644 1645 /* 1646 * Set up and load the per-CPU TSS and LDT 1647 */ 1648 mmgrab(&init_mm); 1649 curr->active_mm = &init_mm; 1650 BUG_ON(curr->mm); 1651 initialize_tlbstate_and_flush(); 1652 enter_lazy_tlb(&init_mm, curr); 1653 1654 /* 1655 * Initialize the TSS. Don't bother initializing sp0, as the initial 1656 * task never enters user mode. 1657 */ 1658 set_tss_desc(cpu, t); 1659 load_TR_desc(); 1660 1661 load_mm_ldt(&init_mm); 1662 1663 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1664 1665 #ifdef CONFIG_DOUBLEFAULT 1666 /* Set up doublefault TSS pointer in the GDT */ 1667 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1668 #endif 1669 1670 clear_all_debug_regs(); 1671 dbg_restore_debug_regs(); 1672 1673 fpu__init_cpu(); 1674 1675 setup_fixmap_gdt(cpu); 1676 load_fixmap_gdt(cpu); 1677 } 1678 #endif 1679 1680 static void bsp_resume(void) 1681 { 1682 if (this_cpu->c_bsp_resume) 1683 this_cpu->c_bsp_resume(&boot_cpu_data); 1684 } 1685 1686 static struct syscore_ops cpu_syscore_ops = { 1687 .resume = bsp_resume, 1688 }; 1689 1690 static int __init init_cpu_syscore(void) 1691 { 1692 register_syscore_ops(&cpu_syscore_ops); 1693 return 0; 1694 } 1695 core_initcall(init_cpu_syscore); 1696