1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/mem_encrypt.h> 22 #include <linux/smp.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/pgtable.h> 27 #include <linux/stackprotector.h> 28 #include <linux/utsname.h> 29 #include <linux/efi.h> 30 31 #include <asm/alternative.h> 32 #include <asm/cmdline.h> 33 #include <asm/cpuid/api.h> 34 #include <asm/perf_event.h> 35 #include <asm/mmu_context.h> 36 #include <asm/doublefault.h> 37 #include <asm/archrandom.h> 38 #include <asm/hypervisor.h> 39 #include <asm/processor.h> 40 #include <asm/tlbflush.h> 41 #include <asm/debugreg.h> 42 #include <asm/sections.h> 43 #include <asm/vsyscall.h> 44 #include <linux/topology.h> 45 #include <linux/cpumask.h> 46 #include <linux/atomic.h> 47 #include <asm/proto.h> 48 #include <asm/setup.h> 49 #include <asm/apic.h> 50 #include <asm/desc.h> 51 #include <asm/fpu/api.h> 52 #include <asm/mtrr.h> 53 #include <asm/hwcap2.h> 54 #include <linux/numa.h> 55 #include <asm/numa.h> 56 #include <asm/asm.h> 57 #include <asm/bugs.h> 58 #include <asm/cpu.h> 59 #include <asm/mce.h> 60 #include <asm/msr.h> 61 #include <asm/cacheinfo.h> 62 #include <asm/memtype.h> 63 #include <asm/microcode.h> 64 #include <asm/intel-family.h> 65 #include <asm/cpu_device_id.h> 66 #include <asm/fred.h> 67 #include <asm/uv/uv.h> 68 #include <asm/ia32.h> 69 #include <asm/set_memory.h> 70 #include <asm/traps.h> 71 #include <asm/sev.h> 72 #include <asm/tdx.h> 73 #include <asm/posted_intr.h> 74 #include <asm/runtime-const.h> 75 76 #include "cpu.h" 77 78 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 79 EXPORT_PER_CPU_SYMBOL(cpu_info); 80 81 /* Used for modules: built-in code uses runtime constants */ 82 unsigned long USER_PTR_MAX; 83 EXPORT_SYMBOL(USER_PTR_MAX); 84 85 u32 elf_hwcap2 __read_mostly; 86 87 /* Number of siblings per CPU package */ 88 unsigned int __max_threads_per_core __ro_after_init = 1; 89 EXPORT_SYMBOL(__max_threads_per_core); 90 91 unsigned int __max_dies_per_package __ro_after_init = 1; 92 EXPORT_SYMBOL(__max_dies_per_package); 93 94 unsigned int __max_logical_packages __ro_after_init = 1; 95 EXPORT_SYMBOL(__max_logical_packages); 96 97 unsigned int __num_cores_per_package __ro_after_init = 1; 98 EXPORT_SYMBOL(__num_cores_per_package); 99 100 unsigned int __num_threads_per_package __ro_after_init = 1; 101 EXPORT_SYMBOL(__num_threads_per_package); 102 103 static struct ppin_info { 104 int feature; 105 int msr_ppin_ctl; 106 int msr_ppin; 107 } ppin_info[] = { 108 [X86_VENDOR_INTEL] = { 109 .feature = X86_FEATURE_INTEL_PPIN, 110 .msr_ppin_ctl = MSR_PPIN_CTL, 111 .msr_ppin = MSR_PPIN 112 }, 113 [X86_VENDOR_AMD] = { 114 .feature = X86_FEATURE_AMD_PPIN, 115 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 116 .msr_ppin = MSR_AMD_PPIN 117 }, 118 }; 119 120 static const struct x86_cpu_id ppin_cpuids[] = { 121 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 122 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 123 124 /* Legacy models without CPUID enumeration */ 125 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 126 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 127 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 128 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 129 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 130 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 131 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 132 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 133 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 134 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 135 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 136 137 {} 138 }; 139 140 static void ppin_init(struct cpuinfo_x86 *c) 141 { 142 const struct x86_cpu_id *id; 143 unsigned long long val; 144 struct ppin_info *info; 145 146 id = x86_match_cpu(ppin_cpuids); 147 if (!id) 148 return; 149 150 /* 151 * Testing the presence of the MSR is not enough. Need to check 152 * that the PPIN_CTL allows reading of the PPIN. 153 */ 154 info = (struct ppin_info *)id->driver_data; 155 156 if (rdmsrq_safe(info->msr_ppin_ctl, &val)) 157 goto clear_ppin; 158 159 if ((val & 3UL) == 1UL) { 160 /* PPIN locked in disabled mode */ 161 goto clear_ppin; 162 } 163 164 /* If PPIN is disabled, try to enable */ 165 if (!(val & 2UL)) { 166 wrmsrq_safe(info->msr_ppin_ctl, val | 2UL); 167 rdmsrq_safe(info->msr_ppin_ctl, &val); 168 } 169 170 /* Is the enable bit set? */ 171 if (val & 2UL) { 172 c->ppin = native_rdmsrq(info->msr_ppin); 173 set_cpu_cap(c, info->feature); 174 return; 175 } 176 177 clear_ppin: 178 setup_clear_cpu_cap(info->feature); 179 } 180 181 static void default_init(struct cpuinfo_x86 *c) 182 { 183 #ifdef CONFIG_X86_64 184 cpu_detect_cache_sizes(c); 185 #else 186 /* Not much we can do here... */ 187 /* Check if at least it has cpuid */ 188 if (c->cpuid_level == -1) { 189 /* No cpuid. It must be an ancient CPU */ 190 if (c->x86 == 4) 191 strcpy(c->x86_model_id, "486"); 192 else if (c->x86 == 3) 193 strcpy(c->x86_model_id, "386"); 194 } 195 #endif 196 } 197 198 static const struct cpu_dev default_cpu = { 199 .c_init = default_init, 200 .c_vendor = "Unknown", 201 .c_x86_vendor = X86_VENDOR_UNKNOWN, 202 }; 203 204 static const struct cpu_dev *this_cpu = &default_cpu; 205 206 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 207 #ifdef CONFIG_X86_64 208 /* 209 * We need valid kernel segments for data and code in long mode too 210 * IRET will check the segment types kkeil 2000/10/28 211 * Also sysret mandates a special GDT layout 212 * 213 * TLS descriptors are currently at a different place compared to i386. 214 * Hopefully nobody expects them at a fixed place (Wine?) 215 */ 216 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 217 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 218 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff), 219 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 220 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff), 221 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff), 222 #else 223 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 224 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 225 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 226 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff), 227 /* 228 * Segments used for calling PnP BIOS have byte granularity. 229 * They code segments and data segments have fixed 64k limits, 230 * the transfer segment sizes are set at run time. 231 */ 232 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 233 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 234 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff), 235 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 236 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 237 /* 238 * The APM segments have byte granularity and their bases 239 * are set at run time. All have 64k limits. 240 */ 241 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 242 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 243 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff), 244 245 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 246 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 247 #endif 248 } }; 249 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 250 SYM_PIC_ALIAS(gdt_page); 251 252 #ifdef CONFIG_X86_64 253 static int __init x86_nopcid_setup(char *s) 254 { 255 /* nopcid doesn't accept parameters */ 256 if (s) 257 return -EINVAL; 258 259 /* do not emit a message if the feature is not present */ 260 if (!boot_cpu_has(X86_FEATURE_PCID)) 261 return 0; 262 263 setup_clear_cpu_cap(X86_FEATURE_PCID); 264 pr_info("nopcid: PCID feature disabled\n"); 265 return 0; 266 } 267 early_param("nopcid", x86_nopcid_setup); 268 #endif 269 270 static int __init x86_noinvpcid_setup(char *s) 271 { 272 /* noinvpcid doesn't accept parameters */ 273 if (s) 274 return -EINVAL; 275 276 /* do not emit a message if the feature is not present */ 277 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 278 return 0; 279 280 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 281 pr_info("noinvpcid: INVPCID feature disabled\n"); 282 return 0; 283 } 284 early_param("noinvpcid", x86_noinvpcid_setup); 285 286 /* Standard macro to see if a specific flag is changeable */ 287 static inline bool flag_is_changeable_p(unsigned long flag) 288 { 289 unsigned long f1, f2; 290 291 if (!IS_ENABLED(CONFIG_X86_32)) 292 return true; 293 294 /* 295 * Cyrix and IDT cpus allow disabling of CPUID 296 * so the code below may return different results 297 * when it is executed before and after enabling 298 * the CPUID. Add "volatile" to not allow gcc to 299 * optimize the subsequent calls to this function. 300 */ 301 asm volatile ("pushfl \n\t" 302 "pushfl \n\t" 303 "popl %0 \n\t" 304 "movl %0, %1 \n\t" 305 "xorl %2, %0 \n\t" 306 "pushl %0 \n\t" 307 "popfl \n\t" 308 "pushfl \n\t" 309 "popl %0 \n\t" 310 "popfl \n\t" 311 312 : "=&r" (f1), "=&r" (f2) 313 : "ir" (flag)); 314 315 return (f1 ^ f2) & flag; 316 } 317 318 #ifdef CONFIG_X86_32 319 static int cachesize_override = -1; 320 static int disable_x86_serial_nr = 1; 321 322 static int __init cachesize_setup(char *str) 323 { 324 get_option(&str, &cachesize_override); 325 return 1; 326 } 327 __setup("cachesize=", cachesize_setup); 328 329 /* Probe for the CPUID instruction */ 330 bool cpuid_feature(void) 331 { 332 return flag_is_changeable_p(X86_EFLAGS_ID); 333 } 334 335 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 336 { 337 unsigned long lo, hi; 338 339 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 340 return; 341 342 /* Disable processor serial number: */ 343 344 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 345 lo |= 0x200000; 346 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 347 348 pr_notice("CPU serial number disabled.\n"); 349 clear_cpu_cap(c, X86_FEATURE_PN); 350 351 /* Disabling the serial number may affect the cpuid level */ 352 c->cpuid_level = cpuid_eax(0); 353 } 354 355 static int __init x86_serial_nr_setup(char *s) 356 { 357 disable_x86_serial_nr = 0; 358 return 1; 359 } 360 __setup("serialnumber", x86_serial_nr_setup); 361 #else 362 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 363 { 364 } 365 #endif 366 367 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 368 { 369 if (cpu_has(c, X86_FEATURE_SMEP)) 370 cr4_set_bits(X86_CR4_SMEP); 371 } 372 373 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 374 { 375 unsigned long eflags = native_save_fl(); 376 377 /* This should have been cleared long ago */ 378 BUG_ON(eflags & X86_EFLAGS_AC); 379 380 if (cpu_has(c, X86_FEATURE_SMAP)) 381 cr4_set_bits(X86_CR4_SMAP); 382 } 383 384 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 385 { 386 /* Check the boot processor, plus build option for UMIP. */ 387 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 388 goto out; 389 390 /* Check the current processor's cpuid bits. */ 391 if (!cpu_has(c, X86_FEATURE_UMIP)) 392 goto out; 393 394 cr4_set_bits(X86_CR4_UMIP); 395 396 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 397 398 return; 399 400 out: 401 /* 402 * Make sure UMIP is disabled in case it was enabled in a 403 * previous boot (e.g., via kexec). 404 */ 405 cr4_clear_bits(X86_CR4_UMIP); 406 } 407 408 /* These bits should not change their value after CPU init is finished. */ 409 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 410 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; 411 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 412 static unsigned long cr4_pinned_bits __ro_after_init; 413 414 void native_write_cr0(unsigned long val) 415 { 416 unsigned long bits_missing = 0; 417 418 set_register: 419 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 420 421 if (static_branch_likely(&cr_pinning)) { 422 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 423 bits_missing = X86_CR0_WP; 424 val |= bits_missing; 425 goto set_register; 426 } 427 /* Warn after we've set the missing bits. */ 428 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 429 } 430 } 431 EXPORT_SYMBOL(native_write_cr0); 432 433 void __no_profile native_write_cr4(unsigned long val) 434 { 435 unsigned long bits_changed = 0; 436 437 set_register: 438 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 439 440 if (static_branch_likely(&cr_pinning)) { 441 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 442 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 443 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 444 goto set_register; 445 } 446 /* Warn after we've corrected the changed bits. */ 447 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 448 bits_changed); 449 } 450 } 451 #if IS_MODULE(CONFIG_LKDTM) 452 EXPORT_SYMBOL_GPL(native_write_cr4); 453 #endif 454 455 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 456 { 457 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 458 459 lockdep_assert_irqs_disabled(); 460 461 newval = (cr4 & ~clear) | set; 462 if (newval != cr4) { 463 this_cpu_write(cpu_tlbstate.cr4, newval); 464 __write_cr4(newval); 465 } 466 } 467 EXPORT_SYMBOL(cr4_update_irqsoff); 468 469 /* Read the CR4 shadow. */ 470 unsigned long cr4_read_shadow(void) 471 { 472 return this_cpu_read(cpu_tlbstate.cr4); 473 } 474 EXPORT_SYMBOL_GPL(cr4_read_shadow); 475 476 void cr4_init(void) 477 { 478 unsigned long cr4 = __read_cr4(); 479 480 if (boot_cpu_has(X86_FEATURE_PCID)) 481 cr4 |= X86_CR4_PCIDE; 482 if (static_branch_likely(&cr_pinning)) 483 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 484 485 __write_cr4(cr4); 486 487 /* Initialize cr4 shadow for this CPU. */ 488 this_cpu_write(cpu_tlbstate.cr4, cr4); 489 } 490 491 /* 492 * Once CPU feature detection is finished (and boot params have been 493 * parsed), record any of the sensitive CR bits that are set, and 494 * enable CR pinning. 495 */ 496 static void __init setup_cr_pinning(void) 497 { 498 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 499 static_key_enable(&cr_pinning.key); 500 } 501 502 static __init int x86_nofsgsbase_setup(char *arg) 503 { 504 /* Require an exact match without trailing characters. */ 505 if (strlen(arg)) 506 return 0; 507 508 /* Do not emit a message if the feature is not present. */ 509 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 510 return 1; 511 512 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 513 pr_info("FSGSBASE disabled via kernel command line\n"); 514 return 1; 515 } 516 __setup("nofsgsbase", x86_nofsgsbase_setup); 517 518 /* 519 * Protection Keys are not available in 32-bit mode. 520 */ 521 static bool pku_disabled; 522 523 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 524 { 525 if (c == &boot_cpu_data) { 526 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 527 return; 528 /* 529 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 530 * bit to be set. Enforce it. 531 */ 532 setup_force_cpu_cap(X86_FEATURE_OSPKE); 533 534 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 535 return; 536 } 537 538 cr4_set_bits(X86_CR4_PKE); 539 /* Load the default PKRU value */ 540 pkru_write_default(); 541 } 542 543 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 544 static __init int setup_disable_pku(char *arg) 545 { 546 /* 547 * Do not clear the X86_FEATURE_PKU bit. All of the 548 * runtime checks are against OSPKE so clearing the 549 * bit does nothing. 550 * 551 * This way, we will see "pku" in cpuinfo, but not 552 * "ospke", which is exactly what we want. It shows 553 * that the CPU has PKU, but the OS has not enabled it. 554 * This happens to be exactly how a system would look 555 * if we disabled the config option. 556 */ 557 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 558 pku_disabled = true; 559 return 1; 560 } 561 __setup("nopku", setup_disable_pku); 562 #endif 563 564 #ifdef CONFIG_X86_KERNEL_IBT 565 566 __noendbr u64 ibt_save(bool disable) 567 { 568 u64 msr = 0; 569 570 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 571 rdmsrq(MSR_IA32_S_CET, msr); 572 if (disable) 573 wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 574 } 575 576 return msr; 577 } 578 579 __noendbr void ibt_restore(u64 save) 580 { 581 u64 msr; 582 583 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 584 rdmsrq(MSR_IA32_S_CET, msr); 585 msr &= ~CET_ENDBR_EN; 586 msr |= (save & CET_ENDBR_EN); 587 wrmsrq(MSR_IA32_S_CET, msr); 588 } 589 } 590 591 #endif 592 593 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 594 { 595 bool user_shstk, kernel_ibt; 596 597 if (!IS_ENABLED(CONFIG_X86_CET)) 598 return; 599 600 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 601 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 602 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 603 604 if (!kernel_ibt && !user_shstk) 605 return; 606 607 if (user_shstk) 608 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 609 610 if (kernel_ibt) 611 wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN); 612 else 613 wrmsrq(MSR_IA32_S_CET, 0); 614 615 cr4_set_bits(X86_CR4_CET); 616 617 if (kernel_ibt && ibt_selftest()) { 618 pr_err("IBT selftest: Failed!\n"); 619 wrmsrq(MSR_IA32_S_CET, 0); 620 setup_clear_cpu_cap(X86_FEATURE_IBT); 621 } 622 } 623 624 __noendbr void cet_disable(void) 625 { 626 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 627 cpu_feature_enabled(X86_FEATURE_SHSTK))) 628 return; 629 630 wrmsrq(MSR_IA32_S_CET, 0); 631 wrmsrq(MSR_IA32_U_CET, 0); 632 } 633 634 /* 635 * Some CPU features depend on higher CPUID levels, which may not always 636 * be available due to CPUID level capping or broken virtualization 637 * software. Add those features to this table to auto-disable them. 638 */ 639 struct cpuid_dependent_feature { 640 u32 feature; 641 u32 level; 642 }; 643 644 static const struct cpuid_dependent_feature 645 cpuid_dependent_features[] = { 646 { X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT }, 647 { X86_FEATURE_DCA, CPUID_LEAF_DCA }, 648 { X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE }, 649 { 0, 0 } 650 }; 651 652 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 653 { 654 const struct cpuid_dependent_feature *df; 655 656 for (df = cpuid_dependent_features; df->feature; df++) { 657 658 if (!cpu_has(c, df->feature)) 659 continue; 660 /* 661 * Note: cpuid_level is set to -1 if unavailable, but 662 * extended_extended_level is set to 0 if unavailable 663 * and the legitimate extended levels are all negative 664 * when signed; hence the weird messing around with 665 * signs here... 666 */ 667 if (!((s32)df->level < 0 ? 668 (u32)df->level > (u32)c->extended_cpuid_level : 669 (s32)df->level > (s32)c->cpuid_level)) 670 continue; 671 672 clear_cpu_cap(c, df->feature); 673 if (!warn) 674 continue; 675 676 pr_warn("CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 677 x86_cap_flags[df->feature], df->level); 678 } 679 } 680 681 /* 682 * Naming convention should be: <Name> [(<Codename>)] 683 * This table only is used unless init_<vendor>() below doesn't set it; 684 * in particular, if CPUID levels 0x80000002..4 are supported, this 685 * isn't used 686 */ 687 688 /* Look up CPU names by table lookup. */ 689 static const char *table_lookup_model(struct cpuinfo_x86 *c) 690 { 691 #ifdef CONFIG_X86_32 692 const struct legacy_cpu_model_info *info; 693 694 if (c->x86_model >= 16) 695 return NULL; /* Range check */ 696 697 if (!this_cpu) 698 return NULL; 699 700 info = this_cpu->legacy_models; 701 702 while (info->family) { 703 if (info->family == c->x86) 704 return info->model_names[c->x86_model]; 705 info++; 706 } 707 #endif 708 return NULL; /* Not found */ 709 } 710 711 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 712 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 713 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 714 715 #ifdef CONFIG_X86_32 716 /* The 32-bit entry code needs to find cpu_entry_area. */ 717 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 718 #endif 719 720 /* Load the original GDT from the per-cpu structure */ 721 void load_direct_gdt(int cpu) 722 { 723 struct desc_ptr gdt_descr; 724 725 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 726 gdt_descr.size = GDT_SIZE - 1; 727 load_gdt(&gdt_descr); 728 } 729 EXPORT_SYMBOL_GPL(load_direct_gdt); 730 731 /* Load a fixmap remapping of the per-cpu GDT */ 732 void load_fixmap_gdt(int cpu) 733 { 734 struct desc_ptr gdt_descr; 735 736 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 737 gdt_descr.size = GDT_SIZE - 1; 738 load_gdt(&gdt_descr); 739 } 740 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 741 742 /** 743 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 744 * @cpu: The CPU number for which this is invoked 745 * 746 * Invoked during early boot to switch from early GDT and early per CPU to 747 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 748 * switch is implicit by loading the direct GDT. On 64bit this requires 749 * to update GSBASE. 750 */ 751 void __init switch_gdt_and_percpu_base(int cpu) 752 { 753 load_direct_gdt(cpu); 754 755 #ifdef CONFIG_X86_64 756 /* 757 * No need to load %gs. It is already correct. 758 * 759 * Writing %gs on 64bit would zero GSBASE which would make any per 760 * CPU operation up to the point of the wrmsrq() fault. 761 * 762 * Set GSBASE to the new offset. Until the wrmsrq() happens the 763 * early mapping is still valid. That means the GSBASE update will 764 * lose any prior per CPU data which was not copied over in 765 * setup_per_cpu_areas(). 766 * 767 * This works even with stackprotector enabled because the 768 * per CPU stack canary is 0 in both per CPU areas. 769 */ 770 wrmsrq(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 771 #else 772 /* 773 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 774 * it is required to load FS again so that the 'hidden' part is 775 * updated from the new GDT. Up to this point the early per CPU 776 * translation is active. Any content of the early per CPU data 777 * which was not copied over in setup_per_cpu_areas() is lost. 778 */ 779 loadsegment(fs, __KERNEL_PERCPU); 780 #endif 781 } 782 783 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 784 785 static void get_model_name(struct cpuinfo_x86 *c) 786 { 787 unsigned int *v; 788 char *p, *q, *s; 789 790 if (c->extended_cpuid_level < 0x80000004) 791 return; 792 793 v = (unsigned int *)c->x86_model_id; 794 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 795 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 796 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 797 c->x86_model_id[48] = 0; 798 799 /* Trim whitespace */ 800 p = q = s = &c->x86_model_id[0]; 801 802 while (*p == ' ') 803 p++; 804 805 while (*p) { 806 /* Note the last non-whitespace index */ 807 if (!isspace(*p)) 808 s = q; 809 810 *q++ = *p++; 811 } 812 813 *(s + 1) = '\0'; 814 } 815 816 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 817 { 818 unsigned int n, dummy, ebx, ecx, edx, l2size; 819 820 n = c->extended_cpuid_level; 821 822 if (n >= 0x80000005) { 823 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 824 c->x86_cache_size = (ecx>>24) + (edx>>24); 825 #ifdef CONFIG_X86_64 826 /* On K8 L1 TLB is inclusive, so don't count it */ 827 c->x86_tlbsize = 0; 828 #endif 829 } 830 831 if (n < 0x80000006) /* Some chips just has a large L1. */ 832 return; 833 834 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 835 l2size = ecx >> 16; 836 837 #ifdef CONFIG_X86_64 838 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 839 #else 840 /* do processor-specific cache resizing */ 841 if (this_cpu->legacy_cache_size) 842 l2size = this_cpu->legacy_cache_size(c, l2size); 843 844 /* Allow user to override all this if necessary. */ 845 if (cachesize_override != -1) 846 l2size = cachesize_override; 847 848 if (l2size == 0) 849 return; /* Again, no L2 cache is possible */ 850 #endif 851 852 c->x86_cache_size = l2size; 853 } 854 855 u16 __read_mostly tlb_lli_4k; 856 u16 __read_mostly tlb_lli_2m; 857 u16 __read_mostly tlb_lli_4m; 858 u16 __read_mostly tlb_lld_4k; 859 u16 __read_mostly tlb_lld_2m; 860 u16 __read_mostly tlb_lld_4m; 861 u16 __read_mostly tlb_lld_1g; 862 863 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 864 { 865 if (this_cpu->c_detect_tlb) 866 this_cpu->c_detect_tlb(c); 867 868 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 869 tlb_lli_4k, tlb_lli_2m, tlb_lli_4m); 870 871 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 872 tlb_lld_4k, tlb_lld_2m, tlb_lld_4m, tlb_lld_1g); 873 } 874 875 void get_cpu_vendor(struct cpuinfo_x86 *c) 876 { 877 char *v = c->x86_vendor_id; 878 int i; 879 880 for (i = 0; i < X86_VENDOR_NUM; i++) { 881 if (!cpu_devs[i]) 882 break; 883 884 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 885 (cpu_devs[i]->c_ident[1] && 886 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 887 888 this_cpu = cpu_devs[i]; 889 c->x86_vendor = this_cpu->c_x86_vendor; 890 return; 891 } 892 } 893 894 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 895 "CPU: Your system may be unstable.\n", v); 896 897 c->x86_vendor = X86_VENDOR_UNKNOWN; 898 this_cpu = &default_cpu; 899 } 900 901 void cpu_detect(struct cpuinfo_x86 *c) 902 { 903 /* Get vendor name */ 904 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 905 (unsigned int *)&c->x86_vendor_id[0], 906 (unsigned int *)&c->x86_vendor_id[8], 907 (unsigned int *)&c->x86_vendor_id[4]); 908 909 c->x86 = 4; 910 /* Intel-defined flags: level 0x00000001 */ 911 if (c->cpuid_level >= 0x00000001) { 912 u32 junk, tfms, cap0, misc; 913 914 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 915 c->x86 = x86_family(tfms); 916 c->x86_model = x86_model(tfms); 917 c->x86_stepping = x86_stepping(tfms); 918 919 if (cap0 & (1<<19)) { 920 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 921 c->x86_cache_alignment = c->x86_clflush_size; 922 } 923 } 924 } 925 926 static void apply_forced_caps(struct cpuinfo_x86 *c) 927 { 928 int i; 929 930 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 931 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 932 c->x86_capability[i] |= cpu_caps_set[i]; 933 } 934 } 935 936 static void init_speculation_control(struct cpuinfo_x86 *c) 937 { 938 /* 939 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 940 * and they also have a different bit for STIBP support. Also, 941 * a hypervisor might have set the individual AMD bits even on 942 * Intel CPUs, for finer-grained selection of what's available. 943 */ 944 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 945 set_cpu_cap(c, X86_FEATURE_IBRS); 946 set_cpu_cap(c, X86_FEATURE_IBPB); 947 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 948 } 949 950 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 951 set_cpu_cap(c, X86_FEATURE_STIBP); 952 953 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 954 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 955 set_cpu_cap(c, X86_FEATURE_SSBD); 956 957 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 958 set_cpu_cap(c, X86_FEATURE_IBRS); 959 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 960 } 961 962 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 963 set_cpu_cap(c, X86_FEATURE_IBPB); 964 965 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 966 set_cpu_cap(c, X86_FEATURE_STIBP); 967 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 968 } 969 970 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 971 set_cpu_cap(c, X86_FEATURE_SSBD); 972 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 973 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 974 } 975 } 976 977 void get_cpu_cap(struct cpuinfo_x86 *c) 978 { 979 u32 eax, ebx, ecx, edx; 980 981 /* Intel-defined flags: level 0x00000001 */ 982 if (c->cpuid_level >= 0x00000001) { 983 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 984 985 c->x86_capability[CPUID_1_ECX] = ecx; 986 c->x86_capability[CPUID_1_EDX] = edx; 987 } 988 989 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 990 if (c->cpuid_level >= 0x00000006) 991 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 992 993 /* Additional Intel-defined flags: level 0x00000007 */ 994 if (c->cpuid_level >= 0x00000007) { 995 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 996 c->x86_capability[CPUID_7_0_EBX] = ebx; 997 c->x86_capability[CPUID_7_ECX] = ecx; 998 c->x86_capability[CPUID_7_EDX] = edx; 999 1000 /* Check valid sub-leaf index before accessing it */ 1001 if (eax >= 1) { 1002 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1003 c->x86_capability[CPUID_7_1_EAX] = eax; 1004 } 1005 } 1006 1007 /* Extended state features: level 0x0000000d */ 1008 if (c->cpuid_level >= 0x0000000d) { 1009 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1010 1011 c->x86_capability[CPUID_D_1_EAX] = eax; 1012 } 1013 1014 /* 1015 * Check if extended CPUID leaves are implemented: Max extended 1016 * CPUID leaf must be in the 0x80000001-0x8000ffff range. 1017 */ 1018 eax = cpuid_eax(0x80000000); 1019 c->extended_cpuid_level = ((eax & 0xffff0000) == 0x80000000) ? eax : 0; 1020 1021 if (c->extended_cpuid_level >= 0x80000001) { 1022 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1023 1024 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1025 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1026 } 1027 1028 if (c->extended_cpuid_level >= 0x80000007) { 1029 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1030 1031 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1032 c->x86_power = edx; 1033 } 1034 1035 if (c->extended_cpuid_level >= 0x80000008) { 1036 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1037 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1038 } 1039 1040 if (c->extended_cpuid_level >= 0x8000000a) 1041 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1042 1043 if (c->extended_cpuid_level >= 0x8000001f) 1044 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1045 1046 if (c->extended_cpuid_level >= 0x80000021) 1047 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1048 1049 init_scattered_cpuid_features(c); 1050 init_speculation_control(c); 1051 1052 /* 1053 * Clear/Set all flags overridden by options, after probe. 1054 * This needs to happen each time we re-probe, which may happen 1055 * several times during CPU initialization. 1056 */ 1057 apply_forced_caps(c); 1058 } 1059 1060 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1061 { 1062 u32 eax, ebx, ecx, edx; 1063 1064 if (!cpu_has(c, X86_FEATURE_CPUID) || 1065 (c->extended_cpuid_level < 0x80000008)) { 1066 if (IS_ENABLED(CONFIG_X86_64)) { 1067 c->x86_clflush_size = 64; 1068 c->x86_phys_bits = 36; 1069 c->x86_virt_bits = 48; 1070 } else { 1071 c->x86_clflush_size = 32; 1072 c->x86_virt_bits = 32; 1073 c->x86_phys_bits = 32; 1074 1075 if (cpu_has(c, X86_FEATURE_PAE) || 1076 cpu_has(c, X86_FEATURE_PSE36)) 1077 c->x86_phys_bits = 36; 1078 } 1079 } else { 1080 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1081 1082 c->x86_virt_bits = (eax >> 8) & 0xff; 1083 c->x86_phys_bits = eax & 0xff; 1084 1085 /* Provide a sane default if not enumerated: */ 1086 if (!c->x86_clflush_size) 1087 c->x86_clflush_size = 32; 1088 } 1089 1090 c->x86_cache_bits = c->x86_phys_bits; 1091 c->x86_cache_alignment = c->x86_clflush_size; 1092 } 1093 1094 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1095 { 1096 int i; 1097 1098 /* 1099 * First of all, decide if this is a 486 or higher 1100 * It's a 486 if we can modify the AC flag 1101 */ 1102 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1103 c->x86 = 4; 1104 else 1105 c->x86 = 3; 1106 1107 for (i = 0; i < X86_VENDOR_NUM; i++) 1108 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1109 c->x86_vendor_id[0] = 0; 1110 cpu_devs[i]->c_identify(c); 1111 if (c->x86_vendor_id[0]) { 1112 get_cpu_vendor(c); 1113 break; 1114 } 1115 } 1116 } 1117 1118 #define NO_SPECULATION BIT(0) 1119 #define NO_MELTDOWN BIT(1) 1120 #define NO_SSB BIT(2) 1121 #define NO_L1TF BIT(3) 1122 #define NO_MDS BIT(4) 1123 #define MSBDS_ONLY BIT(5) 1124 #define NO_SWAPGS BIT(6) 1125 #define NO_ITLB_MULTIHIT BIT(7) 1126 #define NO_SPECTRE_V2 BIT(8) 1127 #define NO_MMIO BIT(9) 1128 #define NO_EIBRS_PBRSB BIT(10) 1129 #define NO_BHI BIT(11) 1130 1131 #define VULNWL(vendor, family, model, whitelist) \ 1132 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1133 1134 #define VULNWL_INTEL(vfm, whitelist) \ 1135 X86_MATCH_VFM(vfm, whitelist) 1136 1137 #define VULNWL_AMD(family, whitelist) \ 1138 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1139 1140 #define VULNWL_HYGON(family, whitelist) \ 1141 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1142 1143 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1144 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1145 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1146 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1147 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1148 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1149 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1150 1151 /* Intel Family 6 */ 1152 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), 1153 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), 1154 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), 1155 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), 1156 1157 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1158 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1159 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1160 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1161 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1162 1163 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1164 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1165 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1166 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1167 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1168 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1169 1170 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), 1171 1172 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY), 1173 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1174 1175 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1176 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1177 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1178 1179 /* 1180 * Technically, swapgs isn't serializing on AMD (despite it previously 1181 * being documented as such in the APM). But according to AMD, %gs is 1182 * updated non-speculatively, and the issuing of %gs-relative memory 1183 * operands will be blocked until the %gs update completes, which is 1184 * good enough for our purposes. 1185 */ 1186 1187 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), 1188 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1189 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1190 1191 /* AMD Family 0xf - 0x12 */ 1192 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1193 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1194 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1195 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1196 1197 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1198 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1199 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1200 1201 /* Zhaoxin Family 7 */ 1202 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1203 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1204 {} 1205 }; 1206 1207 #define VULNBL(vendor, family, model, blacklist) \ 1208 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1209 1210 #define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \ 1211 X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues) 1212 1213 #define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \ 1214 X86_MATCH_VFM_CPU_TYPE(vfm, INTEL_CPU_TYPE_##cpu_type, issues) 1215 1216 #define VULNBL_AMD(family, blacklist) \ 1217 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1218 1219 #define VULNBL_HYGON(family, blacklist) \ 1220 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1221 1222 #define SRBDS BIT(0) 1223 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1224 #define MMIO BIT(1) 1225 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1226 #define MMIO_SBDS BIT(2) 1227 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1228 #define RETBLEED BIT(3) 1229 /* CPU is affected by SMT (cross-thread) return predictions */ 1230 #define SMT_RSB BIT(4) 1231 /* CPU is affected by SRSO */ 1232 #define SRSO BIT(5) 1233 /* CPU is affected by GDS */ 1234 #define GDS BIT(6) 1235 /* CPU is affected by Register File Data Sampling */ 1236 #define RFDS BIT(7) 1237 /* CPU is affected by Indirect Target Selection */ 1238 #define ITS BIT(8) 1239 /* CPU is affected by Indirect Target Selection, but guest-host isolation is not affected */ 1240 #define ITS_NATIVE_ONLY BIT(9) 1241 /* CPU is affected by Transient Scheduler Attacks */ 1242 #define TSA BIT(10) 1243 /* CPU is affected by VMSCAPE */ 1244 #define VMSCAPE BIT(11) 1245 1246 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1247 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE_X, X86_STEP_MAX, VMSCAPE), 1248 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE, X86_STEP_MAX, VMSCAPE), 1249 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE_X, X86_STEP_MAX, VMSCAPE), 1250 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS | VMSCAPE), 1251 VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS | VMSCAPE), 1252 VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS | VMSCAPE), 1253 VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE), 1254 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO | VMSCAPE), 1255 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO | VMSCAPE), 1256 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO | VMSCAPE), 1257 VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE), 1258 VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS | VMSCAPE), 1259 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, 0x5, MMIO | RETBLEED | GDS | VMSCAPE), 1260 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | VMSCAPE), 1261 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1262 VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1263 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, 0xb, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1264 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE), 1265 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, 0xc, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1266 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE), 1267 VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED | VMSCAPE), 1268 VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1269 VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1270 VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1271 VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE), 1272 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED | ITS | VMSCAPE), 1273 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE), 1274 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1275 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1276 VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED), 1277 VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1278 VULNBL_INTEL_TYPE(INTEL_ALDERLAKE, ATOM, RFDS | VMSCAPE), 1279 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE, X86_STEP_MAX, VMSCAPE), 1280 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS | VMSCAPE), 1281 VULNBL_INTEL_TYPE(INTEL_RAPTORLAKE, ATOM, RFDS | VMSCAPE), 1282 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE, X86_STEP_MAX, VMSCAPE), 1283 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS | VMSCAPE), 1284 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS | VMSCAPE), 1285 VULNBL_INTEL_STEPS(INTEL_METEORLAKE_L, X86_STEP_MAX, VMSCAPE), 1286 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_H, X86_STEP_MAX, VMSCAPE), 1287 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE, X86_STEP_MAX, VMSCAPE), 1288 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_U, X86_STEP_MAX, VMSCAPE), 1289 VULNBL_INTEL_STEPS(INTEL_LUNARLAKE_M, X86_STEP_MAX, VMSCAPE), 1290 VULNBL_INTEL_STEPS(INTEL_SAPPHIRERAPIDS_X, X86_STEP_MAX, VMSCAPE), 1291 VULNBL_INTEL_STEPS(INTEL_GRANITERAPIDS_X, X86_STEP_MAX, VMSCAPE), 1292 VULNBL_INTEL_STEPS(INTEL_EMERALDRAPIDS_X, X86_STEP_MAX, VMSCAPE), 1293 VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS | VMSCAPE), 1294 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1295 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS), 1296 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1297 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS), 1298 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS), 1299 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS), 1300 VULNBL_INTEL_STEPS(INTEL_ATOM_CRESTMONT_X, X86_STEP_MAX, VMSCAPE), 1301 1302 VULNBL_AMD(0x15, RETBLEED), 1303 VULNBL_AMD(0x16, RETBLEED), 1304 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO | VMSCAPE), 1305 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO | VMSCAPE), 1306 VULNBL_AMD(0x19, SRSO | TSA | VMSCAPE), 1307 VULNBL_AMD(0x1a, SRSO | VMSCAPE), 1308 {} 1309 }; 1310 1311 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1312 { 1313 const struct x86_cpu_id *m = x86_match_cpu(table); 1314 1315 return m && !!(m->driver_data & which); 1316 } 1317 1318 u64 x86_read_arch_cap_msr(void) 1319 { 1320 u64 x86_arch_cap_msr = 0; 1321 1322 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1323 rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1324 1325 return x86_arch_cap_msr; 1326 } 1327 1328 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr) 1329 { 1330 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO && 1331 x86_arch_cap_msr & ARCH_CAP_PSDP_NO && 1332 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO); 1333 } 1334 1335 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr) 1336 { 1337 /* The "immunity" bit trumps everything else: */ 1338 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO) 1339 return false; 1340 1341 /* 1342 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to 1343 * indicate that mitigation is needed because guest is running on a 1344 * vulnerable hardware or may migrate to such hardware: 1345 */ 1346 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 1347 return true; 1348 1349 /* Only consult the blacklist when there is no enumeration: */ 1350 return cpu_matches(cpu_vuln_blacklist, RFDS); 1351 } 1352 1353 static bool __init vulnerable_to_its(u64 x86_arch_cap_msr) 1354 { 1355 /* The "immunity" bit trumps everything else: */ 1356 if (x86_arch_cap_msr & ARCH_CAP_ITS_NO) 1357 return false; 1358 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 1359 return false; 1360 1361 /* None of the affected CPUs have BHI_CTRL */ 1362 if (boot_cpu_has(X86_FEATURE_BHI_CTRL)) 1363 return false; 1364 1365 /* 1366 * If a VMM did not expose ITS_NO, assume that a guest could 1367 * be running on a vulnerable hardware or may migrate to such 1368 * hardware. 1369 */ 1370 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1371 return true; 1372 1373 if (cpu_matches(cpu_vuln_blacklist, ITS)) 1374 return true; 1375 1376 return false; 1377 } 1378 1379 static struct x86_cpu_id cpu_latest_microcode[] = { 1380 #include "microcode/intel-ucode-defs.h" 1381 {} 1382 }; 1383 1384 static bool __init cpu_has_old_microcode(void) 1385 { 1386 const struct x86_cpu_id *m = x86_match_cpu(cpu_latest_microcode); 1387 1388 /* Give unknown CPUs a pass: */ 1389 if (!m) { 1390 /* Intel CPUs should be in the list. Warn if not: */ 1391 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 1392 pr_info("x86/CPU: Model not found in latest microcode list\n"); 1393 return false; 1394 } 1395 1396 /* 1397 * Hosts usually lie to guests with a super high microcode 1398 * version. Just ignore what hosts tell guests: 1399 */ 1400 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1401 return false; 1402 1403 /* Consider all debug microcode to be old: */ 1404 if (boot_cpu_data.microcode & BIT(31)) 1405 return true; 1406 1407 /* Give new microcode a pass: */ 1408 if (boot_cpu_data.microcode >= m->driver_data) 1409 return false; 1410 1411 /* Uh oh, too old: */ 1412 return true; 1413 } 1414 1415 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1416 { 1417 u64 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1418 1419 if (cpu_has_old_microcode()) { 1420 pr_warn("x86/CPU: Running old microcode\n"); 1421 setup_force_cpu_bug(X86_BUG_OLD_MICROCODE); 1422 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1423 } 1424 1425 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1426 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1427 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO)) 1428 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1429 1430 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1431 return; 1432 1433 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1434 1435 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) { 1436 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1437 setup_force_cpu_bug(X86_BUG_SPECTRE_V2_USER); 1438 } 1439 1440 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1441 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) && 1442 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1443 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1444 1445 /* 1446 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1447 * flag and protect from vendor-specific bugs via the whitelist. 1448 * 1449 * Don't use AutoIBRS when SNP is enabled because it degrades host 1450 * userspace indirect branch performance. 1451 */ 1452 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || 1453 (cpu_has(c, X86_FEATURE_AUTOIBRS) && 1454 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { 1455 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1456 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1457 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO)) 1458 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1459 } 1460 1461 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1462 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) { 1463 setup_force_cpu_bug(X86_BUG_MDS); 1464 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1465 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1466 } 1467 1468 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1469 setup_force_cpu_bug(X86_BUG_SWAPGS); 1470 1471 /* 1472 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1473 * - TSX is supported or 1474 * - TSX_CTRL is present 1475 * 1476 * TSX_CTRL check is needed for cases when TSX could be disabled before 1477 * the kernel boot e.g. kexec. 1478 * TSX_CTRL check alone is not sufficient for cases when the microcode 1479 * update is not present or running as guest that don't get TSX_CTRL. 1480 */ 1481 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) && 1482 (cpu_has(c, X86_FEATURE_RTM) || 1483 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))) 1484 setup_force_cpu_bug(X86_BUG_TAA); 1485 1486 /* 1487 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1488 * in the vulnerability blacklist. 1489 * 1490 * Some of the implications and mitigation of Shared Buffers Data 1491 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1492 * SRBDS. 1493 */ 1494 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1495 cpu_has(c, X86_FEATURE_RDSEED)) && 1496 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1497 setup_force_cpu_bug(X86_BUG_SRBDS); 1498 1499 /* 1500 * Processor MMIO Stale Data bug enumeration 1501 * 1502 * Affected CPU list is generally enough to enumerate the vulnerability, 1503 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1504 * not want the guest to enumerate the bug. 1505 */ 1506 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { 1507 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1508 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1509 } 1510 1511 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1512 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA)) 1513 setup_force_cpu_bug(X86_BUG_RETBLEED); 1514 } 1515 1516 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1517 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1518 1519 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1520 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1521 setup_force_cpu_bug(X86_BUG_SRSO); 1522 } 1523 1524 /* 1525 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1526 * an affected processor, the VMM may have disabled the use of GATHER by 1527 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1528 * which means that AVX will be disabled. 1529 */ 1530 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) && 1531 boot_cpu_has(X86_FEATURE_AVX)) 1532 setup_force_cpu_bug(X86_BUG_GDS); 1533 1534 if (vulnerable_to_rfds(x86_arch_cap_msr)) 1535 setup_force_cpu_bug(X86_BUG_RFDS); 1536 1537 /* 1538 * Intel parts with eIBRS are vulnerable to BHI attacks. Parts with 1539 * BHI_NO still need to use the BHI mitigation to prevent Intra-mode 1540 * attacks. When virtualized, eIBRS could be hidden, assume vulnerable. 1541 */ 1542 if (!cpu_matches(cpu_vuln_whitelist, NO_BHI) && 1543 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) || 1544 boot_cpu_has(X86_FEATURE_HYPERVISOR))) 1545 setup_force_cpu_bug(X86_BUG_BHI); 1546 1547 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET)) 1548 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET); 1549 1550 if (vulnerable_to_its(x86_arch_cap_msr)) { 1551 setup_force_cpu_bug(X86_BUG_ITS); 1552 if (cpu_matches(cpu_vuln_blacklist, ITS_NATIVE_ONLY)) 1553 setup_force_cpu_bug(X86_BUG_ITS_NATIVE_ONLY); 1554 } 1555 1556 if (c->x86_vendor == X86_VENDOR_AMD) { 1557 if (!cpu_has(c, X86_FEATURE_TSA_SQ_NO) || 1558 !cpu_has(c, X86_FEATURE_TSA_L1_NO)) { 1559 if (cpu_matches(cpu_vuln_blacklist, TSA) || 1560 /* Enable bug on Zen guests to allow for live migration. */ 1561 (cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_ZEN))) 1562 setup_force_cpu_bug(X86_BUG_TSA); 1563 } 1564 } 1565 1566 /* 1567 * Set the bug only on bare-metal. A nested hypervisor should already be 1568 * deploying IBPB to isolate itself from nested guests. 1569 */ 1570 if (cpu_matches(cpu_vuln_blacklist, VMSCAPE) && 1571 !boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1572 setup_force_cpu_bug(X86_BUG_VMSCAPE); 1573 1574 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1575 return; 1576 1577 /* Rogue Data Cache Load? No! */ 1578 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO) 1579 return; 1580 1581 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1582 1583 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1584 return; 1585 1586 setup_force_cpu_bug(X86_BUG_L1TF); 1587 } 1588 1589 /* 1590 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1591 * unfortunately, that's not true in practice because of early VIA 1592 * chips and (more importantly) broken virtualizers that are not easy 1593 * to detect. In the latter case it doesn't even *fail* reliably, so 1594 * probing for it doesn't even work. Disable it completely on 32-bit 1595 * unless we can find a reliable way to detect all the broken cases. 1596 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1597 */ 1598 static void detect_nopl(void) 1599 { 1600 #ifdef CONFIG_X86_32 1601 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1602 #else 1603 setup_force_cpu_cap(X86_FEATURE_NOPL); 1604 #endif 1605 } 1606 1607 static inline bool parse_set_clear_cpuid(char *arg, bool set) 1608 { 1609 char *opt; 1610 int taint = 0; 1611 1612 while (arg) { 1613 bool found __maybe_unused = false; 1614 unsigned int bit; 1615 1616 opt = strsep(&arg, ","); 1617 1618 /* 1619 * Handle naked numbers first for feature flags which don't 1620 * have names. It doesn't make sense for a bug not to have a 1621 * name so don't handle bug flags here. 1622 */ 1623 if (!kstrtouint(opt, 10, &bit)) { 1624 if (bit < NCAPINTS * 32) { 1625 1626 if (set) { 1627 pr_warn("setcpuid: force-enabling CPU feature flag:"); 1628 setup_force_cpu_cap(bit); 1629 } else { 1630 pr_warn("clearcpuid: force-disabling CPU feature flag:"); 1631 setup_clear_cpu_cap(bit); 1632 } 1633 /* empty-string, i.e., ""-defined feature flags */ 1634 if (!x86_cap_flags[bit]) 1635 pr_cont(" %d:%d\n", bit >> 5, bit & 31); 1636 else 1637 pr_cont(" %s\n", x86_cap_flags[bit]); 1638 1639 taint++; 1640 } 1641 /* 1642 * The assumption is that there are no feature names with only 1643 * numbers in the name thus go to the next argument. 1644 */ 1645 continue; 1646 } 1647 1648 for (bit = 0; bit < 32 * (NCAPINTS + NBUGINTS); bit++) { 1649 const char *flag; 1650 const char *kind; 1651 1652 if (bit < 32 * NCAPINTS) { 1653 flag = x86_cap_flags[bit]; 1654 kind = "feature"; 1655 } else { 1656 kind = "bug"; 1657 flag = x86_bug_flags[bit - (32 * NCAPINTS)]; 1658 } 1659 1660 if (!flag) 1661 continue; 1662 1663 if (strcmp(flag, opt)) 1664 continue; 1665 1666 if (set) { 1667 pr_warn("setcpuid: force-enabling CPU %s flag: %s\n", 1668 kind, flag); 1669 setup_force_cpu_cap(bit); 1670 } else { 1671 pr_warn("clearcpuid: force-disabling CPU %s flag: %s\n", 1672 kind, flag); 1673 setup_clear_cpu_cap(bit); 1674 } 1675 taint++; 1676 found = true; 1677 break; 1678 } 1679 1680 if (!found) 1681 pr_warn("%s: unknown CPU flag: %s", set ? "setcpuid" : "clearcpuid", opt); 1682 } 1683 1684 return taint; 1685 } 1686 1687 1688 /* 1689 * We parse cpu parameters early because fpu__init_system() is executed 1690 * before parse_early_param(). 1691 */ 1692 static void __init cpu_parse_early_param(void) 1693 { 1694 bool cpuid_taint = false; 1695 char arg[128]; 1696 int arglen; 1697 1698 #ifdef CONFIG_X86_32 1699 if (cmdline_find_option_bool(boot_command_line, "no387")) 1700 #ifdef CONFIG_MATH_EMULATION 1701 setup_clear_cpu_cap(X86_FEATURE_FPU); 1702 #else 1703 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1704 #endif 1705 1706 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1707 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1708 #endif 1709 1710 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1711 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1712 1713 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1714 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1715 1716 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1717 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1718 1719 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1720 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1721 1722 /* Minimize the gap between FRED is available and available but disabled. */ 1723 arglen = cmdline_find_option(boot_command_line, "fred", arg, sizeof(arg)); 1724 if (arglen != 2 || strncmp(arg, "on", 2)) 1725 setup_clear_cpu_cap(X86_FEATURE_FRED); 1726 1727 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1728 if (arglen > 0) 1729 cpuid_taint |= parse_set_clear_cpuid(arg, false); 1730 1731 arglen = cmdline_find_option(boot_command_line, "setcpuid", arg, sizeof(arg)); 1732 if (arglen > 0) 1733 cpuid_taint |= parse_set_clear_cpuid(arg, true); 1734 1735 if (cpuid_taint) { 1736 pr_warn("!!! setcpuid=/clearcpuid= in use, this is for TESTING ONLY, may break things horribly. Tainting kernel.\n"); 1737 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1738 } 1739 } 1740 1741 /* 1742 * Do minimum CPU detection early. 1743 * Fields really needed: vendor, cpuid_level, family, model, mask, 1744 * cache alignment. 1745 * The others are not touched to avoid unwanted side effects. 1746 * 1747 * WARNING: this function is only called on the boot CPU. Don't add code 1748 * here that is supposed to run on all CPUs. 1749 */ 1750 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1751 { 1752 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1753 c->extended_cpuid_level = 0; 1754 1755 if (!cpuid_feature()) 1756 identify_cpu_without_cpuid(c); 1757 1758 /* cyrix could have cpuid enabled via c_identify()*/ 1759 if (cpuid_feature()) { 1760 cpu_detect(c); 1761 get_cpu_vendor(c); 1762 intel_unlock_cpuid_leafs(c); 1763 get_cpu_cap(c); 1764 setup_force_cpu_cap(X86_FEATURE_CPUID); 1765 get_cpu_address_sizes(c); 1766 cpu_parse_early_param(); 1767 1768 cpu_init_topology(c); 1769 1770 if (this_cpu->c_early_init) 1771 this_cpu->c_early_init(c); 1772 1773 c->cpu_index = 0; 1774 filter_cpuid_features(c, false); 1775 check_cpufeature_deps(c); 1776 1777 if (this_cpu->c_bsp_init) 1778 this_cpu->c_bsp_init(c); 1779 } else { 1780 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1781 get_cpu_address_sizes(c); 1782 cpu_init_topology(c); 1783 } 1784 1785 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1786 1787 cpu_set_bug_bits(c); 1788 1789 sld_setup(c); 1790 1791 #ifdef CONFIG_X86_32 1792 /* 1793 * Regardless of whether PCID is enumerated, the SDM says 1794 * that it can't be enabled in 32-bit mode. 1795 */ 1796 setup_clear_cpu_cap(X86_FEATURE_PCID); 1797 #endif 1798 1799 /* 1800 * Later in the boot process pgtable_l5_enabled() relies on 1801 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1802 * enabled by this point we need to clear the feature bit to avoid 1803 * false-positives at the later stage. 1804 * 1805 * pgtable_l5_enabled() can be false here for several reasons: 1806 * - 5-level paging is disabled compile-time; 1807 * - it's 32-bit kernel; 1808 * - machine doesn't support 5-level paging; 1809 * - user specified 'no5lvl' in kernel command line. 1810 */ 1811 if (!pgtable_l5_enabled()) 1812 setup_clear_cpu_cap(X86_FEATURE_LA57); 1813 1814 detect_nopl(); 1815 mca_bsp_init(c); 1816 } 1817 1818 void __init init_cpu_devs(void) 1819 { 1820 const struct cpu_dev *const *cdev; 1821 int count = 0; 1822 1823 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1824 const struct cpu_dev *cpudev = *cdev; 1825 1826 if (count >= X86_VENDOR_NUM) 1827 break; 1828 cpu_devs[count] = cpudev; 1829 count++; 1830 } 1831 } 1832 1833 void __init early_cpu_init(void) 1834 { 1835 #ifdef CONFIG_PROCESSOR_SELECT 1836 unsigned int i, j; 1837 1838 pr_info("KERNEL supported cpus:\n"); 1839 #endif 1840 1841 init_cpu_devs(); 1842 1843 #ifdef CONFIG_PROCESSOR_SELECT 1844 for (i = 0; i < X86_VENDOR_NUM && cpu_devs[i]; i++) { 1845 for (j = 0; j < 2; j++) { 1846 if (!cpu_devs[i]->c_ident[j]) 1847 continue; 1848 pr_info(" %s %s\n", cpu_devs[i]->c_vendor, 1849 cpu_devs[i]->c_ident[j]); 1850 } 1851 } 1852 #endif 1853 1854 early_identify_cpu(&boot_cpu_data); 1855 } 1856 1857 static bool detect_null_seg_behavior(void) 1858 { 1859 /* 1860 * Empirically, writing zero to a segment selector on AMD does 1861 * not clear the base, whereas writing zero to a segment 1862 * selector on Intel does clear the base. Intel's behavior 1863 * allows slightly faster context switches in the common case 1864 * where GS is unused by the prev and next threads. 1865 * 1866 * Since neither vendor documents this anywhere that I can see, 1867 * detect it directly instead of hard-coding the choice by 1868 * vendor. 1869 * 1870 * I've designated AMD's behavior as the "bug" because it's 1871 * counterintuitive and less friendly. 1872 */ 1873 1874 unsigned long old_base, tmp; 1875 rdmsrq(MSR_FS_BASE, old_base); 1876 wrmsrq(MSR_FS_BASE, 1); 1877 loadsegment(fs, 0); 1878 rdmsrq(MSR_FS_BASE, tmp); 1879 wrmsrq(MSR_FS_BASE, old_base); 1880 return tmp == 0; 1881 } 1882 1883 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1884 { 1885 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1886 if (!IS_ENABLED(CONFIG_X86_64)) 1887 return; 1888 1889 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1890 return; 1891 1892 /* 1893 * CPUID bit above wasn't set. If this kernel is still running 1894 * as a HV guest, then the HV has decided not to advertize 1895 * that CPUID bit for whatever reason. For example, one 1896 * member of the migration pool might be vulnerable. Which 1897 * means, the bug is present: set the BUG flag and return. 1898 */ 1899 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1900 set_cpu_bug(c, X86_BUG_NULL_SEG); 1901 return; 1902 } 1903 1904 /* 1905 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1906 * 0x18 is the respective family for Hygon. 1907 */ 1908 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1909 detect_null_seg_behavior()) 1910 return; 1911 1912 /* All the remaining ones are affected */ 1913 set_cpu_bug(c, X86_BUG_NULL_SEG); 1914 } 1915 1916 static void generic_identify(struct cpuinfo_x86 *c) 1917 { 1918 c->extended_cpuid_level = 0; 1919 1920 if (!cpuid_feature()) 1921 identify_cpu_without_cpuid(c); 1922 1923 /* cyrix could have cpuid enabled via c_identify()*/ 1924 if (!cpuid_feature()) 1925 return; 1926 1927 cpu_detect(c); 1928 1929 get_cpu_vendor(c); 1930 intel_unlock_cpuid_leafs(c); 1931 get_cpu_cap(c); 1932 1933 get_cpu_address_sizes(c); 1934 1935 get_model_name(c); /* Default name */ 1936 1937 /* 1938 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1939 * systems that run Linux at CPL > 0 may or may not have the 1940 * issue, but, even if they have the issue, there's absolutely 1941 * nothing we can do about it because we can't use the real IRET 1942 * instruction. 1943 * 1944 * NB: For the time being, only 32-bit kernels support 1945 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1946 * whether to apply espfix using paravirt hooks. If any 1947 * non-paravirt system ever shows up that does *not* have the 1948 * ESPFIX issue, we can change this. 1949 */ 1950 #ifdef CONFIG_X86_32 1951 set_cpu_bug(c, X86_BUG_ESPFIX); 1952 #endif 1953 } 1954 1955 /* 1956 * This does the hard work of actually picking apart the CPU stuff... 1957 */ 1958 static void identify_cpu(struct cpuinfo_x86 *c) 1959 { 1960 int i; 1961 1962 c->loops_per_jiffy = loops_per_jiffy; 1963 c->x86_cache_size = 0; 1964 c->x86_vendor = X86_VENDOR_UNKNOWN; 1965 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1966 c->x86_vendor_id[0] = '\0'; /* Unset */ 1967 c->x86_model_id[0] = '\0'; /* Unset */ 1968 #ifdef CONFIG_X86_64 1969 c->x86_clflush_size = 64; 1970 c->x86_phys_bits = 36; 1971 c->x86_virt_bits = 48; 1972 #else 1973 c->cpuid_level = -1; /* CPUID not detected */ 1974 c->x86_clflush_size = 32; 1975 c->x86_phys_bits = 32; 1976 c->x86_virt_bits = 32; 1977 #endif 1978 c->x86_cache_alignment = c->x86_clflush_size; 1979 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1980 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1981 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1982 #endif 1983 1984 generic_identify(c); 1985 1986 cpu_parse_topology(c); 1987 1988 if (this_cpu->c_identify) 1989 this_cpu->c_identify(c); 1990 1991 /* Clear/Set all flags overridden by options, after probe */ 1992 apply_forced_caps(c); 1993 1994 /* 1995 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 1996 * Hygon will clear it in ->c_init() below. 1997 */ 1998 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1999 2000 /* 2001 * Vendor-specific initialization. In this section we 2002 * canonicalize the feature flags, meaning if there are 2003 * features a certain CPU supports which CPUID doesn't 2004 * tell us, CPUID claiming incorrect flags, or other bugs, 2005 * we handle them here. 2006 * 2007 * At the end of this section, c->x86_capability better 2008 * indicate the features this CPU genuinely supports! 2009 */ 2010 if (this_cpu->c_init) 2011 this_cpu->c_init(c); 2012 2013 bus_lock_init(); 2014 2015 /* Disable the PN if appropriate */ 2016 squash_the_stupid_serial_number(c); 2017 2018 /* Set up SMEP/SMAP/UMIP */ 2019 setup_smep(c); 2020 setup_smap(c); 2021 setup_umip(c); 2022 2023 /* Enable FSGSBASE instructions if available. */ 2024 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 2025 cr4_set_bits(X86_CR4_FSGSBASE); 2026 elf_hwcap2 |= HWCAP2_FSGSBASE; 2027 } 2028 2029 /* 2030 * The vendor-specific functions might have changed features. 2031 * Now we do "generic changes." 2032 */ 2033 2034 /* Filter out anything that depends on CPUID levels we don't have */ 2035 filter_cpuid_features(c, true); 2036 2037 /* Check for unmet dependencies based on the CPUID dependency table */ 2038 check_cpufeature_deps(c); 2039 2040 /* If the model name is still unset, do table lookup. */ 2041 if (!c->x86_model_id[0]) { 2042 const char *p; 2043 p = table_lookup_model(c); 2044 if (p) 2045 strcpy(c->x86_model_id, p); 2046 else 2047 /* Last resort... */ 2048 sprintf(c->x86_model_id, "%02x/%02x", 2049 c->x86, c->x86_model); 2050 } 2051 2052 x86_init_rdrand(c); 2053 setup_pku(c); 2054 setup_cet(c); 2055 2056 /* 2057 * Clear/Set all flags overridden by options, need do it 2058 * before following smp all cpus cap AND. 2059 */ 2060 apply_forced_caps(c); 2061 2062 /* 2063 * On SMP, boot_cpu_data holds the common feature set between 2064 * all CPUs; so make sure that we indicate which features are 2065 * common between the CPUs. The first time this routine gets 2066 * executed, c == &boot_cpu_data. 2067 */ 2068 if (c != &boot_cpu_data) { 2069 /* AND the already accumulated flags with these */ 2070 for (i = 0; i < NCAPINTS; i++) 2071 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 2072 2073 /* OR, i.e. replicate the bug flags */ 2074 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 2075 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 2076 } 2077 2078 ppin_init(c); 2079 2080 /* Init Machine Check Exception if available. */ 2081 mcheck_cpu_init(c); 2082 2083 numa_add_cpu(smp_processor_id()); 2084 } 2085 2086 /* 2087 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 2088 * on 32-bit kernels: 2089 */ 2090 #ifdef CONFIG_X86_32 2091 void enable_sep_cpu(void) 2092 { 2093 struct tss_struct *tss; 2094 int cpu; 2095 2096 if (!boot_cpu_has(X86_FEATURE_SEP)) 2097 return; 2098 2099 cpu = get_cpu(); 2100 tss = &per_cpu(cpu_tss_rw, cpu); 2101 2102 /* 2103 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 2104 * see the big comment in struct x86_hw_tss's definition. 2105 */ 2106 2107 tss->x86_tss.ss1 = __KERNEL_CS; 2108 wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1); 2109 wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 2110 wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32); 2111 2112 put_cpu(); 2113 } 2114 #endif 2115 2116 static __init void identify_boot_cpu(void) 2117 { 2118 identify_cpu(&boot_cpu_data); 2119 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 2120 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 2121 #ifdef CONFIG_X86_32 2122 enable_sep_cpu(); 2123 #endif 2124 cpu_detect_tlb(&boot_cpu_data); 2125 setup_cr_pinning(); 2126 2127 tsx_init(); 2128 tdx_init(); 2129 lkgs_init(); 2130 } 2131 2132 void identify_secondary_cpu(unsigned int cpu) 2133 { 2134 struct cpuinfo_x86 *c = &cpu_data(cpu); 2135 2136 /* Copy boot_cpu_data only on the first bringup */ 2137 if (!c->initialized) 2138 *c = boot_cpu_data; 2139 c->cpu_index = cpu; 2140 2141 identify_cpu(c); 2142 #ifdef CONFIG_X86_32 2143 enable_sep_cpu(); 2144 #endif 2145 x86_spec_ctrl_setup_ap(); 2146 update_srbds_msr(); 2147 if (boot_cpu_has_bug(X86_BUG_GDS)) 2148 update_gds_msr(); 2149 2150 tsx_ap_init(); 2151 c->initialized = true; 2152 } 2153 2154 void print_cpu_info(struct cpuinfo_x86 *c) 2155 { 2156 const char *vendor = NULL; 2157 2158 if (c->x86_vendor < X86_VENDOR_NUM) { 2159 vendor = this_cpu->c_vendor; 2160 } else { 2161 if (c->cpuid_level >= 0) 2162 vendor = c->x86_vendor_id; 2163 } 2164 2165 if (vendor && !strstr(c->x86_model_id, vendor)) 2166 pr_cont("%s ", vendor); 2167 2168 if (c->x86_model_id[0]) 2169 pr_cont("%s", c->x86_model_id); 2170 else 2171 pr_cont("%d86", c->x86); 2172 2173 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2174 2175 if (c->x86_stepping || c->cpuid_level >= 0) 2176 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2177 else 2178 pr_cont(")\n"); 2179 } 2180 2181 /* 2182 * clearcpuid= and setcpuid= were already parsed in cpu_parse_early_param(). 2183 * These dummy functions prevent them from becoming an environment variable for 2184 * init. 2185 */ 2186 2187 static __init int setup_clearcpuid(char *arg) 2188 { 2189 return 1; 2190 } 2191 __setup("clearcpuid=", setup_clearcpuid); 2192 2193 static __init int setup_setcpuid(char *arg) 2194 { 2195 return 1; 2196 } 2197 __setup("setcpuid=", setup_setcpuid); 2198 2199 DEFINE_PER_CPU_CACHE_HOT(struct task_struct *, current_task) = &init_task; 2200 EXPORT_PER_CPU_SYMBOL(current_task); 2201 EXPORT_PER_CPU_SYMBOL(const_current_task); 2202 2203 DEFINE_PER_CPU_CACHE_HOT(int, __preempt_count) = INIT_PREEMPT_COUNT; 2204 EXPORT_PER_CPU_SYMBOL(__preempt_count); 2205 2206 DEFINE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 2207 2208 #ifdef CONFIG_X86_64 2209 /* 2210 * Note: Do not make this dependant on CONFIG_MITIGATION_CALL_DEPTH_TRACKING 2211 * so that this space is reserved in the hot cache section even when the 2212 * mitigation is disabled. 2213 */ 2214 DEFINE_PER_CPU_CACHE_HOT(u64, __x86_call_depth); 2215 EXPORT_PER_CPU_SYMBOL(__x86_call_depth); 2216 2217 static void wrmsrq_cstar(unsigned long val) 2218 { 2219 /* 2220 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2221 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2222 * guest. Avoid the pointless write on all Intel CPUs. 2223 */ 2224 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2225 wrmsrq(MSR_CSTAR, val); 2226 } 2227 2228 static inline void idt_syscall_init(void) 2229 { 2230 wrmsrq(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2231 2232 if (ia32_enabled()) { 2233 wrmsrq_cstar((unsigned long)entry_SYSCALL_compat); 2234 /* 2235 * This only works on Intel CPUs. 2236 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2237 * This does not cause SYSENTER to jump to the wrong location, because 2238 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2239 */ 2240 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2241 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 2242 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2243 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2244 } else { 2245 wrmsrq_cstar((unsigned long)entry_SYSCALL32_ignore); 2246 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2247 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2248 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2249 } 2250 2251 /* 2252 * Flags to clear on syscall; clear as much as possible 2253 * to minimize user space-kernel interference. 2254 */ 2255 wrmsrq(MSR_SYSCALL_MASK, 2256 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2257 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2258 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2259 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2260 X86_EFLAGS_AC|X86_EFLAGS_ID); 2261 } 2262 2263 /* May not be marked __init: used by software suspend */ 2264 void syscall_init(void) 2265 { 2266 /* The default user and kernel segments */ 2267 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2268 2269 /* 2270 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and 2271 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED 2272 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit 2273 * instruction to return to ring 3 (both sysexit and sysret cause 2274 * #UD when FRED is enabled). 2275 */ 2276 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2277 idt_syscall_init(); 2278 } 2279 #endif /* CONFIG_X86_64 */ 2280 2281 #ifdef CONFIG_STACKPROTECTOR 2282 DEFINE_PER_CPU_CACHE_HOT(unsigned long, __stack_chk_guard); 2283 #ifndef CONFIG_SMP 2284 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2285 #endif 2286 #endif 2287 2288 static void initialize_debug_regs(void) 2289 { 2290 /* Control register first -- to make sure everything is disabled. */ 2291 set_debugreg(DR7_FIXED_1, 7); 2292 set_debugreg(DR6_RESERVED, 6); 2293 /* dr5 and dr4 don't exist */ 2294 set_debugreg(0, 3); 2295 set_debugreg(0, 2); 2296 set_debugreg(0, 1); 2297 set_debugreg(0, 0); 2298 } 2299 2300 #ifdef CONFIG_KGDB 2301 /* 2302 * Restore debug regs if using kgdbwait and you have a kernel debugger 2303 * connection established. 2304 */ 2305 static void dbg_restore_debug_regs(void) 2306 { 2307 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2308 arch_kgdb_ops.correct_hw_break(); 2309 } 2310 #else /* ! CONFIG_KGDB */ 2311 #define dbg_restore_debug_regs() 2312 #endif /* ! CONFIG_KGDB */ 2313 2314 static inline void setup_getcpu(int cpu) 2315 { 2316 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2317 struct desc_struct d = { }; 2318 2319 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2320 wrmsrq(MSR_TSC_AUX, cpudata); 2321 2322 /* Store CPU and node number in limit. */ 2323 d.limit0 = cpudata; 2324 d.limit1 = cpudata >> 16; 2325 2326 d.type = 5; /* RO data, expand down, accessed */ 2327 d.dpl = 3; /* Visible to user code */ 2328 d.s = 1; /* Not a system segment */ 2329 d.p = 1; /* Present */ 2330 d.d = 1; /* 32-bit */ 2331 2332 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2333 } 2334 2335 #ifdef CONFIG_X86_64 2336 static inline void tss_setup_ist(struct tss_struct *tss) 2337 { 2338 /* Set up the per-CPU TSS IST stacks */ 2339 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2340 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2341 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2342 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2343 /* Only mapped when SEV-ES is active */ 2344 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2345 } 2346 #else /* CONFIG_X86_64 */ 2347 static inline void tss_setup_ist(struct tss_struct *tss) { } 2348 #endif /* !CONFIG_X86_64 */ 2349 2350 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2351 { 2352 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2353 2354 #ifdef CONFIG_X86_IOPL_IOPERM 2355 tss->io_bitmap.prev_max = 0; 2356 tss->io_bitmap.prev_sequence = 0; 2357 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2358 /* 2359 * Invalidate the extra array entry past the end of the all 2360 * permission bitmap as required by the hardware. 2361 */ 2362 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2363 #endif 2364 } 2365 2366 /* 2367 * Setup everything needed to handle exceptions from the IDT, including the IST 2368 * exceptions which use paranoid_entry(). 2369 */ 2370 void cpu_init_exception_handling(bool boot_cpu) 2371 { 2372 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2373 int cpu = raw_smp_processor_id(); 2374 2375 /* paranoid_entry() gets the CPU number from the GDT */ 2376 setup_getcpu(cpu); 2377 2378 /* For IDT mode, IST vectors need to be set in TSS. */ 2379 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2380 tss_setup_ist(tss); 2381 tss_setup_io_bitmap(tss); 2382 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2383 2384 load_TR_desc(); 2385 2386 /* GHCB needs to be setup to handle #VC. */ 2387 setup_ghcb(); 2388 2389 if (cpu_feature_enabled(X86_FEATURE_FRED)) { 2390 /* The boot CPU has enabled FRED during early boot */ 2391 if (!boot_cpu) 2392 cpu_init_fred_exceptions(); 2393 2394 cpu_init_fred_rsps(); 2395 } else { 2396 load_current_idt(); 2397 } 2398 } 2399 2400 void __init cpu_init_replace_early_idt(void) 2401 { 2402 if (cpu_feature_enabled(X86_FEATURE_FRED)) 2403 cpu_init_fred_exceptions(); 2404 else 2405 idt_setup_early_pf(); 2406 } 2407 2408 /* 2409 * cpu_init() initializes state that is per-CPU. Some data is already 2410 * initialized (naturally) in the bootstrap process, such as the GDT. We 2411 * reload it nevertheless, this function acts as a 'CPU state barrier', 2412 * nothing should get across. 2413 */ 2414 void cpu_init(void) 2415 { 2416 struct task_struct *cur = current; 2417 int cpu = raw_smp_processor_id(); 2418 2419 #ifdef CONFIG_NUMA 2420 if (this_cpu_read(numa_node) == 0 && 2421 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2422 set_numa_node(early_cpu_to_node(cpu)); 2423 #endif 2424 pr_debug("Initializing CPU#%d\n", cpu); 2425 2426 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2427 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2428 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2429 2430 if (IS_ENABLED(CONFIG_X86_64)) { 2431 loadsegment(fs, 0); 2432 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2433 syscall_init(); 2434 2435 wrmsrq(MSR_FS_BASE, 0); 2436 wrmsrq(MSR_KERNEL_GS_BASE, 0); 2437 barrier(); 2438 2439 x2apic_setup(); 2440 2441 intel_posted_msi_init(); 2442 } 2443 2444 mmgrab(&init_mm); 2445 cur->active_mm = &init_mm; 2446 BUG_ON(cur->mm); 2447 initialize_tlbstate_and_flush(); 2448 enter_lazy_tlb(&init_mm, cur); 2449 2450 /* 2451 * sp0 points to the entry trampoline stack regardless of what task 2452 * is running. 2453 */ 2454 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2455 2456 load_mm_ldt(&init_mm); 2457 2458 initialize_debug_regs(); 2459 dbg_restore_debug_regs(); 2460 2461 doublefault_init_cpu_tss(); 2462 2463 if (is_uv_system()) 2464 uv_cpu_init(); 2465 2466 load_fixmap_gdt(cpu); 2467 } 2468 2469 #ifdef CONFIG_MICROCODE_LATE_LOADING 2470 /** 2471 * store_cpu_caps() - Store a snapshot of CPU capabilities 2472 * @curr_info: Pointer where to store it 2473 * 2474 * Returns: None 2475 */ 2476 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2477 { 2478 /* Reload CPUID max function as it might've changed. */ 2479 curr_info->cpuid_level = cpuid_eax(0); 2480 2481 /* Copy all capability leafs and pick up the synthetic ones. */ 2482 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2483 sizeof(curr_info->x86_capability)); 2484 2485 /* Get the hardware CPUID leafs */ 2486 get_cpu_cap(curr_info); 2487 } 2488 2489 /** 2490 * microcode_check() - Check if any CPU capabilities changed after an update. 2491 * @prev_info: CPU capabilities stored before an update. 2492 * 2493 * The microcode loader calls this upon late microcode load to recheck features, 2494 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2495 * 2496 * Return: None 2497 */ 2498 void microcode_check(struct cpuinfo_x86 *prev_info) 2499 { 2500 struct cpuinfo_x86 curr_info; 2501 2502 perf_check_microcode(); 2503 2504 amd_check_microcode(); 2505 2506 store_cpu_caps(&curr_info); 2507 2508 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2509 sizeof(prev_info->x86_capability))) 2510 return; 2511 2512 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2513 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2514 } 2515 #endif 2516 2517 /* 2518 * Invoked from core CPU hotplug code after hotplug operations 2519 */ 2520 void arch_smt_update(void) 2521 { 2522 /* Handle the speculative execution misfeatures */ 2523 cpu_bugs_smt_update(); 2524 /* Check whether IPI broadcasting can be enabled */ 2525 apic_smt_update(); 2526 } 2527 2528 void __init arch_cpu_finalize_init(void) 2529 { 2530 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 2531 2532 identify_boot_cpu(); 2533 2534 select_idle_routine(); 2535 2536 /* 2537 * identify_boot_cpu() initialized SMT support information, let the 2538 * core code know. 2539 */ 2540 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core); 2541 2542 if (!IS_ENABLED(CONFIG_SMP)) { 2543 pr_info("CPU: "); 2544 print_cpu_info(&boot_cpu_data); 2545 } 2546 2547 cpu_select_mitigations(); 2548 2549 arch_smt_update(); 2550 2551 if (IS_ENABLED(CONFIG_X86_32)) { 2552 /* 2553 * Check whether this is a real i386 which is not longer 2554 * supported and fixup the utsname. 2555 */ 2556 if (boot_cpu_data.x86 < 4) 2557 panic("Kernel requires i486+ for 'invlpg' and other features"); 2558 2559 init_utsname()->machine[1] = 2560 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2561 } 2562 2563 /* 2564 * Must be before alternatives because it might set or clear 2565 * feature bits. 2566 */ 2567 fpu__init_system(); 2568 fpu__init_cpu(); 2569 2570 /* 2571 * This needs to follow the FPU initializtion, since EFI depends on it. 2572 */ 2573 if (efi_enabled(EFI_RUNTIME_SERVICES)) 2574 efi_enter_virtual_mode(); 2575 2576 /* 2577 * Ensure that access to the per CPU representation has the initial 2578 * boot CPU configuration. 2579 */ 2580 *c = boot_cpu_data; 2581 c->initialized = true; 2582 2583 alternative_instructions(); 2584 2585 if (IS_ENABLED(CONFIG_X86_64)) { 2586 USER_PTR_MAX = TASK_SIZE_MAX; 2587 2588 /* 2589 * Enable this when LAM is gated on LASS support 2590 if (cpu_feature_enabled(X86_FEATURE_LAM)) 2591 USER_PTR_MAX = (1ul << 63) - PAGE_SIZE; 2592 */ 2593 runtime_const_init(ptr, USER_PTR_MAX); 2594 2595 /* 2596 * Make sure the first 2MB area is not mapped by huge pages 2597 * There are typically fixed size MTRRs in there and overlapping 2598 * MTRRs into large pages causes slow downs. 2599 * 2600 * Right now we don't do that with gbpages because there seems 2601 * very little benefit for that case. 2602 */ 2603 if (!direct_gbpages) 2604 set_memory_4k((unsigned long)__va(0), 1); 2605 } else { 2606 fpu__init_check_bugs(); 2607 } 2608 2609 /* 2610 * This needs to be called before any devices perform DMA 2611 * operations that might use the SWIOTLB bounce buffers. It will 2612 * mark the bounce buffers as decrypted so that their usage will 2613 * not cause "plain-text" data to be decrypted when accessed. It 2614 * must be called after late_time_init() so that Hyper-V x86/x64 2615 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2616 */ 2617 mem_encrypt_init(); 2618 } 2619