1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/kvm_types.h> 11 #include <linux/percpu.h> 12 #include <linux/string.h> 13 #include <linux/ctype.h> 14 #include <linux/delay.h> 15 #include <linux/sched/mm.h> 16 #include <linux/sched/clock.h> 17 #include <linux/sched/task.h> 18 #include <linux/sched/smt.h> 19 #include <linux/init.h> 20 #include <linux/kprobes.h> 21 #include <linux/kgdb.h> 22 #include <linux/mem_encrypt.h> 23 #include <linux/smp.h> 24 #include <linux/cpu.h> 25 #include <linux/io.h> 26 #include <linux/syscore_ops.h> 27 #include <linux/pgtable.h> 28 #include <linux/stackprotector.h> 29 #include <linux/utsname.h> 30 #include <linux/efi.h> 31 32 #include <asm/alternative.h> 33 #include <asm/cmdline.h> 34 #include <asm/cpuid/api.h> 35 #include <asm/perf_event.h> 36 #include <asm/mmu_context.h> 37 #include <asm/doublefault.h> 38 #include <asm/archrandom.h> 39 #include <asm/hypervisor.h> 40 #include <asm/processor.h> 41 #include <asm/tlbflush.h> 42 #include <asm/debugreg.h> 43 #include <asm/sections.h> 44 #include <asm/vsyscall.h> 45 #include <linux/topology.h> 46 #include <linux/cpumask.h> 47 #include <linux/atomic.h> 48 #include <asm/proto.h> 49 #include <asm/setup.h> 50 #include <asm/apic.h> 51 #include <asm/desc.h> 52 #include <asm/fpu/api.h> 53 #include <asm/mtrr.h> 54 #include <asm/hwcap2.h> 55 #include <linux/numa.h> 56 #include <asm/numa.h> 57 #include <asm/asm.h> 58 #include <asm/bugs.h> 59 #include <asm/cpu.h> 60 #include <asm/mce.h> 61 #include <asm/msr.h> 62 #include <asm/cacheinfo.h> 63 #include <asm/memtype.h> 64 #include <asm/microcode.h> 65 #include <asm/intel-family.h> 66 #include <asm/cpu_device_id.h> 67 #include <asm/fred.h> 68 #include <asm/uv/uv.h> 69 #include <asm/ia32.h> 70 #include <asm/set_memory.h> 71 #include <asm/traps.h> 72 #include <asm/sev.h> 73 #include <asm/tdx.h> 74 #include <asm/posted_intr.h> 75 #include <asm/runtime-const.h> 76 77 #include "cpu.h" 78 79 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 80 EXPORT_PER_CPU_SYMBOL(cpu_info); 81 82 u32 elf_hwcap2 __read_mostly; 83 84 /* Number of siblings per CPU package */ 85 unsigned int __max_threads_per_core __ro_after_init = 1; 86 EXPORT_SYMBOL(__max_threads_per_core); 87 88 unsigned int __max_dies_per_package __ro_after_init = 1; 89 EXPORT_SYMBOL(__max_dies_per_package); 90 91 unsigned int __max_logical_packages __ro_after_init = 1; 92 EXPORT_SYMBOL(__max_logical_packages); 93 94 unsigned int __num_cores_per_package __ro_after_init = 1; 95 EXPORT_SYMBOL(__num_cores_per_package); 96 97 unsigned int __num_threads_per_package __ro_after_init = 1; 98 EXPORT_SYMBOL(__num_threads_per_package); 99 100 static struct ppin_info { 101 int feature; 102 int msr_ppin_ctl; 103 int msr_ppin; 104 } ppin_info[] = { 105 [X86_VENDOR_INTEL] = { 106 .feature = X86_FEATURE_INTEL_PPIN, 107 .msr_ppin_ctl = MSR_PPIN_CTL, 108 .msr_ppin = MSR_PPIN 109 }, 110 [X86_VENDOR_AMD] = { 111 .feature = X86_FEATURE_AMD_PPIN, 112 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 113 .msr_ppin = MSR_AMD_PPIN 114 }, 115 }; 116 117 static const struct x86_cpu_id ppin_cpuids[] = { 118 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 119 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 120 121 /* Legacy models without CPUID enumeration */ 122 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 125 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 126 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 127 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 128 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 129 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 130 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 131 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 132 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 133 134 {} 135 }; 136 137 static void ppin_init(struct cpuinfo_x86 *c) 138 { 139 const struct x86_cpu_id *id; 140 unsigned long long val; 141 struct ppin_info *info; 142 143 id = x86_match_cpu(ppin_cpuids); 144 if (!id) 145 return; 146 147 /* 148 * Testing the presence of the MSR is not enough. Need to check 149 * that the PPIN_CTL allows reading of the PPIN. 150 */ 151 info = (struct ppin_info *)id->driver_data; 152 153 if (rdmsrq_safe(info->msr_ppin_ctl, &val)) 154 goto clear_ppin; 155 156 if ((val & 3UL) == 1UL) { 157 /* PPIN locked in disabled mode */ 158 goto clear_ppin; 159 } 160 161 /* If PPIN is disabled, try to enable */ 162 if (!(val & 2UL)) { 163 wrmsrq_safe(info->msr_ppin_ctl, val | 2UL); 164 rdmsrq_safe(info->msr_ppin_ctl, &val); 165 } 166 167 /* Is the enable bit set? */ 168 if (val & 2UL) { 169 c->ppin = native_rdmsrq(info->msr_ppin); 170 set_cpu_cap(c, info->feature); 171 return; 172 } 173 174 clear_ppin: 175 setup_clear_cpu_cap(info->feature); 176 } 177 178 static void default_init(struct cpuinfo_x86 *c) 179 { 180 #ifdef CONFIG_X86_64 181 cpu_detect_cache_sizes(c); 182 #else 183 /* Not much we can do here... */ 184 /* Check if at least it has cpuid */ 185 if (c->cpuid_level == -1) { 186 /* No cpuid. It must be an ancient CPU */ 187 if (c->x86 == 4) 188 strcpy(c->x86_model_id, "486"); 189 else if (c->x86 == 3) 190 strcpy(c->x86_model_id, "386"); 191 } 192 #endif 193 } 194 195 static const struct cpu_dev default_cpu = { 196 .c_init = default_init, 197 .c_vendor = "Unknown", 198 .c_x86_vendor = X86_VENDOR_UNKNOWN, 199 }; 200 201 static const struct cpu_dev *this_cpu = &default_cpu; 202 203 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 204 #ifdef CONFIG_X86_64 205 /* 206 * We need valid kernel segments for data and code in long mode too 207 * IRET will check the segment types kkeil 2000/10/28 208 * Also sysret mandates a special GDT layout 209 * 210 * TLS descriptors are currently at a different place compared to i386. 211 * Hopefully nobody expects them at a fixed place (Wine?) 212 */ 213 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 214 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 215 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff), 216 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 217 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff), 218 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff), 219 #else 220 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 221 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 222 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 223 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff), 224 /* 225 * Segments used for calling PnP BIOS have byte granularity. 226 * They code segments and data segments have fixed 64k limits, 227 * the transfer segment sizes are set at run time. 228 */ 229 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 230 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 231 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff), 232 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 233 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 234 /* 235 * The APM segments have byte granularity and their bases 236 * are set at run time. All have 64k limits. 237 */ 238 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 239 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 240 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff), 241 242 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 243 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 244 #endif 245 } }; 246 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 247 SYM_PIC_ALIAS(gdt_page); 248 249 #ifdef CONFIG_X86_64 250 static int __init x86_nopcid_setup(char *s) 251 { 252 /* nopcid doesn't accept parameters */ 253 if (s) 254 return -EINVAL; 255 256 /* do not emit a message if the feature is not present */ 257 if (!boot_cpu_has(X86_FEATURE_PCID)) 258 return 0; 259 260 setup_clear_cpu_cap(X86_FEATURE_PCID); 261 pr_info("nopcid: PCID feature disabled\n"); 262 return 0; 263 } 264 early_param("nopcid", x86_nopcid_setup); 265 #endif 266 267 static int __init x86_noinvpcid_setup(char *s) 268 { 269 /* noinvpcid doesn't accept parameters */ 270 if (s) 271 return -EINVAL; 272 273 /* do not emit a message if the feature is not present */ 274 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 275 return 0; 276 277 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 278 pr_info("noinvpcid: INVPCID feature disabled\n"); 279 return 0; 280 } 281 early_param("noinvpcid", x86_noinvpcid_setup); 282 283 /* Standard macro to see if a specific flag is changeable */ 284 static inline bool flag_is_changeable_p(unsigned long flag) 285 { 286 unsigned long f1, f2; 287 288 if (!IS_ENABLED(CONFIG_X86_32)) 289 return true; 290 291 /* 292 * Cyrix and IDT cpus allow disabling of CPUID 293 * so the code below may return different results 294 * when it is executed before and after enabling 295 * the CPUID. Add "volatile" to not allow gcc to 296 * optimize the subsequent calls to this function. 297 */ 298 asm volatile ("pushfl \n\t" 299 "pushfl \n\t" 300 "popl %0 \n\t" 301 "movl %0, %1 \n\t" 302 "xorl %2, %0 \n\t" 303 "pushl %0 \n\t" 304 "popfl \n\t" 305 "pushfl \n\t" 306 "popl %0 \n\t" 307 "popfl \n\t" 308 309 : "=&r" (f1), "=&r" (f2) 310 : "ir" (flag)); 311 312 return (f1 ^ f2) & flag; 313 } 314 315 #ifdef CONFIG_X86_32 316 static int cachesize_override = -1; 317 static int disable_x86_serial_nr = 1; 318 319 static int __init cachesize_setup(char *str) 320 { 321 get_option(&str, &cachesize_override); 322 return 1; 323 } 324 __setup("cachesize=", cachesize_setup); 325 326 /* Probe for the CPUID instruction */ 327 bool cpuid_feature(void) 328 { 329 return flag_is_changeable_p(X86_EFLAGS_ID); 330 } 331 332 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 333 { 334 unsigned long lo, hi; 335 336 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 337 return; 338 339 /* Disable processor serial number: */ 340 341 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 342 lo |= 0x200000; 343 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 344 345 pr_notice("CPU serial number disabled.\n"); 346 clear_cpu_cap(c, X86_FEATURE_PN); 347 348 /* Disabling the serial number may affect the cpuid level */ 349 c->cpuid_level = cpuid_eax(0); 350 } 351 352 static int __init x86_serial_nr_setup(char *s) 353 { 354 disable_x86_serial_nr = 0; 355 return 1; 356 } 357 __setup("serialnumber", x86_serial_nr_setup); 358 #else 359 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 360 { 361 } 362 #endif 363 364 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 365 { 366 if (cpu_has(c, X86_FEATURE_SMEP)) 367 cr4_set_bits(X86_CR4_SMEP); 368 } 369 370 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 371 { 372 unsigned long eflags = native_save_fl(); 373 374 /* This should have been cleared long ago */ 375 BUG_ON(eflags & X86_EFLAGS_AC); 376 377 if (cpu_has(c, X86_FEATURE_SMAP)) 378 cr4_set_bits(X86_CR4_SMAP); 379 } 380 381 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 382 { 383 /* Check the boot processor, plus build option for UMIP. */ 384 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 385 goto out; 386 387 /* Check the current processor's cpuid bits. */ 388 if (!cpu_has(c, X86_FEATURE_UMIP)) 389 goto out; 390 391 cr4_set_bits(X86_CR4_UMIP); 392 393 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 394 395 return; 396 397 out: 398 /* 399 * Make sure UMIP is disabled in case it was enabled in a 400 * previous boot (e.g., via kexec). 401 */ 402 cr4_clear_bits(X86_CR4_UMIP); 403 } 404 405 /* These bits should not change their value after CPU init is finished. */ 406 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 407 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; 408 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 409 static unsigned long cr4_pinned_bits __ro_after_init; 410 411 void native_write_cr0(unsigned long val) 412 { 413 unsigned long bits_missing = 0; 414 415 set_register: 416 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 417 418 if (static_branch_likely(&cr_pinning)) { 419 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 420 bits_missing = X86_CR0_WP; 421 val |= bits_missing; 422 goto set_register; 423 } 424 /* Warn after we've set the missing bits. */ 425 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 426 } 427 } 428 EXPORT_SYMBOL(native_write_cr0); 429 430 void __no_profile native_write_cr4(unsigned long val) 431 { 432 unsigned long bits_changed = 0; 433 434 set_register: 435 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 436 437 if (static_branch_likely(&cr_pinning)) { 438 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 439 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 440 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 441 goto set_register; 442 } 443 /* Warn after we've corrected the changed bits. */ 444 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 445 bits_changed); 446 } 447 } 448 #if IS_MODULE(CONFIG_LKDTM) 449 EXPORT_SYMBOL_GPL(native_write_cr4); 450 #endif 451 452 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 453 { 454 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 455 456 lockdep_assert_irqs_disabled(); 457 458 newval = (cr4 & ~clear) | set; 459 if (newval != cr4) { 460 this_cpu_write(cpu_tlbstate.cr4, newval); 461 __write_cr4(newval); 462 } 463 } 464 EXPORT_SYMBOL_FOR_KVM(cr4_update_irqsoff); 465 466 /* Read the CR4 shadow. */ 467 unsigned long cr4_read_shadow(void) 468 { 469 return this_cpu_read(cpu_tlbstate.cr4); 470 } 471 EXPORT_SYMBOL_FOR_KVM(cr4_read_shadow); 472 473 void cr4_init(void) 474 { 475 unsigned long cr4 = __read_cr4(); 476 477 if (boot_cpu_has(X86_FEATURE_PCID)) 478 cr4 |= X86_CR4_PCIDE; 479 if (static_branch_likely(&cr_pinning)) 480 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 481 482 __write_cr4(cr4); 483 484 /* Initialize cr4 shadow for this CPU. */ 485 this_cpu_write(cpu_tlbstate.cr4, cr4); 486 } 487 488 /* 489 * Once CPU feature detection is finished (and boot params have been 490 * parsed), record any of the sensitive CR bits that are set, and 491 * enable CR pinning. 492 */ 493 static void __init setup_cr_pinning(void) 494 { 495 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 496 static_key_enable(&cr_pinning.key); 497 } 498 499 static __init int x86_nofsgsbase_setup(char *arg) 500 { 501 /* Require an exact match without trailing characters. */ 502 if (strlen(arg)) 503 return 0; 504 505 /* Do not emit a message if the feature is not present. */ 506 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 507 return 1; 508 509 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 510 pr_info("FSGSBASE disabled via kernel command line\n"); 511 return 1; 512 } 513 __setup("nofsgsbase", x86_nofsgsbase_setup); 514 515 /* 516 * Protection Keys are not available in 32-bit mode. 517 */ 518 static bool pku_disabled; 519 520 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 521 { 522 if (c == &boot_cpu_data) { 523 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 524 return; 525 /* 526 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 527 * bit to be set. Enforce it. 528 */ 529 setup_force_cpu_cap(X86_FEATURE_OSPKE); 530 531 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 532 return; 533 } 534 535 cr4_set_bits(X86_CR4_PKE); 536 /* Load the default PKRU value */ 537 pkru_write_default(); 538 } 539 540 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 541 static __init int setup_disable_pku(char *arg) 542 { 543 /* 544 * Do not clear the X86_FEATURE_PKU bit. All of the 545 * runtime checks are against OSPKE so clearing the 546 * bit does nothing. 547 * 548 * This way, we will see "pku" in cpuinfo, but not 549 * "ospke", which is exactly what we want. It shows 550 * that the CPU has PKU, but the OS has not enabled it. 551 * This happens to be exactly how a system would look 552 * if we disabled the config option. 553 */ 554 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 555 pku_disabled = true; 556 return 1; 557 } 558 __setup("nopku", setup_disable_pku); 559 #endif 560 561 #ifdef CONFIG_X86_KERNEL_IBT 562 563 __noendbr u64 ibt_save(bool disable) 564 { 565 u64 msr = 0; 566 567 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 568 rdmsrq(MSR_IA32_S_CET, msr); 569 if (disable) 570 wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 571 } 572 573 return msr; 574 } 575 576 __noendbr void ibt_restore(u64 save) 577 { 578 u64 msr; 579 580 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 581 rdmsrq(MSR_IA32_S_CET, msr); 582 msr &= ~CET_ENDBR_EN; 583 msr |= (save & CET_ENDBR_EN); 584 wrmsrq(MSR_IA32_S_CET, msr); 585 } 586 } 587 588 #endif 589 590 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 591 { 592 bool user_shstk, kernel_ibt; 593 594 if (!IS_ENABLED(CONFIG_X86_CET)) 595 return; 596 597 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 598 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 599 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 600 601 if (!kernel_ibt && !user_shstk) 602 return; 603 604 if (user_shstk) 605 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 606 607 if (kernel_ibt) 608 wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN); 609 else 610 wrmsrq(MSR_IA32_S_CET, 0); 611 612 cr4_set_bits(X86_CR4_CET); 613 614 if (kernel_ibt && ibt_selftest()) { 615 pr_err("IBT selftest: Failed!\n"); 616 wrmsrq(MSR_IA32_S_CET, 0); 617 setup_clear_cpu_cap(X86_FEATURE_IBT); 618 } 619 } 620 621 __noendbr void cet_disable(void) 622 { 623 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 624 cpu_feature_enabled(X86_FEATURE_SHSTK))) 625 return; 626 627 wrmsrq(MSR_IA32_S_CET, 0); 628 wrmsrq(MSR_IA32_U_CET, 0); 629 } 630 631 /* 632 * Some CPU features depend on higher CPUID levels, which may not always 633 * be available due to CPUID level capping or broken virtualization 634 * software. Add those features to this table to auto-disable them. 635 */ 636 struct cpuid_dependent_feature { 637 u32 feature; 638 u32 level; 639 }; 640 641 static const struct cpuid_dependent_feature 642 cpuid_dependent_features[] = { 643 { X86_FEATURE_MWAIT, CPUID_LEAF_MWAIT }, 644 { X86_FEATURE_DCA, CPUID_LEAF_DCA }, 645 { X86_FEATURE_XSAVE, CPUID_LEAF_XSTATE }, 646 { 0, 0 } 647 }; 648 649 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 650 { 651 const struct cpuid_dependent_feature *df; 652 653 for (df = cpuid_dependent_features; df->feature; df++) { 654 655 if (!cpu_has(c, df->feature)) 656 continue; 657 /* 658 * Note: cpuid_level is set to -1 if unavailable, but 659 * extended_extended_level is set to 0 if unavailable 660 * and the legitimate extended levels are all negative 661 * when signed; hence the weird messing around with 662 * signs here... 663 */ 664 if (!((s32)df->level < 0 ? 665 (u32)df->level > (u32)c->extended_cpuid_level : 666 (s32)df->level > (s32)c->cpuid_level)) 667 continue; 668 669 clear_cpu_cap(c, df->feature); 670 if (!warn) 671 continue; 672 673 pr_warn("CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 674 x86_cap_flags[df->feature], df->level); 675 } 676 } 677 678 /* 679 * Naming convention should be: <Name> [(<Codename>)] 680 * This table only is used unless init_<vendor>() below doesn't set it; 681 * in particular, if CPUID levels 0x80000002..4 are supported, this 682 * isn't used 683 */ 684 685 /* Look up CPU names by table lookup. */ 686 static const char *table_lookup_model(struct cpuinfo_x86 *c) 687 { 688 #ifdef CONFIG_X86_32 689 const struct legacy_cpu_model_info *info; 690 691 if (c->x86_model >= 16) 692 return NULL; /* Range check */ 693 694 if (!this_cpu) 695 return NULL; 696 697 info = this_cpu->legacy_models; 698 699 while (info->family) { 700 if (info->family == c->x86) 701 return info->model_names[c->x86_model]; 702 info++; 703 } 704 #endif 705 return NULL; /* Not found */ 706 } 707 708 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 709 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 710 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 711 712 #ifdef CONFIG_X86_32 713 /* The 32-bit entry code needs to find cpu_entry_area. */ 714 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 715 #endif 716 717 /* Load the original GDT from the per-cpu structure */ 718 void load_direct_gdt(int cpu) 719 { 720 struct desc_ptr gdt_descr; 721 722 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 723 gdt_descr.size = GDT_SIZE - 1; 724 load_gdt(&gdt_descr); 725 } 726 EXPORT_SYMBOL_FOR_KVM(load_direct_gdt); 727 728 /* Load a fixmap remapping of the per-cpu GDT */ 729 void load_fixmap_gdt(int cpu) 730 { 731 struct desc_ptr gdt_descr; 732 733 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 734 gdt_descr.size = GDT_SIZE - 1; 735 load_gdt(&gdt_descr); 736 } 737 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 738 739 /** 740 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 741 * @cpu: The CPU number for which this is invoked 742 * 743 * Invoked during early boot to switch from early GDT and early per CPU to 744 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 745 * switch is implicit by loading the direct GDT. On 64bit this requires 746 * to update GSBASE. 747 */ 748 void __init switch_gdt_and_percpu_base(int cpu) 749 { 750 load_direct_gdt(cpu); 751 752 #ifdef CONFIG_X86_64 753 /* 754 * No need to load %gs. It is already correct. 755 * 756 * Writing %gs on 64bit would zero GSBASE which would make any per 757 * CPU operation up to the point of the wrmsrq() fault. 758 * 759 * Set GSBASE to the new offset. Until the wrmsrq() happens the 760 * early mapping is still valid. That means the GSBASE update will 761 * lose any prior per CPU data which was not copied over in 762 * setup_per_cpu_areas(). 763 * 764 * This works even with stackprotector enabled because the 765 * per CPU stack canary is 0 in both per CPU areas. 766 */ 767 wrmsrq(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 768 #else 769 /* 770 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 771 * it is required to load FS again so that the 'hidden' part is 772 * updated from the new GDT. Up to this point the early per CPU 773 * translation is active. Any content of the early per CPU data 774 * which was not copied over in setup_per_cpu_areas() is lost. 775 */ 776 loadsegment(fs, __KERNEL_PERCPU); 777 #endif 778 } 779 780 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 781 782 static void get_model_name(struct cpuinfo_x86 *c) 783 { 784 unsigned int *v; 785 char *p, *q, *s; 786 787 if (c->extended_cpuid_level < 0x80000004) 788 return; 789 790 v = (unsigned int *)c->x86_model_id; 791 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 792 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 793 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 794 c->x86_model_id[48] = 0; 795 796 /* Trim whitespace */ 797 p = q = s = &c->x86_model_id[0]; 798 799 while (*p == ' ') 800 p++; 801 802 while (*p) { 803 /* Note the last non-whitespace index */ 804 if (!isspace(*p)) 805 s = q; 806 807 *q++ = *p++; 808 } 809 810 *(s + 1) = '\0'; 811 } 812 813 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 814 { 815 unsigned int n, dummy, ebx, ecx, edx, l2size; 816 817 n = c->extended_cpuid_level; 818 819 if (n >= 0x80000005) { 820 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 821 c->x86_cache_size = (ecx>>24) + (edx>>24); 822 #ifdef CONFIG_X86_64 823 /* On K8 L1 TLB is inclusive, so don't count it */ 824 c->x86_tlbsize = 0; 825 #endif 826 } 827 828 if (n < 0x80000006) /* Some chips just has a large L1. */ 829 return; 830 831 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 832 l2size = ecx >> 16; 833 834 #ifdef CONFIG_X86_64 835 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 836 #else 837 /* do processor-specific cache resizing */ 838 if (this_cpu->legacy_cache_size) 839 l2size = this_cpu->legacy_cache_size(c, l2size); 840 841 /* Allow user to override all this if necessary. */ 842 if (cachesize_override != -1) 843 l2size = cachesize_override; 844 845 if (l2size == 0) 846 return; /* Again, no L2 cache is possible */ 847 #endif 848 849 c->x86_cache_size = l2size; 850 } 851 852 u16 __read_mostly tlb_lli_4k; 853 u16 __read_mostly tlb_lli_2m; 854 u16 __read_mostly tlb_lli_4m; 855 u16 __read_mostly tlb_lld_4k; 856 u16 __read_mostly tlb_lld_2m; 857 u16 __read_mostly tlb_lld_4m; 858 u16 __read_mostly tlb_lld_1g; 859 860 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 861 { 862 if (this_cpu->c_detect_tlb) 863 this_cpu->c_detect_tlb(c); 864 865 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 866 tlb_lli_4k, tlb_lli_2m, tlb_lli_4m); 867 868 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 869 tlb_lld_4k, tlb_lld_2m, tlb_lld_4m, tlb_lld_1g); 870 } 871 872 void get_cpu_vendor(struct cpuinfo_x86 *c) 873 { 874 char *v = c->x86_vendor_id; 875 int i; 876 877 for (i = 0; i < X86_VENDOR_NUM; i++) { 878 if (!cpu_devs[i]) 879 break; 880 881 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 882 (cpu_devs[i]->c_ident[1] && 883 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 884 885 this_cpu = cpu_devs[i]; 886 c->x86_vendor = this_cpu->c_x86_vendor; 887 return; 888 } 889 } 890 891 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 892 "CPU: Your system may be unstable.\n", v); 893 894 c->x86_vendor = X86_VENDOR_UNKNOWN; 895 this_cpu = &default_cpu; 896 } 897 898 void cpu_detect(struct cpuinfo_x86 *c) 899 { 900 /* Get vendor name */ 901 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 902 (unsigned int *)&c->x86_vendor_id[0], 903 (unsigned int *)&c->x86_vendor_id[8], 904 (unsigned int *)&c->x86_vendor_id[4]); 905 906 c->x86 = 4; 907 /* Intel-defined flags: level 0x00000001 */ 908 if (c->cpuid_level >= 0x00000001) { 909 u32 junk, tfms, cap0, misc; 910 911 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 912 c->x86 = x86_family(tfms); 913 c->x86_model = x86_model(tfms); 914 c->x86_stepping = x86_stepping(tfms); 915 916 if (cap0 & (1<<19)) { 917 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 918 c->x86_cache_alignment = c->x86_clflush_size; 919 } 920 } 921 } 922 923 static void apply_forced_caps(struct cpuinfo_x86 *c) 924 { 925 int i; 926 927 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 928 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 929 c->x86_capability[i] |= cpu_caps_set[i]; 930 } 931 } 932 933 static void init_speculation_control(struct cpuinfo_x86 *c) 934 { 935 /* 936 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 937 * and they also have a different bit for STIBP support. Also, 938 * a hypervisor might have set the individual AMD bits even on 939 * Intel CPUs, for finer-grained selection of what's available. 940 */ 941 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 942 set_cpu_cap(c, X86_FEATURE_IBRS); 943 set_cpu_cap(c, X86_FEATURE_IBPB); 944 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 945 } 946 947 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 948 set_cpu_cap(c, X86_FEATURE_STIBP); 949 950 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 951 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 952 set_cpu_cap(c, X86_FEATURE_SSBD); 953 954 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 955 set_cpu_cap(c, X86_FEATURE_IBRS); 956 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 957 } 958 959 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 960 set_cpu_cap(c, X86_FEATURE_IBPB); 961 962 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 963 set_cpu_cap(c, X86_FEATURE_STIBP); 964 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 965 } 966 967 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 968 set_cpu_cap(c, X86_FEATURE_SSBD); 969 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 970 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 971 } 972 } 973 974 void get_cpu_cap(struct cpuinfo_x86 *c) 975 { 976 u32 eax, ebx, ecx, edx; 977 978 /* Intel-defined flags: level 0x00000001 */ 979 if (c->cpuid_level >= 0x00000001) { 980 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 981 982 c->x86_capability[CPUID_1_ECX] = ecx; 983 c->x86_capability[CPUID_1_EDX] = edx; 984 } 985 986 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 987 if (c->cpuid_level >= 0x00000006) 988 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 989 990 /* Additional Intel-defined flags: level 0x00000007 */ 991 if (c->cpuid_level >= 0x00000007) { 992 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 993 c->x86_capability[CPUID_7_0_EBX] = ebx; 994 c->x86_capability[CPUID_7_ECX] = ecx; 995 c->x86_capability[CPUID_7_EDX] = edx; 996 997 /* Check valid sub-leaf index before accessing it */ 998 if (eax >= 1) { 999 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1000 c->x86_capability[CPUID_7_1_EAX] = eax; 1001 } 1002 } 1003 1004 /* Extended state features: level 0x0000000d */ 1005 if (c->cpuid_level >= 0x0000000d) { 1006 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1007 1008 c->x86_capability[CPUID_D_1_EAX] = eax; 1009 } 1010 1011 /* 1012 * Check if extended CPUID leaves are implemented: Max extended 1013 * CPUID leaf must be in the 0x80000001-0x8000ffff range. 1014 */ 1015 eax = cpuid_eax(0x80000000); 1016 c->extended_cpuid_level = ((eax & 0xffff0000) == 0x80000000) ? eax : 0; 1017 1018 if (c->extended_cpuid_level >= 0x80000001) { 1019 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1020 1021 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1022 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1023 } 1024 1025 if (c->extended_cpuid_level >= 0x80000007) { 1026 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1027 1028 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1029 c->x86_power = edx; 1030 } 1031 1032 if (c->extended_cpuid_level >= 0x80000008) { 1033 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1034 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1035 } 1036 1037 if (c->extended_cpuid_level >= 0x8000000a) 1038 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1039 1040 if (c->extended_cpuid_level >= 0x8000001f) 1041 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1042 1043 if (c->extended_cpuid_level >= 0x80000021) 1044 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1045 1046 init_scattered_cpuid_features(c); 1047 init_speculation_control(c); 1048 1049 /* 1050 * Clear/Set all flags overridden by options, after probe. 1051 * This needs to happen each time we re-probe, which may happen 1052 * several times during CPU initialization. 1053 */ 1054 apply_forced_caps(c); 1055 } 1056 1057 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1058 { 1059 u32 eax, ebx, ecx, edx; 1060 1061 if (!cpu_has(c, X86_FEATURE_CPUID) || 1062 (c->extended_cpuid_level < 0x80000008)) { 1063 if (IS_ENABLED(CONFIG_X86_64)) { 1064 c->x86_clflush_size = 64; 1065 c->x86_phys_bits = 36; 1066 c->x86_virt_bits = 48; 1067 } else { 1068 c->x86_clflush_size = 32; 1069 c->x86_virt_bits = 32; 1070 c->x86_phys_bits = 32; 1071 1072 if (cpu_has(c, X86_FEATURE_PAE) || 1073 cpu_has(c, X86_FEATURE_PSE36)) 1074 c->x86_phys_bits = 36; 1075 } 1076 } else { 1077 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1078 1079 c->x86_virt_bits = (eax >> 8) & 0xff; 1080 c->x86_phys_bits = eax & 0xff; 1081 1082 /* Provide a sane default if not enumerated: */ 1083 if (!c->x86_clflush_size) 1084 c->x86_clflush_size = 32; 1085 } 1086 1087 c->x86_cache_bits = c->x86_phys_bits; 1088 c->x86_cache_alignment = c->x86_clflush_size; 1089 } 1090 1091 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1092 { 1093 int i; 1094 1095 /* 1096 * First of all, decide if this is a 486 or higher 1097 * It's a 486 if we can modify the AC flag 1098 */ 1099 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1100 c->x86 = 4; 1101 else 1102 c->x86 = 3; 1103 1104 for (i = 0; i < X86_VENDOR_NUM; i++) 1105 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1106 c->x86_vendor_id[0] = 0; 1107 cpu_devs[i]->c_identify(c); 1108 if (c->x86_vendor_id[0]) { 1109 get_cpu_vendor(c); 1110 break; 1111 } 1112 } 1113 } 1114 1115 #define NO_SPECULATION BIT(0) 1116 #define NO_MELTDOWN BIT(1) 1117 #define NO_SSB BIT(2) 1118 #define NO_L1TF BIT(3) 1119 #define NO_MDS BIT(4) 1120 #define MSBDS_ONLY BIT(5) 1121 #define NO_SWAPGS BIT(6) 1122 #define NO_ITLB_MULTIHIT BIT(7) 1123 #define NO_SPECTRE_V2 BIT(8) 1124 #define NO_MMIO BIT(9) 1125 #define NO_EIBRS_PBRSB BIT(10) 1126 #define NO_BHI BIT(11) 1127 1128 #define VULNWL(vendor, family, model, whitelist) \ 1129 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1130 1131 #define VULNWL_INTEL(vfm, whitelist) \ 1132 X86_MATCH_VFM(vfm, whitelist) 1133 1134 #define VULNWL_AMD(family, whitelist) \ 1135 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1136 1137 #define VULNWL_HYGON(family, whitelist) \ 1138 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1139 1140 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1141 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1142 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1143 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1144 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1145 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1146 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1147 1148 /* Intel Family 6 */ 1149 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), 1150 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), 1151 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), 1152 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), 1153 1154 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1155 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1156 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1157 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1158 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1159 1160 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1161 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1162 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1163 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1164 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1165 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1166 1167 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), 1168 1169 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY), 1170 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1171 1172 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1173 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1174 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1175 1176 /* 1177 * Technically, swapgs isn't serializing on AMD (despite it previously 1178 * being documented as such in the APM). But according to AMD, %gs is 1179 * updated non-speculatively, and the issuing of %gs-relative memory 1180 * operands will be blocked until the %gs update completes, which is 1181 * good enough for our purposes. 1182 */ 1183 1184 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), 1185 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1186 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1187 1188 /* AMD Family 0xf - 0x12 */ 1189 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1190 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1191 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1192 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1193 1194 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1195 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1196 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1197 1198 /* Zhaoxin Family 7 */ 1199 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1200 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1201 {} 1202 }; 1203 1204 #define VULNBL(vendor, family, model, blacklist) \ 1205 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1206 1207 #define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \ 1208 X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues) 1209 1210 #define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \ 1211 X86_MATCH_VFM_CPU_TYPE(vfm, INTEL_CPU_TYPE_##cpu_type, issues) 1212 1213 #define VULNBL_AMD(family, blacklist) \ 1214 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1215 1216 #define VULNBL_HYGON(family, blacklist) \ 1217 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1218 1219 #define SRBDS BIT(0) 1220 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1221 #define MMIO BIT(1) 1222 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1223 #define MMIO_SBDS BIT(2) 1224 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1225 #define RETBLEED BIT(3) 1226 /* CPU is affected by SMT (cross-thread) return predictions */ 1227 #define SMT_RSB BIT(4) 1228 /* CPU is affected by SRSO */ 1229 #define SRSO BIT(5) 1230 /* CPU is affected by GDS */ 1231 #define GDS BIT(6) 1232 /* CPU is affected by Register File Data Sampling */ 1233 #define RFDS BIT(7) 1234 /* CPU is affected by Indirect Target Selection */ 1235 #define ITS BIT(8) 1236 /* CPU is affected by Indirect Target Selection, but guest-host isolation is not affected */ 1237 #define ITS_NATIVE_ONLY BIT(9) 1238 /* CPU is affected by Transient Scheduler Attacks */ 1239 #define TSA BIT(10) 1240 /* CPU is affected by VMSCAPE */ 1241 #define VMSCAPE BIT(11) 1242 1243 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1244 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE_X, X86_STEP_MAX, VMSCAPE), 1245 VULNBL_INTEL_STEPS(INTEL_SANDYBRIDGE, X86_STEP_MAX, VMSCAPE), 1246 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE_X, X86_STEP_MAX, VMSCAPE), 1247 VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS | VMSCAPE), 1248 VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS | VMSCAPE), 1249 VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS | VMSCAPE), 1250 VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE), 1251 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO | VMSCAPE), 1252 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO | VMSCAPE), 1253 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO | VMSCAPE), 1254 VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS | VMSCAPE), 1255 VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS | VMSCAPE), 1256 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, 0x5, MMIO | RETBLEED | GDS | VMSCAPE), 1257 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | VMSCAPE), 1258 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1259 VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1260 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, 0xb, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1261 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE), 1262 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, 0xc, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE), 1263 VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSCAPE), 1264 VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED | VMSCAPE), 1265 VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1266 VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1267 VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS | ITS | ITS_NATIVE_ONLY), 1268 VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE), 1269 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED | ITS | VMSCAPE), 1270 VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED | GDS | ITS | VMSCAPE), 1271 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1272 VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS | ITS | ITS_NATIVE_ONLY), 1273 VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS | RETBLEED), 1274 VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | ITS_NATIVE_ONLY), 1275 VULNBL_INTEL_TYPE(INTEL_ALDERLAKE, ATOM, RFDS | VMSCAPE), 1276 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE, X86_STEP_MAX, VMSCAPE), 1277 VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS | VMSCAPE), 1278 VULNBL_INTEL_TYPE(INTEL_RAPTORLAKE, ATOM, RFDS | VMSCAPE), 1279 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE, X86_STEP_MAX, VMSCAPE), 1280 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS | VMSCAPE), 1281 VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS | VMSCAPE), 1282 VULNBL_INTEL_STEPS(INTEL_METEORLAKE_L, X86_STEP_MAX, VMSCAPE), 1283 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_H, X86_STEP_MAX, VMSCAPE), 1284 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE, X86_STEP_MAX, VMSCAPE), 1285 VULNBL_INTEL_STEPS(INTEL_ARROWLAKE_U, X86_STEP_MAX, VMSCAPE), 1286 VULNBL_INTEL_STEPS(INTEL_LUNARLAKE_M, X86_STEP_MAX, VMSCAPE), 1287 VULNBL_INTEL_STEPS(INTEL_SAPPHIRERAPIDS_X, X86_STEP_MAX, VMSCAPE), 1288 VULNBL_INTEL_STEPS(INTEL_GRANITERAPIDS_X, X86_STEP_MAX, VMSCAPE), 1289 VULNBL_INTEL_STEPS(INTEL_EMERALDRAPIDS_X, X86_STEP_MAX, VMSCAPE), 1290 VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS | VMSCAPE), 1291 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1292 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS), 1293 VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SBDS | RFDS), 1294 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS), 1295 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS), 1296 VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS), 1297 VULNBL_INTEL_STEPS(INTEL_ATOM_CRESTMONT_X, X86_STEP_MAX, VMSCAPE), 1298 1299 VULNBL_AMD(0x15, RETBLEED), 1300 VULNBL_AMD(0x16, RETBLEED), 1301 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO | VMSCAPE), 1302 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO | VMSCAPE), 1303 VULNBL_AMD(0x19, SRSO | TSA | VMSCAPE), 1304 VULNBL_AMD(0x1a, SRSO | VMSCAPE), 1305 {} 1306 }; 1307 1308 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1309 { 1310 const struct x86_cpu_id *m = x86_match_cpu(table); 1311 1312 return m && !!(m->driver_data & which); 1313 } 1314 1315 u64 x86_read_arch_cap_msr(void) 1316 { 1317 u64 x86_arch_cap_msr = 0; 1318 1319 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1320 rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1321 1322 return x86_arch_cap_msr; 1323 } 1324 1325 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr) 1326 { 1327 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO && 1328 x86_arch_cap_msr & ARCH_CAP_PSDP_NO && 1329 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO); 1330 } 1331 1332 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr) 1333 { 1334 /* The "immunity" bit trumps everything else: */ 1335 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO) 1336 return false; 1337 1338 /* 1339 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to 1340 * indicate that mitigation is needed because guest is running on a 1341 * vulnerable hardware or may migrate to such hardware: 1342 */ 1343 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 1344 return true; 1345 1346 /* Only consult the blacklist when there is no enumeration: */ 1347 return cpu_matches(cpu_vuln_blacklist, RFDS); 1348 } 1349 1350 static bool __init vulnerable_to_its(u64 x86_arch_cap_msr) 1351 { 1352 /* The "immunity" bit trumps everything else: */ 1353 if (x86_arch_cap_msr & ARCH_CAP_ITS_NO) 1354 return false; 1355 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 1356 return false; 1357 1358 /* None of the affected CPUs have BHI_CTRL */ 1359 if (boot_cpu_has(X86_FEATURE_BHI_CTRL)) 1360 return false; 1361 1362 /* 1363 * If a VMM did not expose ITS_NO, assume that a guest could 1364 * be running on a vulnerable hardware or may migrate to such 1365 * hardware. 1366 */ 1367 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1368 return true; 1369 1370 if (cpu_matches(cpu_vuln_blacklist, ITS)) 1371 return true; 1372 1373 return false; 1374 } 1375 1376 static struct x86_cpu_id cpu_latest_microcode[] = { 1377 #include "microcode/intel-ucode-defs.h" 1378 {} 1379 }; 1380 1381 static bool __init cpu_has_old_microcode(void) 1382 { 1383 const struct x86_cpu_id *m = x86_match_cpu(cpu_latest_microcode); 1384 1385 /* Give unknown CPUs a pass: */ 1386 if (!m) { 1387 /* Intel CPUs should be in the list. Warn if not: */ 1388 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 1389 pr_info("x86/CPU: Model not found in latest microcode list\n"); 1390 return false; 1391 } 1392 1393 /* 1394 * Hosts usually lie to guests with a super high microcode 1395 * version. Just ignore what hosts tell guests: 1396 */ 1397 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1398 return false; 1399 1400 /* Consider all debug microcode to be old: */ 1401 if (boot_cpu_data.microcode & BIT(31)) 1402 return true; 1403 1404 /* Give new microcode a pass: */ 1405 if (boot_cpu_data.microcode >= m->driver_data) 1406 return false; 1407 1408 /* Uh oh, too old: */ 1409 return true; 1410 } 1411 1412 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1413 { 1414 u64 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1415 1416 if (cpu_has_old_microcode()) { 1417 pr_warn("x86/CPU: Running old microcode\n"); 1418 setup_force_cpu_bug(X86_BUG_OLD_MICROCODE); 1419 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1420 } 1421 1422 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1423 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1424 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO)) 1425 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1426 1427 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1428 return; 1429 1430 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1431 1432 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) { 1433 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1434 setup_force_cpu_bug(X86_BUG_SPECTRE_V2_USER); 1435 } 1436 1437 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1438 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) && 1439 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1440 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1441 1442 /* 1443 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1444 * flag and protect from vendor-specific bugs via the whitelist. 1445 * 1446 * Don't use AutoIBRS when SNP is enabled because it degrades host 1447 * userspace indirect branch performance. 1448 */ 1449 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || 1450 (cpu_has(c, X86_FEATURE_AUTOIBRS) && 1451 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { 1452 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1453 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1454 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO)) 1455 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1456 } 1457 1458 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1459 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) { 1460 setup_force_cpu_bug(X86_BUG_MDS); 1461 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1462 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1463 } 1464 1465 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1466 setup_force_cpu_bug(X86_BUG_SWAPGS); 1467 1468 /* 1469 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1470 * - TSX is supported or 1471 * - TSX_CTRL is present 1472 * 1473 * TSX_CTRL check is needed for cases when TSX could be disabled before 1474 * the kernel boot e.g. kexec. 1475 * TSX_CTRL check alone is not sufficient for cases when the microcode 1476 * update is not present or running as guest that don't get TSX_CTRL. 1477 */ 1478 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) && 1479 (cpu_has(c, X86_FEATURE_RTM) || 1480 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))) 1481 setup_force_cpu_bug(X86_BUG_TAA); 1482 1483 /* 1484 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1485 * in the vulnerability blacklist. 1486 * 1487 * Some of the implications and mitigation of Shared Buffers Data 1488 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1489 * SRBDS. 1490 */ 1491 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1492 cpu_has(c, X86_FEATURE_RDSEED)) && 1493 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1494 setup_force_cpu_bug(X86_BUG_SRBDS); 1495 1496 /* 1497 * Processor MMIO Stale Data bug enumeration 1498 * 1499 * Affected CPU list is generally enough to enumerate the vulnerability, 1500 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1501 * not want the guest to enumerate the bug. 1502 */ 1503 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { 1504 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1505 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1506 } 1507 1508 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1509 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA)) 1510 setup_force_cpu_bug(X86_BUG_RETBLEED); 1511 } 1512 1513 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1514 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1515 1516 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1517 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1518 setup_force_cpu_bug(X86_BUG_SRSO); 1519 } 1520 1521 /* 1522 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1523 * an affected processor, the VMM may have disabled the use of GATHER by 1524 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1525 * which means that AVX will be disabled. 1526 */ 1527 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) && 1528 boot_cpu_has(X86_FEATURE_AVX)) 1529 setup_force_cpu_bug(X86_BUG_GDS); 1530 1531 if (vulnerable_to_rfds(x86_arch_cap_msr)) 1532 setup_force_cpu_bug(X86_BUG_RFDS); 1533 1534 /* 1535 * Intel parts with eIBRS are vulnerable to BHI attacks. Parts with 1536 * BHI_NO still need to use the BHI mitigation to prevent Intra-mode 1537 * attacks. When virtualized, eIBRS could be hidden, assume vulnerable. 1538 */ 1539 if (!cpu_matches(cpu_vuln_whitelist, NO_BHI) && 1540 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) || 1541 boot_cpu_has(X86_FEATURE_HYPERVISOR))) 1542 setup_force_cpu_bug(X86_BUG_BHI); 1543 1544 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET)) 1545 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET); 1546 1547 if (vulnerable_to_its(x86_arch_cap_msr)) { 1548 setup_force_cpu_bug(X86_BUG_ITS); 1549 if (cpu_matches(cpu_vuln_blacklist, ITS_NATIVE_ONLY)) 1550 setup_force_cpu_bug(X86_BUG_ITS_NATIVE_ONLY); 1551 } 1552 1553 if (c->x86_vendor == X86_VENDOR_AMD) { 1554 if (!cpu_has(c, X86_FEATURE_TSA_SQ_NO) || 1555 !cpu_has(c, X86_FEATURE_TSA_L1_NO)) { 1556 if (cpu_matches(cpu_vuln_blacklist, TSA) || 1557 /* Enable bug on Zen guests to allow for live migration. */ 1558 (cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_ZEN))) 1559 setup_force_cpu_bug(X86_BUG_TSA); 1560 } 1561 } 1562 1563 /* 1564 * Set the bug only on bare-metal. A nested hypervisor should already be 1565 * deploying IBPB to isolate itself from nested guests. 1566 */ 1567 if (cpu_matches(cpu_vuln_blacklist, VMSCAPE) && 1568 !boot_cpu_has(X86_FEATURE_HYPERVISOR)) 1569 setup_force_cpu_bug(X86_BUG_VMSCAPE); 1570 1571 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1572 return; 1573 1574 /* Rogue Data Cache Load? No! */ 1575 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO) 1576 return; 1577 1578 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1579 1580 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1581 return; 1582 1583 setup_force_cpu_bug(X86_BUG_L1TF); 1584 } 1585 1586 /* 1587 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1588 * unfortunately, that's not true in practice because of early VIA 1589 * chips and (more importantly) broken virtualizers that are not easy 1590 * to detect. In the latter case it doesn't even *fail* reliably, so 1591 * probing for it doesn't even work. Disable it completely on 32-bit 1592 * unless we can find a reliable way to detect all the broken cases. 1593 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1594 */ 1595 static void detect_nopl(void) 1596 { 1597 #ifdef CONFIG_X86_32 1598 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1599 #else 1600 setup_force_cpu_cap(X86_FEATURE_NOPL); 1601 #endif 1602 } 1603 1604 static inline bool parse_set_clear_cpuid(char *arg, bool set) 1605 { 1606 char *opt; 1607 int taint = 0; 1608 1609 while (arg) { 1610 bool found __maybe_unused = false; 1611 unsigned int bit; 1612 1613 opt = strsep(&arg, ","); 1614 1615 /* 1616 * Handle naked numbers first for feature flags which don't 1617 * have names. It doesn't make sense for a bug not to have a 1618 * name so don't handle bug flags here. 1619 */ 1620 if (!kstrtouint(opt, 10, &bit)) { 1621 if (bit < NCAPINTS * 32) { 1622 1623 if (set) { 1624 pr_warn("setcpuid: force-enabling CPU feature flag:"); 1625 setup_force_cpu_cap(bit); 1626 } else { 1627 pr_warn("clearcpuid: force-disabling CPU feature flag:"); 1628 setup_clear_cpu_cap(bit); 1629 } 1630 /* empty-string, i.e., ""-defined feature flags */ 1631 if (!x86_cap_flags[bit]) 1632 pr_cont(" %d:%d\n", bit >> 5, bit & 31); 1633 else 1634 pr_cont(" %s\n", x86_cap_flags[bit]); 1635 1636 taint++; 1637 } 1638 /* 1639 * The assumption is that there are no feature names with only 1640 * numbers in the name thus go to the next argument. 1641 */ 1642 continue; 1643 } 1644 1645 for (bit = 0; bit < 32 * (NCAPINTS + NBUGINTS); bit++) { 1646 const char *flag; 1647 const char *kind; 1648 1649 if (bit < 32 * NCAPINTS) { 1650 flag = x86_cap_flags[bit]; 1651 kind = "feature"; 1652 } else { 1653 kind = "bug"; 1654 flag = x86_bug_flags[bit - (32 * NCAPINTS)]; 1655 } 1656 1657 if (!flag) 1658 continue; 1659 1660 if (strcmp(flag, opt)) 1661 continue; 1662 1663 if (set) { 1664 pr_warn("setcpuid: force-enabling CPU %s flag: %s\n", 1665 kind, flag); 1666 setup_force_cpu_cap(bit); 1667 } else { 1668 pr_warn("clearcpuid: force-disabling CPU %s flag: %s\n", 1669 kind, flag); 1670 setup_clear_cpu_cap(bit); 1671 } 1672 taint++; 1673 found = true; 1674 break; 1675 } 1676 1677 if (!found) 1678 pr_warn("%s: unknown CPU flag: %s", set ? "setcpuid" : "clearcpuid", opt); 1679 } 1680 1681 return taint; 1682 } 1683 1684 1685 /* 1686 * We parse cpu parameters early because fpu__init_system() is executed 1687 * before parse_early_param(). 1688 */ 1689 static void __init cpu_parse_early_param(void) 1690 { 1691 bool cpuid_taint = false; 1692 char arg[128]; 1693 int arglen; 1694 1695 #ifdef CONFIG_X86_32 1696 if (cmdline_find_option_bool(boot_command_line, "no387")) 1697 #ifdef CONFIG_MATH_EMULATION 1698 setup_clear_cpu_cap(X86_FEATURE_FPU); 1699 #else 1700 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1701 #endif 1702 1703 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1704 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1705 #endif 1706 1707 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1708 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1709 1710 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1711 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1712 1713 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1714 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1715 1716 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1717 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1718 1719 /* Minimize the gap between FRED is available and available but disabled. */ 1720 arglen = cmdline_find_option(boot_command_line, "fred", arg, sizeof(arg)); 1721 if (arglen != 2 || strncmp(arg, "on", 2)) 1722 setup_clear_cpu_cap(X86_FEATURE_FRED); 1723 1724 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1725 if (arglen > 0) 1726 cpuid_taint |= parse_set_clear_cpuid(arg, false); 1727 1728 arglen = cmdline_find_option(boot_command_line, "setcpuid", arg, sizeof(arg)); 1729 if (arglen > 0) 1730 cpuid_taint |= parse_set_clear_cpuid(arg, true); 1731 1732 if (cpuid_taint) { 1733 pr_warn("!!! setcpuid=/clearcpuid= in use, this is for TESTING ONLY, may break things horribly. Tainting kernel.\n"); 1734 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1735 } 1736 } 1737 1738 /* 1739 * Do minimum CPU detection early. 1740 * Fields really needed: vendor, cpuid_level, family, model, mask, 1741 * cache alignment. 1742 * The others are not touched to avoid unwanted side effects. 1743 * 1744 * WARNING: this function is only called on the boot CPU. Don't add code 1745 * here that is supposed to run on all CPUs. 1746 */ 1747 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1748 { 1749 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1750 c->extended_cpuid_level = 0; 1751 1752 if (!cpuid_feature()) 1753 identify_cpu_without_cpuid(c); 1754 1755 /* cyrix could have cpuid enabled via c_identify()*/ 1756 if (cpuid_feature()) { 1757 cpu_detect(c); 1758 get_cpu_vendor(c); 1759 intel_unlock_cpuid_leafs(c); 1760 get_cpu_cap(c); 1761 setup_force_cpu_cap(X86_FEATURE_CPUID); 1762 get_cpu_address_sizes(c); 1763 cpu_parse_early_param(); 1764 1765 cpu_init_topology(c); 1766 1767 if (this_cpu->c_early_init) 1768 this_cpu->c_early_init(c); 1769 1770 c->cpu_index = 0; 1771 filter_cpuid_features(c, false); 1772 check_cpufeature_deps(c); 1773 1774 if (this_cpu->c_bsp_init) 1775 this_cpu->c_bsp_init(c); 1776 } else { 1777 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1778 get_cpu_address_sizes(c); 1779 cpu_init_topology(c); 1780 } 1781 1782 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1783 1784 cpu_set_bug_bits(c); 1785 1786 sld_setup(c); 1787 1788 #ifdef CONFIG_X86_32 1789 /* 1790 * Regardless of whether PCID is enumerated, the SDM says 1791 * that it can't be enabled in 32-bit mode. 1792 */ 1793 setup_clear_cpu_cap(X86_FEATURE_PCID); 1794 #endif 1795 1796 /* 1797 * Later in the boot process pgtable_l5_enabled() relies on 1798 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1799 * enabled by this point we need to clear the feature bit to avoid 1800 * false-positives at the later stage. 1801 * 1802 * pgtable_l5_enabled() can be false here for several reasons: 1803 * - 5-level paging is disabled compile-time; 1804 * - it's 32-bit kernel; 1805 * - machine doesn't support 5-level paging; 1806 * - user specified 'no5lvl' in kernel command line. 1807 */ 1808 if (!pgtable_l5_enabled()) 1809 setup_clear_cpu_cap(X86_FEATURE_LA57); 1810 1811 detect_nopl(); 1812 mca_bsp_init(c); 1813 } 1814 1815 void __init init_cpu_devs(void) 1816 { 1817 const struct cpu_dev *const *cdev; 1818 int count = 0; 1819 1820 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1821 const struct cpu_dev *cpudev = *cdev; 1822 1823 if (count >= X86_VENDOR_NUM) 1824 break; 1825 cpu_devs[count] = cpudev; 1826 count++; 1827 } 1828 } 1829 1830 void __init early_cpu_init(void) 1831 { 1832 #ifdef CONFIG_PROCESSOR_SELECT 1833 unsigned int i, j; 1834 1835 pr_info("KERNEL supported cpus:\n"); 1836 #endif 1837 1838 init_cpu_devs(); 1839 1840 #ifdef CONFIG_PROCESSOR_SELECT 1841 for (i = 0; i < X86_VENDOR_NUM && cpu_devs[i]; i++) { 1842 for (j = 0; j < 2; j++) { 1843 if (!cpu_devs[i]->c_ident[j]) 1844 continue; 1845 pr_info(" %s %s\n", cpu_devs[i]->c_vendor, 1846 cpu_devs[i]->c_ident[j]); 1847 } 1848 } 1849 #endif 1850 1851 early_identify_cpu(&boot_cpu_data); 1852 } 1853 1854 static bool detect_null_seg_behavior(void) 1855 { 1856 /* 1857 * Empirically, writing zero to a segment selector on AMD does 1858 * not clear the base, whereas writing zero to a segment 1859 * selector on Intel does clear the base. Intel's behavior 1860 * allows slightly faster context switches in the common case 1861 * where GS is unused by the prev and next threads. 1862 * 1863 * Since neither vendor documents this anywhere that I can see, 1864 * detect it directly instead of hard-coding the choice by 1865 * vendor. 1866 * 1867 * I've designated AMD's behavior as the "bug" because it's 1868 * counterintuitive and less friendly. 1869 */ 1870 1871 unsigned long old_base, tmp; 1872 rdmsrq(MSR_FS_BASE, old_base); 1873 wrmsrq(MSR_FS_BASE, 1); 1874 loadsegment(fs, 0); 1875 rdmsrq(MSR_FS_BASE, tmp); 1876 wrmsrq(MSR_FS_BASE, old_base); 1877 return tmp == 0; 1878 } 1879 1880 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1881 { 1882 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1883 if (!IS_ENABLED(CONFIG_X86_64)) 1884 return; 1885 1886 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1887 return; 1888 1889 /* 1890 * CPUID bit above wasn't set. If this kernel is still running 1891 * as a HV guest, then the HV has decided not to advertize 1892 * that CPUID bit for whatever reason. For example, one 1893 * member of the migration pool might be vulnerable. Which 1894 * means, the bug is present: set the BUG flag and return. 1895 */ 1896 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1897 set_cpu_bug(c, X86_BUG_NULL_SEG); 1898 return; 1899 } 1900 1901 /* 1902 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1903 * 0x18 is the respective family for Hygon. 1904 */ 1905 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1906 detect_null_seg_behavior()) 1907 return; 1908 1909 /* All the remaining ones are affected */ 1910 set_cpu_bug(c, X86_BUG_NULL_SEG); 1911 } 1912 1913 static void generic_identify(struct cpuinfo_x86 *c) 1914 { 1915 c->extended_cpuid_level = 0; 1916 1917 if (!cpuid_feature()) 1918 identify_cpu_without_cpuid(c); 1919 1920 /* cyrix could have cpuid enabled via c_identify()*/ 1921 if (!cpuid_feature()) 1922 return; 1923 1924 cpu_detect(c); 1925 1926 get_cpu_vendor(c); 1927 intel_unlock_cpuid_leafs(c); 1928 get_cpu_cap(c); 1929 1930 get_cpu_address_sizes(c); 1931 1932 get_model_name(c); /* Default name */ 1933 1934 /* 1935 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1936 * systems that run Linux at CPL > 0 may or may not have the 1937 * issue, but, even if they have the issue, there's absolutely 1938 * nothing we can do about it because we can't use the real IRET 1939 * instruction. 1940 * 1941 * NB: For the time being, only 32-bit kernels support 1942 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1943 * whether to apply espfix using paravirt hooks. If any 1944 * non-paravirt system ever shows up that does *not* have the 1945 * ESPFIX issue, we can change this. 1946 */ 1947 #ifdef CONFIG_X86_32 1948 set_cpu_bug(c, X86_BUG_ESPFIX); 1949 #endif 1950 } 1951 1952 /* 1953 * This does the hard work of actually picking apart the CPU stuff... 1954 */ 1955 static void identify_cpu(struct cpuinfo_x86 *c) 1956 { 1957 int i; 1958 1959 c->loops_per_jiffy = loops_per_jiffy; 1960 c->x86_cache_size = 0; 1961 c->x86_vendor = X86_VENDOR_UNKNOWN; 1962 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1963 c->x86_vendor_id[0] = '\0'; /* Unset */ 1964 c->x86_model_id[0] = '\0'; /* Unset */ 1965 #ifdef CONFIG_X86_64 1966 c->x86_clflush_size = 64; 1967 c->x86_phys_bits = 36; 1968 c->x86_virt_bits = 48; 1969 #else 1970 c->cpuid_level = -1; /* CPUID not detected */ 1971 c->x86_clflush_size = 32; 1972 c->x86_phys_bits = 32; 1973 c->x86_virt_bits = 32; 1974 #endif 1975 c->x86_cache_alignment = c->x86_clflush_size; 1976 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1977 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1978 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1979 #endif 1980 1981 generic_identify(c); 1982 1983 cpu_parse_topology(c); 1984 1985 if (this_cpu->c_identify) 1986 this_cpu->c_identify(c); 1987 1988 /* Clear/Set all flags overridden by options, after probe */ 1989 apply_forced_caps(c); 1990 1991 /* 1992 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 1993 * Hygon will clear it in ->c_init() below. 1994 */ 1995 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1996 1997 /* 1998 * Vendor-specific initialization. In this section we 1999 * canonicalize the feature flags, meaning if there are 2000 * features a certain CPU supports which CPUID doesn't 2001 * tell us, CPUID claiming incorrect flags, or other bugs, 2002 * we handle them here. 2003 * 2004 * At the end of this section, c->x86_capability better 2005 * indicate the features this CPU genuinely supports! 2006 */ 2007 if (this_cpu->c_init) 2008 this_cpu->c_init(c); 2009 2010 bus_lock_init(); 2011 2012 /* Disable the PN if appropriate */ 2013 squash_the_stupid_serial_number(c); 2014 2015 /* Set up SMEP/SMAP/UMIP */ 2016 setup_smep(c); 2017 setup_smap(c); 2018 setup_umip(c); 2019 2020 /* Enable FSGSBASE instructions if available. */ 2021 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 2022 cr4_set_bits(X86_CR4_FSGSBASE); 2023 elf_hwcap2 |= HWCAP2_FSGSBASE; 2024 } 2025 2026 /* 2027 * The vendor-specific functions might have changed features. 2028 * Now we do "generic changes." 2029 */ 2030 2031 /* Filter out anything that depends on CPUID levels we don't have */ 2032 filter_cpuid_features(c, true); 2033 2034 /* Check for unmet dependencies based on the CPUID dependency table */ 2035 check_cpufeature_deps(c); 2036 2037 /* If the model name is still unset, do table lookup. */ 2038 if (!c->x86_model_id[0]) { 2039 const char *p; 2040 p = table_lookup_model(c); 2041 if (p) 2042 strcpy(c->x86_model_id, p); 2043 else 2044 /* Last resort... */ 2045 sprintf(c->x86_model_id, "%02x/%02x", 2046 c->x86, c->x86_model); 2047 } 2048 2049 x86_init_rdrand(c); 2050 setup_pku(c); 2051 setup_cet(c); 2052 2053 /* 2054 * Clear/Set all flags overridden by options, need do it 2055 * before following smp all cpus cap AND. 2056 */ 2057 apply_forced_caps(c); 2058 2059 /* 2060 * On SMP, boot_cpu_data holds the common feature set between 2061 * all CPUs; so make sure that we indicate which features are 2062 * common between the CPUs. The first time this routine gets 2063 * executed, c == &boot_cpu_data. 2064 */ 2065 if (c != &boot_cpu_data) { 2066 /* AND the already accumulated flags with these */ 2067 for (i = 0; i < NCAPINTS; i++) 2068 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 2069 2070 /* OR, i.e. replicate the bug flags */ 2071 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 2072 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 2073 } 2074 2075 ppin_init(c); 2076 2077 /* Init Machine Check Exception if available. */ 2078 mcheck_cpu_init(c); 2079 2080 numa_add_cpu(smp_processor_id()); 2081 } 2082 2083 /* 2084 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 2085 * on 32-bit kernels: 2086 */ 2087 #ifdef CONFIG_X86_32 2088 void enable_sep_cpu(void) 2089 { 2090 struct tss_struct *tss; 2091 int cpu; 2092 2093 if (!boot_cpu_has(X86_FEATURE_SEP)) 2094 return; 2095 2096 cpu = get_cpu(); 2097 tss = &per_cpu(cpu_tss_rw, cpu); 2098 2099 /* 2100 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 2101 * see the big comment in struct x86_hw_tss's definition. 2102 */ 2103 2104 tss->x86_tss.ss1 = __KERNEL_CS; 2105 wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1); 2106 wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 2107 wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32); 2108 2109 put_cpu(); 2110 } 2111 #endif 2112 2113 static __init void identify_boot_cpu(void) 2114 { 2115 identify_cpu(&boot_cpu_data); 2116 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 2117 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 2118 #ifdef CONFIG_X86_32 2119 enable_sep_cpu(); 2120 #endif 2121 cpu_detect_tlb(&boot_cpu_data); 2122 setup_cr_pinning(); 2123 2124 tsx_init(); 2125 tdx_init(); 2126 lkgs_init(); 2127 } 2128 2129 void identify_secondary_cpu(unsigned int cpu) 2130 { 2131 struct cpuinfo_x86 *c = &cpu_data(cpu); 2132 2133 /* Copy boot_cpu_data only on the first bringup */ 2134 if (!c->initialized) 2135 *c = boot_cpu_data; 2136 c->cpu_index = cpu; 2137 2138 identify_cpu(c); 2139 #ifdef CONFIG_X86_32 2140 enable_sep_cpu(); 2141 #endif 2142 x86_spec_ctrl_setup_ap(); 2143 update_srbds_msr(); 2144 if (boot_cpu_has_bug(X86_BUG_GDS)) 2145 update_gds_msr(); 2146 2147 tsx_ap_init(); 2148 c->initialized = true; 2149 } 2150 2151 void print_cpu_info(struct cpuinfo_x86 *c) 2152 { 2153 const char *vendor = NULL; 2154 2155 if (c->x86_vendor < X86_VENDOR_NUM) { 2156 vendor = this_cpu->c_vendor; 2157 } else { 2158 if (c->cpuid_level >= 0) 2159 vendor = c->x86_vendor_id; 2160 } 2161 2162 if (vendor && !strstr(c->x86_model_id, vendor)) 2163 pr_cont("%s ", vendor); 2164 2165 if (c->x86_model_id[0]) 2166 pr_cont("%s", c->x86_model_id); 2167 else 2168 pr_cont("%d86", c->x86); 2169 2170 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2171 2172 if (c->x86_stepping || c->cpuid_level >= 0) 2173 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2174 else 2175 pr_cont(")\n"); 2176 } 2177 2178 /* 2179 * clearcpuid= and setcpuid= were already parsed in cpu_parse_early_param(). 2180 * These dummy functions prevent them from becoming an environment variable for 2181 * init. 2182 */ 2183 2184 static __init int setup_clearcpuid(char *arg) 2185 { 2186 return 1; 2187 } 2188 __setup("clearcpuid=", setup_clearcpuid); 2189 2190 static __init int setup_setcpuid(char *arg) 2191 { 2192 return 1; 2193 } 2194 __setup("setcpuid=", setup_setcpuid); 2195 2196 DEFINE_PER_CPU_CACHE_HOT(struct task_struct *, current_task) = &init_task; 2197 EXPORT_PER_CPU_SYMBOL(current_task); 2198 EXPORT_PER_CPU_SYMBOL(const_current_task); 2199 2200 DEFINE_PER_CPU_CACHE_HOT(int, __preempt_count) = INIT_PREEMPT_COUNT; 2201 EXPORT_PER_CPU_SYMBOL(__preempt_count); 2202 2203 DEFINE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 2204 2205 #ifdef CONFIG_X86_64 2206 /* 2207 * Note: Do not make this dependant on CONFIG_MITIGATION_CALL_DEPTH_TRACKING 2208 * so that this space is reserved in the hot cache section even when the 2209 * mitigation is disabled. 2210 */ 2211 DEFINE_PER_CPU_CACHE_HOT(u64, __x86_call_depth); 2212 EXPORT_PER_CPU_SYMBOL(__x86_call_depth); 2213 2214 static void wrmsrq_cstar(unsigned long val) 2215 { 2216 /* 2217 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2218 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2219 * guest. Avoid the pointless write on all Intel CPUs. 2220 */ 2221 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2222 wrmsrq(MSR_CSTAR, val); 2223 } 2224 2225 static inline void idt_syscall_init(void) 2226 { 2227 wrmsrq(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2228 2229 if (ia32_enabled()) { 2230 wrmsrq_cstar((unsigned long)entry_SYSCALL_compat); 2231 /* 2232 * This only works on Intel CPUs. 2233 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2234 * This does not cause SYSENTER to jump to the wrong location, because 2235 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2236 */ 2237 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2238 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 2239 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2240 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2241 } else { 2242 wrmsrq_cstar((unsigned long)entry_SYSCALL32_ignore); 2243 wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2244 wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2245 wrmsrq_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2246 } 2247 2248 /* 2249 * Flags to clear on syscall; clear as much as possible 2250 * to minimize user space-kernel interference. 2251 */ 2252 wrmsrq(MSR_SYSCALL_MASK, 2253 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2254 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2255 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2256 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2257 X86_EFLAGS_AC|X86_EFLAGS_ID); 2258 } 2259 2260 /* May not be marked __init: used by software suspend */ 2261 void syscall_init(void) 2262 { 2263 /* The default user and kernel segments */ 2264 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2265 2266 /* 2267 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and 2268 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED 2269 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit 2270 * instruction to return to ring 3 (both sysexit and sysret cause 2271 * #UD when FRED is enabled). 2272 */ 2273 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2274 idt_syscall_init(); 2275 } 2276 #endif /* CONFIG_X86_64 */ 2277 2278 #ifdef CONFIG_STACKPROTECTOR 2279 DEFINE_PER_CPU_CACHE_HOT(unsigned long, __stack_chk_guard); 2280 #ifndef CONFIG_SMP 2281 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2282 #endif 2283 #endif 2284 2285 static void initialize_debug_regs(void) 2286 { 2287 /* Control register first -- to make sure everything is disabled. */ 2288 set_debugreg(DR7_FIXED_1, 7); 2289 set_debugreg(DR6_RESERVED, 6); 2290 /* dr5 and dr4 don't exist */ 2291 set_debugreg(0, 3); 2292 set_debugreg(0, 2); 2293 set_debugreg(0, 1); 2294 set_debugreg(0, 0); 2295 } 2296 2297 #ifdef CONFIG_KGDB 2298 /* 2299 * Restore debug regs if using kgdbwait and you have a kernel debugger 2300 * connection established. 2301 */ 2302 static void dbg_restore_debug_regs(void) 2303 { 2304 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2305 arch_kgdb_ops.correct_hw_break(); 2306 } 2307 #else /* ! CONFIG_KGDB */ 2308 #define dbg_restore_debug_regs() 2309 #endif /* ! CONFIG_KGDB */ 2310 2311 static inline void setup_getcpu(int cpu) 2312 { 2313 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2314 struct desc_struct d = { }; 2315 2316 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2317 wrmsrq(MSR_TSC_AUX, cpudata); 2318 2319 /* Store CPU and node number in limit. */ 2320 d.limit0 = cpudata; 2321 d.limit1 = cpudata >> 16; 2322 2323 d.type = 5; /* RO data, expand down, accessed */ 2324 d.dpl = 3; /* Visible to user code */ 2325 d.s = 1; /* Not a system segment */ 2326 d.p = 1; /* Present */ 2327 d.d = 1; /* 32-bit */ 2328 2329 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2330 } 2331 2332 #ifdef CONFIG_X86_64 2333 static inline void tss_setup_ist(struct tss_struct *tss) 2334 { 2335 /* Set up the per-CPU TSS IST stacks */ 2336 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2337 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2338 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2339 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2340 /* Only mapped when SEV-ES is active */ 2341 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2342 } 2343 #else /* CONFIG_X86_64 */ 2344 static inline void tss_setup_ist(struct tss_struct *tss) { } 2345 #endif /* !CONFIG_X86_64 */ 2346 2347 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2348 { 2349 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2350 2351 #ifdef CONFIG_X86_IOPL_IOPERM 2352 tss->io_bitmap.prev_max = 0; 2353 tss->io_bitmap.prev_sequence = 0; 2354 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2355 /* 2356 * Invalidate the extra array entry past the end of the all 2357 * permission bitmap as required by the hardware. 2358 */ 2359 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2360 #endif 2361 } 2362 2363 /* 2364 * Setup everything needed to handle exceptions from the IDT, including the IST 2365 * exceptions which use paranoid_entry(). 2366 */ 2367 void cpu_init_exception_handling(bool boot_cpu) 2368 { 2369 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2370 int cpu = raw_smp_processor_id(); 2371 2372 /* paranoid_entry() gets the CPU number from the GDT */ 2373 setup_getcpu(cpu); 2374 2375 /* For IDT mode, IST vectors need to be set in TSS. */ 2376 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2377 tss_setup_ist(tss); 2378 tss_setup_io_bitmap(tss); 2379 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2380 2381 load_TR_desc(); 2382 2383 /* GHCB needs to be setup to handle #VC. */ 2384 setup_ghcb(); 2385 2386 if (cpu_feature_enabled(X86_FEATURE_FRED)) { 2387 /* The boot CPU has enabled FRED during early boot */ 2388 if (!boot_cpu) 2389 cpu_init_fred_exceptions(); 2390 2391 cpu_init_fred_rsps(); 2392 } else { 2393 load_current_idt(); 2394 } 2395 } 2396 2397 void __init cpu_init_replace_early_idt(void) 2398 { 2399 if (cpu_feature_enabled(X86_FEATURE_FRED)) 2400 cpu_init_fred_exceptions(); 2401 else 2402 idt_setup_early_pf(); 2403 } 2404 2405 /* 2406 * cpu_init() initializes state that is per-CPU. Some data is already 2407 * initialized (naturally) in the bootstrap process, such as the GDT. We 2408 * reload it nevertheless, this function acts as a 'CPU state barrier', 2409 * nothing should get across. 2410 */ 2411 void cpu_init(void) 2412 { 2413 struct task_struct *cur = current; 2414 int cpu = raw_smp_processor_id(); 2415 2416 #ifdef CONFIG_NUMA 2417 if (this_cpu_read(numa_node) == 0 && 2418 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2419 set_numa_node(early_cpu_to_node(cpu)); 2420 #endif 2421 pr_debug("Initializing CPU#%d\n", cpu); 2422 2423 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2424 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2425 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2426 2427 if (IS_ENABLED(CONFIG_X86_64)) { 2428 loadsegment(fs, 0); 2429 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2430 syscall_init(); 2431 2432 wrmsrq(MSR_FS_BASE, 0); 2433 wrmsrq(MSR_KERNEL_GS_BASE, 0); 2434 barrier(); 2435 2436 x2apic_setup(); 2437 2438 intel_posted_msi_init(); 2439 } 2440 2441 mmgrab(&init_mm); 2442 cur->active_mm = &init_mm; 2443 BUG_ON(cur->mm); 2444 initialize_tlbstate_and_flush(); 2445 enter_lazy_tlb(&init_mm, cur); 2446 2447 /* 2448 * sp0 points to the entry trampoline stack regardless of what task 2449 * is running. 2450 */ 2451 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2452 2453 load_mm_ldt(&init_mm); 2454 2455 initialize_debug_regs(); 2456 dbg_restore_debug_regs(); 2457 2458 doublefault_init_cpu_tss(); 2459 2460 if (is_uv_system()) 2461 uv_cpu_init(); 2462 2463 load_fixmap_gdt(cpu); 2464 } 2465 2466 #ifdef CONFIG_MICROCODE_LATE_LOADING 2467 /** 2468 * store_cpu_caps() - Store a snapshot of CPU capabilities 2469 * @curr_info: Pointer where to store it 2470 * 2471 * Returns: None 2472 */ 2473 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2474 { 2475 /* Reload CPUID max function as it might've changed. */ 2476 curr_info->cpuid_level = cpuid_eax(0); 2477 2478 /* Copy all capability leafs and pick up the synthetic ones. */ 2479 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2480 sizeof(curr_info->x86_capability)); 2481 2482 /* Get the hardware CPUID leafs */ 2483 get_cpu_cap(curr_info); 2484 } 2485 2486 /** 2487 * microcode_check() - Check if any CPU capabilities changed after an update. 2488 * @prev_info: CPU capabilities stored before an update. 2489 * 2490 * The microcode loader calls this upon late microcode load to recheck features, 2491 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2492 * 2493 * Return: None 2494 */ 2495 void microcode_check(struct cpuinfo_x86 *prev_info) 2496 { 2497 struct cpuinfo_x86 curr_info; 2498 2499 perf_check_microcode(); 2500 2501 amd_check_microcode(); 2502 2503 store_cpu_caps(&curr_info); 2504 2505 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2506 sizeof(prev_info->x86_capability))) 2507 return; 2508 2509 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2510 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2511 } 2512 #endif 2513 2514 /* 2515 * Invoked from core CPU hotplug code after hotplug operations 2516 */ 2517 void arch_smt_update(void) 2518 { 2519 /* Handle the speculative execution misfeatures */ 2520 cpu_bugs_smt_update(); 2521 /* Check whether IPI broadcasting can be enabled */ 2522 apic_smt_update(); 2523 } 2524 2525 void __init arch_cpu_finalize_init(void) 2526 { 2527 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 2528 2529 identify_boot_cpu(); 2530 2531 select_idle_routine(); 2532 2533 /* 2534 * identify_boot_cpu() initialized SMT support information, let the 2535 * core code know. 2536 */ 2537 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core); 2538 2539 if (!IS_ENABLED(CONFIG_SMP)) { 2540 pr_info("CPU: "); 2541 print_cpu_info(&boot_cpu_data); 2542 } 2543 2544 cpu_select_mitigations(); 2545 2546 arch_smt_update(); 2547 2548 if (IS_ENABLED(CONFIG_X86_32)) { 2549 /* 2550 * Check whether this is a real i386 which is not longer 2551 * supported and fixup the utsname. 2552 */ 2553 if (boot_cpu_data.x86 < 4) 2554 panic("Kernel requires i486+ for 'invlpg' and other features"); 2555 2556 init_utsname()->machine[1] = 2557 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2558 } 2559 2560 /* 2561 * Must be before alternatives because it might set or clear 2562 * feature bits. 2563 */ 2564 fpu__init_system(); 2565 fpu__init_cpu(); 2566 2567 /* 2568 * This needs to follow the FPU initializtion, since EFI depends on it. 2569 */ 2570 if (efi_enabled(EFI_RUNTIME_SERVICES)) 2571 efi_enter_virtual_mode(); 2572 2573 /* 2574 * Ensure that access to the per CPU representation has the initial 2575 * boot CPU configuration. 2576 */ 2577 *c = boot_cpu_data; 2578 c->initialized = true; 2579 2580 alternative_instructions(); 2581 2582 if (IS_ENABLED(CONFIG_X86_64)) { 2583 unsigned long USER_PTR_MAX = TASK_SIZE_MAX; 2584 2585 /* 2586 * Enable this when LAM is gated on LASS support 2587 if (cpu_feature_enabled(X86_FEATURE_LAM)) 2588 USER_PTR_MAX = (1ul << 63) - PAGE_SIZE; 2589 */ 2590 runtime_const_init(ptr, USER_PTR_MAX); 2591 2592 /* 2593 * Make sure the first 2MB area is not mapped by huge pages 2594 * There are typically fixed size MTRRs in there and overlapping 2595 * MTRRs into large pages causes slow downs. 2596 * 2597 * Right now we don't do that with gbpages because there seems 2598 * very little benefit for that case. 2599 */ 2600 if (!direct_gbpages) 2601 set_memory_4k((unsigned long)__va(0), 1); 2602 } else { 2603 fpu__init_check_bugs(); 2604 } 2605 2606 /* 2607 * This needs to be called before any devices perform DMA 2608 * operations that might use the SWIOTLB bounce buffers. It will 2609 * mark the bounce buffers as decrypted so that their usage will 2610 * not cause "plain-text" data to be decrypted when accessed. It 2611 * must be called after late_time_init() so that Hyper-V x86/x64 2612 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2613 */ 2614 mem_encrypt_init(); 2615 } 2616