1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/mem_encrypt.h> 22 #include <linux/smp.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/pgtable.h> 27 #include <linux/stackprotector.h> 28 #include <linux/utsname.h> 29 30 #include <asm/alternative.h> 31 #include <asm/cmdline.h> 32 #include <asm/perf_event.h> 33 #include <asm/mmu_context.h> 34 #include <asm/doublefault.h> 35 #include <asm/archrandom.h> 36 #include <asm/hypervisor.h> 37 #include <asm/processor.h> 38 #include <asm/tlbflush.h> 39 #include <asm/debugreg.h> 40 #include <asm/sections.h> 41 #include <asm/vsyscall.h> 42 #include <linux/topology.h> 43 #include <linux/cpumask.h> 44 #include <linux/atomic.h> 45 #include <asm/proto.h> 46 #include <asm/setup.h> 47 #include <asm/apic.h> 48 #include <asm/desc.h> 49 #include <asm/fpu/api.h> 50 #include <asm/mtrr.h> 51 #include <asm/hwcap2.h> 52 #include <linux/numa.h> 53 #include <asm/numa.h> 54 #include <asm/asm.h> 55 #include <asm/bugs.h> 56 #include <asm/cpu.h> 57 #include <asm/mce.h> 58 #include <asm/msr.h> 59 #include <asm/cacheinfo.h> 60 #include <asm/memtype.h> 61 #include <asm/microcode.h> 62 #include <asm/intel-family.h> 63 #include <asm/cpu_device_id.h> 64 #include <asm/uv/uv.h> 65 #include <asm/ia32.h> 66 #include <asm/set_memory.h> 67 #include <asm/traps.h> 68 #include <asm/sev.h> 69 70 #include "cpu.h" 71 72 u32 elf_hwcap2 __read_mostly; 73 74 /* Number of siblings per CPU package */ 75 int smp_num_siblings = 1; 76 EXPORT_SYMBOL(smp_num_siblings); 77 78 static struct ppin_info { 79 int feature; 80 int msr_ppin_ctl; 81 int msr_ppin; 82 } ppin_info[] = { 83 [X86_VENDOR_INTEL] = { 84 .feature = X86_FEATURE_INTEL_PPIN, 85 .msr_ppin_ctl = MSR_PPIN_CTL, 86 .msr_ppin = MSR_PPIN 87 }, 88 [X86_VENDOR_AMD] = { 89 .feature = X86_FEATURE_AMD_PPIN, 90 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 91 .msr_ppin = MSR_AMD_PPIN 92 }, 93 }; 94 95 static const struct x86_cpu_id ppin_cpuids[] = { 96 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 97 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 98 99 /* Legacy models without CPUID enumeration */ 100 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 101 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 102 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 103 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 104 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 105 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 106 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 107 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 108 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 109 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 110 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 111 112 {} 113 }; 114 115 static void ppin_init(struct cpuinfo_x86 *c) 116 { 117 const struct x86_cpu_id *id; 118 unsigned long long val; 119 struct ppin_info *info; 120 121 id = x86_match_cpu(ppin_cpuids); 122 if (!id) 123 return; 124 125 /* 126 * Testing the presence of the MSR is not enough. Need to check 127 * that the PPIN_CTL allows reading of the PPIN. 128 */ 129 info = (struct ppin_info *)id->driver_data; 130 131 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 132 goto clear_ppin; 133 134 if ((val & 3UL) == 1UL) { 135 /* PPIN locked in disabled mode */ 136 goto clear_ppin; 137 } 138 139 /* If PPIN is disabled, try to enable */ 140 if (!(val & 2UL)) { 141 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 142 rdmsrl_safe(info->msr_ppin_ctl, &val); 143 } 144 145 /* Is the enable bit set? */ 146 if (val & 2UL) { 147 c->ppin = __rdmsr(info->msr_ppin); 148 set_cpu_cap(c, info->feature); 149 return; 150 } 151 152 clear_ppin: 153 clear_cpu_cap(c, info->feature); 154 } 155 156 static void default_init(struct cpuinfo_x86 *c) 157 { 158 #ifdef CONFIG_X86_64 159 cpu_detect_cache_sizes(c); 160 #else 161 /* Not much we can do here... */ 162 /* Check if at least it has cpuid */ 163 if (c->cpuid_level == -1) { 164 /* No cpuid. It must be an ancient CPU */ 165 if (c->x86 == 4) 166 strcpy(c->x86_model_id, "486"); 167 else if (c->x86 == 3) 168 strcpy(c->x86_model_id, "386"); 169 } 170 #endif 171 } 172 173 static const struct cpu_dev default_cpu = { 174 .c_init = default_init, 175 .c_vendor = "Unknown", 176 .c_x86_vendor = X86_VENDOR_UNKNOWN, 177 }; 178 179 static const struct cpu_dev *this_cpu = &default_cpu; 180 181 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 182 #ifdef CONFIG_X86_64 183 /* 184 * We need valid kernel segments for data and code in long mode too 185 * IRET will check the segment types kkeil 2000/10/28 186 * Also sysret mandates a special GDT layout 187 * 188 * TLS descriptors are currently at a different place compared to i386. 189 * Hopefully nobody expects them at a fixed place (Wine?) 190 */ 191 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 192 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 193 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff), 194 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 195 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff), 196 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff), 197 #else 198 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 199 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 200 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 201 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff), 202 /* 203 * Segments used for calling PnP BIOS have byte granularity. 204 * They code segments and data segments have fixed 64k limits, 205 * the transfer segment sizes are set at run time. 206 */ 207 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 208 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 209 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff), 210 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 211 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 212 /* 213 * The APM segments have byte granularity and their bases 214 * are set at run time. All have 64k limits. 215 */ 216 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 217 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 218 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff), 219 220 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 221 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 222 #endif 223 } }; 224 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 225 226 #ifdef CONFIG_X86_64 227 static int __init x86_nopcid_setup(char *s) 228 { 229 /* nopcid doesn't accept parameters */ 230 if (s) 231 return -EINVAL; 232 233 /* do not emit a message if the feature is not present */ 234 if (!boot_cpu_has(X86_FEATURE_PCID)) 235 return 0; 236 237 setup_clear_cpu_cap(X86_FEATURE_PCID); 238 pr_info("nopcid: PCID feature disabled\n"); 239 return 0; 240 } 241 early_param("nopcid", x86_nopcid_setup); 242 #endif 243 244 static int __init x86_noinvpcid_setup(char *s) 245 { 246 /* noinvpcid doesn't accept parameters */ 247 if (s) 248 return -EINVAL; 249 250 /* do not emit a message if the feature is not present */ 251 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 252 return 0; 253 254 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 255 pr_info("noinvpcid: INVPCID feature disabled\n"); 256 return 0; 257 } 258 early_param("noinvpcid", x86_noinvpcid_setup); 259 260 #ifdef CONFIG_X86_32 261 static int cachesize_override = -1; 262 static int disable_x86_serial_nr = 1; 263 264 static int __init cachesize_setup(char *str) 265 { 266 get_option(&str, &cachesize_override); 267 return 1; 268 } 269 __setup("cachesize=", cachesize_setup); 270 271 /* Standard macro to see if a specific flag is changeable */ 272 static inline int flag_is_changeable_p(u32 flag) 273 { 274 u32 f1, f2; 275 276 /* 277 * Cyrix and IDT cpus allow disabling of CPUID 278 * so the code below may return different results 279 * when it is executed before and after enabling 280 * the CPUID. Add "volatile" to not allow gcc to 281 * optimize the subsequent calls to this function. 282 */ 283 asm volatile ("pushfl \n\t" 284 "pushfl \n\t" 285 "popl %0 \n\t" 286 "movl %0, %1 \n\t" 287 "xorl %2, %0 \n\t" 288 "pushl %0 \n\t" 289 "popfl \n\t" 290 "pushfl \n\t" 291 "popl %0 \n\t" 292 "popfl \n\t" 293 294 : "=&r" (f1), "=&r" (f2) 295 : "ir" (flag)); 296 297 return ((f1^f2) & flag) != 0; 298 } 299 300 /* Probe for the CPUID instruction */ 301 int have_cpuid_p(void) 302 { 303 return flag_is_changeable_p(X86_EFLAGS_ID); 304 } 305 306 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 307 { 308 unsigned long lo, hi; 309 310 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 311 return; 312 313 /* Disable processor serial number: */ 314 315 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 316 lo |= 0x200000; 317 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 318 319 pr_notice("CPU serial number disabled.\n"); 320 clear_cpu_cap(c, X86_FEATURE_PN); 321 322 /* Disabling the serial number may affect the cpuid level */ 323 c->cpuid_level = cpuid_eax(0); 324 } 325 326 static int __init x86_serial_nr_setup(char *s) 327 { 328 disable_x86_serial_nr = 0; 329 return 1; 330 } 331 __setup("serialnumber", x86_serial_nr_setup); 332 #else 333 static inline int flag_is_changeable_p(u32 flag) 334 { 335 return 1; 336 } 337 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 338 { 339 } 340 #endif 341 342 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 343 { 344 if (cpu_has(c, X86_FEATURE_SMEP)) 345 cr4_set_bits(X86_CR4_SMEP); 346 } 347 348 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 349 { 350 unsigned long eflags = native_save_fl(); 351 352 /* This should have been cleared long ago */ 353 BUG_ON(eflags & X86_EFLAGS_AC); 354 355 if (cpu_has(c, X86_FEATURE_SMAP)) 356 cr4_set_bits(X86_CR4_SMAP); 357 } 358 359 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 360 { 361 /* Check the boot processor, plus build option for UMIP. */ 362 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 363 goto out; 364 365 /* Check the current processor's cpuid bits. */ 366 if (!cpu_has(c, X86_FEATURE_UMIP)) 367 goto out; 368 369 cr4_set_bits(X86_CR4_UMIP); 370 371 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 372 373 return; 374 375 out: 376 /* 377 * Make sure UMIP is disabled in case it was enabled in a 378 * previous boot (e.g., via kexec). 379 */ 380 cr4_clear_bits(X86_CR4_UMIP); 381 } 382 383 /* These bits should not change their value after CPU init is finished. */ 384 static const unsigned long cr4_pinned_mask = 385 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 386 X86_CR4_FSGSBASE | X86_CR4_CET; 387 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 388 static unsigned long cr4_pinned_bits __ro_after_init; 389 390 void native_write_cr0(unsigned long val) 391 { 392 unsigned long bits_missing = 0; 393 394 set_register: 395 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 396 397 if (static_branch_likely(&cr_pinning)) { 398 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 399 bits_missing = X86_CR0_WP; 400 val |= bits_missing; 401 goto set_register; 402 } 403 /* Warn after we've set the missing bits. */ 404 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 405 } 406 } 407 EXPORT_SYMBOL(native_write_cr0); 408 409 void __no_profile native_write_cr4(unsigned long val) 410 { 411 unsigned long bits_changed = 0; 412 413 set_register: 414 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 415 416 if (static_branch_likely(&cr_pinning)) { 417 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 418 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 419 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 420 goto set_register; 421 } 422 /* Warn after we've corrected the changed bits. */ 423 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 424 bits_changed); 425 } 426 } 427 #if IS_MODULE(CONFIG_LKDTM) 428 EXPORT_SYMBOL_GPL(native_write_cr4); 429 #endif 430 431 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 432 { 433 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 434 435 lockdep_assert_irqs_disabled(); 436 437 newval = (cr4 & ~clear) | set; 438 if (newval != cr4) { 439 this_cpu_write(cpu_tlbstate.cr4, newval); 440 __write_cr4(newval); 441 } 442 } 443 EXPORT_SYMBOL(cr4_update_irqsoff); 444 445 /* Read the CR4 shadow. */ 446 unsigned long cr4_read_shadow(void) 447 { 448 return this_cpu_read(cpu_tlbstate.cr4); 449 } 450 EXPORT_SYMBOL_GPL(cr4_read_shadow); 451 452 void cr4_init(void) 453 { 454 unsigned long cr4 = __read_cr4(); 455 456 if (boot_cpu_has(X86_FEATURE_PCID)) 457 cr4 |= X86_CR4_PCIDE; 458 if (static_branch_likely(&cr_pinning)) 459 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 460 461 __write_cr4(cr4); 462 463 /* Initialize cr4 shadow for this CPU. */ 464 this_cpu_write(cpu_tlbstate.cr4, cr4); 465 } 466 467 /* 468 * Once CPU feature detection is finished (and boot params have been 469 * parsed), record any of the sensitive CR bits that are set, and 470 * enable CR pinning. 471 */ 472 static void __init setup_cr_pinning(void) 473 { 474 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 475 static_key_enable(&cr_pinning.key); 476 } 477 478 static __init int x86_nofsgsbase_setup(char *arg) 479 { 480 /* Require an exact match without trailing characters. */ 481 if (strlen(arg)) 482 return 0; 483 484 /* Do not emit a message if the feature is not present. */ 485 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 486 return 1; 487 488 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 489 pr_info("FSGSBASE disabled via kernel command line\n"); 490 return 1; 491 } 492 __setup("nofsgsbase", x86_nofsgsbase_setup); 493 494 /* 495 * Protection Keys are not available in 32-bit mode. 496 */ 497 static bool pku_disabled; 498 499 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 500 { 501 if (c == &boot_cpu_data) { 502 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 503 return; 504 /* 505 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 506 * bit to be set. Enforce it. 507 */ 508 setup_force_cpu_cap(X86_FEATURE_OSPKE); 509 510 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 511 return; 512 } 513 514 cr4_set_bits(X86_CR4_PKE); 515 /* Load the default PKRU value */ 516 pkru_write_default(); 517 } 518 519 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 520 static __init int setup_disable_pku(char *arg) 521 { 522 /* 523 * Do not clear the X86_FEATURE_PKU bit. All of the 524 * runtime checks are against OSPKE so clearing the 525 * bit does nothing. 526 * 527 * This way, we will see "pku" in cpuinfo, but not 528 * "ospke", which is exactly what we want. It shows 529 * that the CPU has PKU, but the OS has not enabled it. 530 * This happens to be exactly how a system would look 531 * if we disabled the config option. 532 */ 533 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 534 pku_disabled = true; 535 return 1; 536 } 537 __setup("nopku", setup_disable_pku); 538 #endif 539 540 #ifdef CONFIG_X86_KERNEL_IBT 541 542 __noendbr u64 ibt_save(bool disable) 543 { 544 u64 msr = 0; 545 546 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 547 rdmsrl(MSR_IA32_S_CET, msr); 548 if (disable) 549 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 550 } 551 552 return msr; 553 } 554 555 __noendbr void ibt_restore(u64 save) 556 { 557 u64 msr; 558 559 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 560 rdmsrl(MSR_IA32_S_CET, msr); 561 msr &= ~CET_ENDBR_EN; 562 msr |= (save & CET_ENDBR_EN); 563 wrmsrl(MSR_IA32_S_CET, msr); 564 } 565 } 566 567 #endif 568 569 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 570 { 571 bool user_shstk, kernel_ibt; 572 573 if (!IS_ENABLED(CONFIG_X86_CET)) 574 return; 575 576 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 577 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 578 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 579 580 if (!kernel_ibt && !user_shstk) 581 return; 582 583 if (user_shstk) 584 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 585 586 if (kernel_ibt) 587 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN); 588 else 589 wrmsrl(MSR_IA32_S_CET, 0); 590 591 cr4_set_bits(X86_CR4_CET); 592 593 if (kernel_ibt && ibt_selftest()) { 594 pr_err("IBT selftest: Failed!\n"); 595 wrmsrl(MSR_IA32_S_CET, 0); 596 setup_clear_cpu_cap(X86_FEATURE_IBT); 597 } 598 } 599 600 __noendbr void cet_disable(void) 601 { 602 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 603 cpu_feature_enabled(X86_FEATURE_SHSTK))) 604 return; 605 606 wrmsrl(MSR_IA32_S_CET, 0); 607 wrmsrl(MSR_IA32_U_CET, 0); 608 } 609 610 /* 611 * Some CPU features depend on higher CPUID levels, which may not always 612 * be available due to CPUID level capping or broken virtualization 613 * software. Add those features to this table to auto-disable them. 614 */ 615 struct cpuid_dependent_feature { 616 u32 feature; 617 u32 level; 618 }; 619 620 static const struct cpuid_dependent_feature 621 cpuid_dependent_features[] = { 622 { X86_FEATURE_MWAIT, 0x00000005 }, 623 { X86_FEATURE_DCA, 0x00000009 }, 624 { X86_FEATURE_XSAVE, 0x0000000d }, 625 { 0, 0 } 626 }; 627 628 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 629 { 630 const struct cpuid_dependent_feature *df; 631 632 for (df = cpuid_dependent_features; df->feature; df++) { 633 634 if (!cpu_has(c, df->feature)) 635 continue; 636 /* 637 * Note: cpuid_level is set to -1 if unavailable, but 638 * extended_extended_level is set to 0 if unavailable 639 * and the legitimate extended levels are all negative 640 * when signed; hence the weird messing around with 641 * signs here... 642 */ 643 if (!((s32)df->level < 0 ? 644 (u32)df->level > (u32)c->extended_cpuid_level : 645 (s32)df->level > (s32)c->cpuid_level)) 646 continue; 647 648 clear_cpu_cap(c, df->feature); 649 if (!warn) 650 continue; 651 652 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 653 x86_cap_flag(df->feature), df->level); 654 } 655 } 656 657 /* 658 * Naming convention should be: <Name> [(<Codename>)] 659 * This table only is used unless init_<vendor>() below doesn't set it; 660 * in particular, if CPUID levels 0x80000002..4 are supported, this 661 * isn't used 662 */ 663 664 /* Look up CPU names by table lookup. */ 665 static const char *table_lookup_model(struct cpuinfo_x86 *c) 666 { 667 #ifdef CONFIG_X86_32 668 const struct legacy_cpu_model_info *info; 669 670 if (c->x86_model >= 16) 671 return NULL; /* Range check */ 672 673 if (!this_cpu) 674 return NULL; 675 676 info = this_cpu->legacy_models; 677 678 while (info->family) { 679 if (info->family == c->x86) 680 return info->model_names[c->x86_model]; 681 info++; 682 } 683 #endif 684 return NULL; /* Not found */ 685 } 686 687 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 688 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 689 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 690 691 #ifdef CONFIG_X86_32 692 /* The 32-bit entry code needs to find cpu_entry_area. */ 693 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 694 #endif 695 696 /* Load the original GDT from the per-cpu structure */ 697 void load_direct_gdt(int cpu) 698 { 699 struct desc_ptr gdt_descr; 700 701 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 702 gdt_descr.size = GDT_SIZE - 1; 703 load_gdt(&gdt_descr); 704 } 705 EXPORT_SYMBOL_GPL(load_direct_gdt); 706 707 /* Load a fixmap remapping of the per-cpu GDT */ 708 void load_fixmap_gdt(int cpu) 709 { 710 struct desc_ptr gdt_descr; 711 712 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 713 gdt_descr.size = GDT_SIZE - 1; 714 load_gdt(&gdt_descr); 715 } 716 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 717 718 /** 719 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 720 * @cpu: The CPU number for which this is invoked 721 * 722 * Invoked during early boot to switch from early GDT and early per CPU to 723 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 724 * switch is implicit by loading the direct GDT. On 64bit this requires 725 * to update GSBASE. 726 */ 727 void __init switch_gdt_and_percpu_base(int cpu) 728 { 729 load_direct_gdt(cpu); 730 731 #ifdef CONFIG_X86_64 732 /* 733 * No need to load %gs. It is already correct. 734 * 735 * Writing %gs on 64bit would zero GSBASE which would make any per 736 * CPU operation up to the point of the wrmsrl() fault. 737 * 738 * Set GSBASE to the new offset. Until the wrmsrl() happens the 739 * early mapping is still valid. That means the GSBASE update will 740 * lose any prior per CPU data which was not copied over in 741 * setup_per_cpu_areas(). 742 * 743 * This works even with stackprotector enabled because the 744 * per CPU stack canary is 0 in both per CPU areas. 745 */ 746 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 747 #else 748 /* 749 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 750 * it is required to load FS again so that the 'hidden' part is 751 * updated from the new GDT. Up to this point the early per CPU 752 * translation is active. Any content of the early per CPU data 753 * which was not copied over in setup_per_cpu_areas() is lost. 754 */ 755 loadsegment(fs, __KERNEL_PERCPU); 756 #endif 757 } 758 759 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 760 761 static void get_model_name(struct cpuinfo_x86 *c) 762 { 763 unsigned int *v; 764 char *p, *q, *s; 765 766 if (c->extended_cpuid_level < 0x80000004) 767 return; 768 769 v = (unsigned int *)c->x86_model_id; 770 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 771 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 772 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 773 c->x86_model_id[48] = 0; 774 775 /* Trim whitespace */ 776 p = q = s = &c->x86_model_id[0]; 777 778 while (*p == ' ') 779 p++; 780 781 while (*p) { 782 /* Note the last non-whitespace index */ 783 if (!isspace(*p)) 784 s = q; 785 786 *q++ = *p++; 787 } 788 789 *(s + 1) = '\0'; 790 } 791 792 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 793 { 794 unsigned int eax, ebx, ecx, edx; 795 796 c->x86_max_cores = 1; 797 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 798 return; 799 800 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 801 if (eax & 0x1f) 802 c->x86_max_cores = (eax >> 26) + 1; 803 } 804 805 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 806 { 807 unsigned int n, dummy, ebx, ecx, edx, l2size; 808 809 n = c->extended_cpuid_level; 810 811 if (n >= 0x80000005) { 812 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 813 c->x86_cache_size = (ecx>>24) + (edx>>24); 814 #ifdef CONFIG_X86_64 815 /* On K8 L1 TLB is inclusive, so don't count it */ 816 c->x86_tlbsize = 0; 817 #endif 818 } 819 820 if (n < 0x80000006) /* Some chips just has a large L1. */ 821 return; 822 823 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 824 l2size = ecx >> 16; 825 826 #ifdef CONFIG_X86_64 827 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 828 #else 829 /* do processor-specific cache resizing */ 830 if (this_cpu->legacy_cache_size) 831 l2size = this_cpu->legacy_cache_size(c, l2size); 832 833 /* Allow user to override all this if necessary. */ 834 if (cachesize_override != -1) 835 l2size = cachesize_override; 836 837 if (l2size == 0) 838 return; /* Again, no L2 cache is possible */ 839 #endif 840 841 c->x86_cache_size = l2size; 842 } 843 844 u16 __read_mostly tlb_lli_4k[NR_INFO]; 845 u16 __read_mostly tlb_lli_2m[NR_INFO]; 846 u16 __read_mostly tlb_lli_4m[NR_INFO]; 847 u16 __read_mostly tlb_lld_4k[NR_INFO]; 848 u16 __read_mostly tlb_lld_2m[NR_INFO]; 849 u16 __read_mostly tlb_lld_4m[NR_INFO]; 850 u16 __read_mostly tlb_lld_1g[NR_INFO]; 851 852 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 853 { 854 if (this_cpu->c_detect_tlb) 855 this_cpu->c_detect_tlb(c); 856 857 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 858 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 859 tlb_lli_4m[ENTRIES]); 860 861 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 862 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 863 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 864 } 865 866 int detect_ht_early(struct cpuinfo_x86 *c) 867 { 868 #ifdef CONFIG_SMP 869 u32 eax, ebx, ecx, edx; 870 871 if (!cpu_has(c, X86_FEATURE_HT)) 872 return -1; 873 874 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 875 return -1; 876 877 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 878 return -1; 879 880 cpuid(1, &eax, &ebx, &ecx, &edx); 881 882 smp_num_siblings = (ebx & 0xff0000) >> 16; 883 if (smp_num_siblings == 1) 884 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 885 #endif 886 return 0; 887 } 888 889 void detect_ht(struct cpuinfo_x86 *c) 890 { 891 #ifdef CONFIG_SMP 892 int index_msb, core_bits; 893 894 if (detect_ht_early(c) < 0) 895 return; 896 897 index_msb = get_count_order(smp_num_siblings); 898 c->topo.pkg_id = apic->phys_pkg_id(c->topo.initial_apicid, index_msb); 899 900 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 901 902 index_msb = get_count_order(smp_num_siblings); 903 904 core_bits = get_count_order(c->x86_max_cores); 905 906 c->topo.core_id = apic->phys_pkg_id(c->topo.initial_apicid, index_msb) & 907 ((1 << core_bits) - 1); 908 #endif 909 } 910 911 static void get_cpu_vendor(struct cpuinfo_x86 *c) 912 { 913 char *v = c->x86_vendor_id; 914 int i; 915 916 for (i = 0; i < X86_VENDOR_NUM; i++) { 917 if (!cpu_devs[i]) 918 break; 919 920 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 921 (cpu_devs[i]->c_ident[1] && 922 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 923 924 this_cpu = cpu_devs[i]; 925 c->x86_vendor = this_cpu->c_x86_vendor; 926 return; 927 } 928 } 929 930 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 931 "CPU: Your system may be unstable.\n", v); 932 933 c->x86_vendor = X86_VENDOR_UNKNOWN; 934 this_cpu = &default_cpu; 935 } 936 937 void cpu_detect(struct cpuinfo_x86 *c) 938 { 939 /* Get vendor name */ 940 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 941 (unsigned int *)&c->x86_vendor_id[0], 942 (unsigned int *)&c->x86_vendor_id[8], 943 (unsigned int *)&c->x86_vendor_id[4]); 944 945 c->x86 = 4; 946 /* Intel-defined flags: level 0x00000001 */ 947 if (c->cpuid_level >= 0x00000001) { 948 u32 junk, tfms, cap0, misc; 949 950 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 951 c->x86 = x86_family(tfms); 952 c->x86_model = x86_model(tfms); 953 c->x86_stepping = x86_stepping(tfms); 954 955 if (cap0 & (1<<19)) { 956 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 957 c->x86_cache_alignment = c->x86_clflush_size; 958 } 959 } 960 } 961 962 static void apply_forced_caps(struct cpuinfo_x86 *c) 963 { 964 int i; 965 966 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 967 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 968 c->x86_capability[i] |= cpu_caps_set[i]; 969 } 970 } 971 972 static void init_speculation_control(struct cpuinfo_x86 *c) 973 { 974 /* 975 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 976 * and they also have a different bit for STIBP support. Also, 977 * a hypervisor might have set the individual AMD bits even on 978 * Intel CPUs, for finer-grained selection of what's available. 979 */ 980 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 981 set_cpu_cap(c, X86_FEATURE_IBRS); 982 set_cpu_cap(c, X86_FEATURE_IBPB); 983 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 984 } 985 986 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 987 set_cpu_cap(c, X86_FEATURE_STIBP); 988 989 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 990 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 991 set_cpu_cap(c, X86_FEATURE_SSBD); 992 993 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 994 set_cpu_cap(c, X86_FEATURE_IBRS); 995 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 996 } 997 998 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 999 set_cpu_cap(c, X86_FEATURE_IBPB); 1000 1001 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 1002 set_cpu_cap(c, X86_FEATURE_STIBP); 1003 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1004 } 1005 1006 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1007 set_cpu_cap(c, X86_FEATURE_SSBD); 1008 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1009 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1010 } 1011 } 1012 1013 void get_cpu_cap(struct cpuinfo_x86 *c) 1014 { 1015 u32 eax, ebx, ecx, edx; 1016 1017 /* Intel-defined flags: level 0x00000001 */ 1018 if (c->cpuid_level >= 0x00000001) { 1019 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1020 1021 c->x86_capability[CPUID_1_ECX] = ecx; 1022 c->x86_capability[CPUID_1_EDX] = edx; 1023 } 1024 1025 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1026 if (c->cpuid_level >= 0x00000006) 1027 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1028 1029 /* Additional Intel-defined flags: level 0x00000007 */ 1030 if (c->cpuid_level >= 0x00000007) { 1031 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1032 c->x86_capability[CPUID_7_0_EBX] = ebx; 1033 c->x86_capability[CPUID_7_ECX] = ecx; 1034 c->x86_capability[CPUID_7_EDX] = edx; 1035 1036 /* Check valid sub-leaf index before accessing it */ 1037 if (eax >= 1) { 1038 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1039 c->x86_capability[CPUID_7_1_EAX] = eax; 1040 } 1041 } 1042 1043 /* Extended state features: level 0x0000000d */ 1044 if (c->cpuid_level >= 0x0000000d) { 1045 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1046 1047 c->x86_capability[CPUID_D_1_EAX] = eax; 1048 } 1049 1050 /* AMD-defined flags: level 0x80000001 */ 1051 eax = cpuid_eax(0x80000000); 1052 c->extended_cpuid_level = eax; 1053 1054 if ((eax & 0xffff0000) == 0x80000000) { 1055 if (eax >= 0x80000001) { 1056 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1057 1058 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1059 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1060 } 1061 } 1062 1063 if (c->extended_cpuid_level >= 0x80000007) { 1064 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1065 1066 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1067 c->x86_power = edx; 1068 } 1069 1070 if (c->extended_cpuid_level >= 0x80000008) { 1071 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1072 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1073 } 1074 1075 if (c->extended_cpuid_level >= 0x8000000a) 1076 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1077 1078 if (c->extended_cpuid_level >= 0x8000001f) 1079 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1080 1081 if (c->extended_cpuid_level >= 0x80000021) 1082 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1083 1084 init_scattered_cpuid_features(c); 1085 init_speculation_control(c); 1086 1087 /* 1088 * Clear/Set all flags overridden by options, after probe. 1089 * This needs to happen each time we re-probe, which may happen 1090 * several times during CPU initialization. 1091 */ 1092 apply_forced_caps(c); 1093 } 1094 1095 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1096 { 1097 u32 eax, ebx, ecx, edx; 1098 bool vp_bits_from_cpuid = true; 1099 1100 if (!cpu_has(c, X86_FEATURE_CPUID) || 1101 (c->extended_cpuid_level < 0x80000008)) 1102 vp_bits_from_cpuid = false; 1103 1104 if (vp_bits_from_cpuid) { 1105 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1106 1107 c->x86_virt_bits = (eax >> 8) & 0xff; 1108 c->x86_phys_bits = eax & 0xff; 1109 } else { 1110 if (IS_ENABLED(CONFIG_X86_64)) { 1111 c->x86_clflush_size = 64; 1112 c->x86_phys_bits = 36; 1113 c->x86_virt_bits = 48; 1114 } else { 1115 c->x86_clflush_size = 32; 1116 c->x86_virt_bits = 32; 1117 c->x86_phys_bits = 32; 1118 1119 if (cpu_has(c, X86_FEATURE_PAE) || 1120 cpu_has(c, X86_FEATURE_PSE36)) 1121 c->x86_phys_bits = 36; 1122 } 1123 } 1124 c->x86_cache_bits = c->x86_phys_bits; 1125 c->x86_cache_alignment = c->x86_clflush_size; 1126 } 1127 1128 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1129 { 1130 #ifdef CONFIG_X86_32 1131 int i; 1132 1133 /* 1134 * First of all, decide if this is a 486 or higher 1135 * It's a 486 if we can modify the AC flag 1136 */ 1137 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1138 c->x86 = 4; 1139 else 1140 c->x86 = 3; 1141 1142 for (i = 0; i < X86_VENDOR_NUM; i++) 1143 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1144 c->x86_vendor_id[0] = 0; 1145 cpu_devs[i]->c_identify(c); 1146 if (c->x86_vendor_id[0]) { 1147 get_cpu_vendor(c); 1148 break; 1149 } 1150 } 1151 #endif 1152 } 1153 1154 #define NO_SPECULATION BIT(0) 1155 #define NO_MELTDOWN BIT(1) 1156 #define NO_SSB BIT(2) 1157 #define NO_L1TF BIT(3) 1158 #define NO_MDS BIT(4) 1159 #define MSBDS_ONLY BIT(5) 1160 #define NO_SWAPGS BIT(6) 1161 #define NO_ITLB_MULTIHIT BIT(7) 1162 #define NO_SPECTRE_V2 BIT(8) 1163 #define NO_MMIO BIT(9) 1164 #define NO_EIBRS_PBRSB BIT(10) 1165 1166 #define VULNWL(vendor, family, model, whitelist) \ 1167 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1168 1169 #define VULNWL_INTEL(model, whitelist) \ 1170 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1171 1172 #define VULNWL_AMD(family, whitelist) \ 1173 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1174 1175 #define VULNWL_HYGON(family, whitelist) \ 1176 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1177 1178 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1179 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1180 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1181 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1182 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1183 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1184 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1185 1186 /* Intel Family 6 */ 1187 VULNWL_INTEL(TIGERLAKE, NO_MMIO), 1188 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), 1189 VULNWL_INTEL(ALDERLAKE, NO_MMIO), 1190 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), 1191 1192 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1193 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1194 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1195 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1196 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1197 1198 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1199 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1200 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1201 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1202 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1203 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1204 1205 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1206 1207 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1208 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1209 1210 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1211 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1212 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1213 1214 /* 1215 * Technically, swapgs isn't serializing on AMD (despite it previously 1216 * being documented as such in the APM). But according to AMD, %gs is 1217 * updated non-speculatively, and the issuing of %gs-relative memory 1218 * operands will be blocked until the %gs update completes, which is 1219 * good enough for our purposes. 1220 */ 1221 1222 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), 1223 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1224 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1225 1226 /* AMD Family 0xf - 0x12 */ 1227 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1228 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1229 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1230 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1231 1232 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1233 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1234 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1235 1236 /* Zhaoxin Family 7 */ 1237 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1238 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1239 {} 1240 }; 1241 1242 #define VULNBL(vendor, family, model, blacklist) \ 1243 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1244 1245 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1246 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1247 INTEL_FAM6_##model, steppings, \ 1248 X86_FEATURE_ANY, issues) 1249 1250 #define VULNBL_AMD(family, blacklist) \ 1251 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1252 1253 #define VULNBL_HYGON(family, blacklist) \ 1254 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1255 1256 #define SRBDS BIT(0) 1257 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1258 #define MMIO BIT(1) 1259 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1260 #define MMIO_SBDS BIT(2) 1261 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1262 #define RETBLEED BIT(3) 1263 /* CPU is affected by SMT (cross-thread) return predictions */ 1264 #define SMT_RSB BIT(4) 1265 /* CPU is affected by SRSO */ 1266 #define SRSO BIT(5) 1267 /* CPU is affected by GDS */ 1268 #define GDS BIT(6) 1269 1270 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1271 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1272 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1273 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1274 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1275 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), 1276 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), 1277 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1278 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), 1279 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1280 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1281 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1282 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1283 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1284 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1285 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), 1286 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1287 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), 1288 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), 1289 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1290 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), 1291 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1292 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS), 1293 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS), 1294 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1295 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1296 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1297 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO), 1298 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1299 1300 VULNBL_AMD(0x15, RETBLEED), 1301 VULNBL_AMD(0x16, RETBLEED), 1302 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), 1303 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), 1304 VULNBL_AMD(0x19, SRSO), 1305 {} 1306 }; 1307 1308 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1309 { 1310 const struct x86_cpu_id *m = x86_match_cpu(table); 1311 1312 return m && !!(m->driver_data & which); 1313 } 1314 1315 u64 x86_read_arch_cap_msr(void) 1316 { 1317 u64 ia32_cap = 0; 1318 1319 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1320 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1321 1322 return ia32_cap; 1323 } 1324 1325 static bool arch_cap_mmio_immune(u64 ia32_cap) 1326 { 1327 return (ia32_cap & ARCH_CAP_FBSDP_NO && 1328 ia32_cap & ARCH_CAP_PSDP_NO && 1329 ia32_cap & ARCH_CAP_SBDR_SSDP_NO); 1330 } 1331 1332 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1333 { 1334 u64 ia32_cap = x86_read_arch_cap_msr(); 1335 1336 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1337 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1338 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1339 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1340 1341 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1342 return; 1343 1344 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1345 1346 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1347 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1348 1349 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1350 !(ia32_cap & ARCH_CAP_SSB_NO) && 1351 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1352 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1353 1354 /* 1355 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1356 * flag and protect from vendor-specific bugs via the whitelist. 1357 */ 1358 if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { 1359 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1360 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1361 !(ia32_cap & ARCH_CAP_PBRSB_NO)) 1362 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1363 } 1364 1365 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1366 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1367 setup_force_cpu_bug(X86_BUG_MDS); 1368 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1369 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1370 } 1371 1372 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1373 setup_force_cpu_bug(X86_BUG_SWAPGS); 1374 1375 /* 1376 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1377 * - TSX is supported or 1378 * - TSX_CTRL is present 1379 * 1380 * TSX_CTRL check is needed for cases when TSX could be disabled before 1381 * the kernel boot e.g. kexec. 1382 * TSX_CTRL check alone is not sufficient for cases when the microcode 1383 * update is not present or running as guest that don't get TSX_CTRL. 1384 */ 1385 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1386 (cpu_has(c, X86_FEATURE_RTM) || 1387 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1388 setup_force_cpu_bug(X86_BUG_TAA); 1389 1390 /* 1391 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1392 * in the vulnerability blacklist. 1393 * 1394 * Some of the implications and mitigation of Shared Buffers Data 1395 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1396 * SRBDS. 1397 */ 1398 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1399 cpu_has(c, X86_FEATURE_RDSEED)) && 1400 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1401 setup_force_cpu_bug(X86_BUG_SRBDS); 1402 1403 /* 1404 * Processor MMIO Stale Data bug enumeration 1405 * 1406 * Affected CPU list is generally enough to enumerate the vulnerability, 1407 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1408 * not want the guest to enumerate the bug. 1409 * 1410 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1411 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1412 */ 1413 if (!arch_cap_mmio_immune(ia32_cap)) { 1414 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1415 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1416 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1417 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1418 } 1419 1420 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1421 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA)) 1422 setup_force_cpu_bug(X86_BUG_RETBLEED); 1423 } 1424 1425 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1426 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1427 1428 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1429 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1430 setup_force_cpu_bug(X86_BUG_SRSO); 1431 } 1432 1433 /* 1434 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1435 * an affected processor, the VMM may have disabled the use of GATHER by 1436 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1437 * which means that AVX will be disabled. 1438 */ 1439 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) && 1440 boot_cpu_has(X86_FEATURE_AVX)) 1441 setup_force_cpu_bug(X86_BUG_GDS); 1442 1443 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1444 return; 1445 1446 /* Rogue Data Cache Load? No! */ 1447 if (ia32_cap & ARCH_CAP_RDCL_NO) 1448 return; 1449 1450 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1451 1452 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1453 return; 1454 1455 setup_force_cpu_bug(X86_BUG_L1TF); 1456 } 1457 1458 /* 1459 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1460 * unfortunately, that's not true in practice because of early VIA 1461 * chips and (more importantly) broken virtualizers that are not easy 1462 * to detect. In the latter case it doesn't even *fail* reliably, so 1463 * probing for it doesn't even work. Disable it completely on 32-bit 1464 * unless we can find a reliable way to detect all the broken cases. 1465 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1466 */ 1467 static void detect_nopl(void) 1468 { 1469 #ifdef CONFIG_X86_32 1470 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1471 #else 1472 setup_force_cpu_cap(X86_FEATURE_NOPL); 1473 #endif 1474 } 1475 1476 /* 1477 * We parse cpu parameters early because fpu__init_system() is executed 1478 * before parse_early_param(). 1479 */ 1480 static void __init cpu_parse_early_param(void) 1481 { 1482 char arg[128]; 1483 char *argptr = arg, *opt; 1484 int arglen, taint = 0; 1485 1486 #ifdef CONFIG_X86_32 1487 if (cmdline_find_option_bool(boot_command_line, "no387")) 1488 #ifdef CONFIG_MATH_EMULATION 1489 setup_clear_cpu_cap(X86_FEATURE_FPU); 1490 #else 1491 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1492 #endif 1493 1494 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1495 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1496 #endif 1497 1498 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1499 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1500 1501 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1502 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1503 1504 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1505 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1506 1507 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1508 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1509 1510 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1511 if (arglen <= 0) 1512 return; 1513 1514 pr_info("Clearing CPUID bits:"); 1515 1516 while (argptr) { 1517 bool found __maybe_unused = false; 1518 unsigned int bit; 1519 1520 opt = strsep(&argptr, ","); 1521 1522 /* 1523 * Handle naked numbers first for feature flags which don't 1524 * have names. 1525 */ 1526 if (!kstrtouint(opt, 10, &bit)) { 1527 if (bit < NCAPINTS * 32) { 1528 1529 /* empty-string, i.e., ""-defined feature flags */ 1530 if (!x86_cap_flags[bit]) 1531 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1532 else 1533 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1534 1535 setup_clear_cpu_cap(bit); 1536 taint++; 1537 } 1538 /* 1539 * The assumption is that there are no feature names with only 1540 * numbers in the name thus go to the next argument. 1541 */ 1542 continue; 1543 } 1544 1545 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1546 if (!x86_cap_flag(bit)) 1547 continue; 1548 1549 if (strcmp(x86_cap_flag(bit), opt)) 1550 continue; 1551 1552 pr_cont(" %s", opt); 1553 setup_clear_cpu_cap(bit); 1554 taint++; 1555 found = true; 1556 break; 1557 } 1558 1559 if (!found) 1560 pr_cont(" (unknown: %s)", opt); 1561 } 1562 pr_cont("\n"); 1563 1564 if (taint) 1565 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1566 } 1567 1568 /* 1569 * Do minimum CPU detection early. 1570 * Fields really needed: vendor, cpuid_level, family, model, mask, 1571 * cache alignment. 1572 * The others are not touched to avoid unwanted side effects. 1573 * 1574 * WARNING: this function is only called on the boot CPU. Don't add code 1575 * here that is supposed to run on all CPUs. 1576 */ 1577 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1578 { 1579 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1580 c->extended_cpuid_level = 0; 1581 1582 if (!have_cpuid_p()) 1583 identify_cpu_without_cpuid(c); 1584 1585 /* cyrix could have cpuid enabled via c_identify()*/ 1586 if (have_cpuid_p()) { 1587 cpu_detect(c); 1588 get_cpu_vendor(c); 1589 get_cpu_cap(c); 1590 setup_force_cpu_cap(X86_FEATURE_CPUID); 1591 cpu_parse_early_param(); 1592 1593 if (this_cpu->c_early_init) 1594 this_cpu->c_early_init(c); 1595 1596 c->cpu_index = 0; 1597 filter_cpuid_features(c, false); 1598 1599 if (this_cpu->c_bsp_init) 1600 this_cpu->c_bsp_init(c); 1601 } else { 1602 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1603 } 1604 1605 get_cpu_address_sizes(c); 1606 1607 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1608 1609 cpu_set_bug_bits(c); 1610 1611 sld_setup(c); 1612 1613 #ifdef CONFIG_X86_32 1614 /* 1615 * Regardless of whether PCID is enumerated, the SDM says 1616 * that it can't be enabled in 32-bit mode. 1617 */ 1618 setup_clear_cpu_cap(X86_FEATURE_PCID); 1619 #endif 1620 1621 /* 1622 * Later in the boot process pgtable_l5_enabled() relies on 1623 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1624 * enabled by this point we need to clear the feature bit to avoid 1625 * false-positives at the later stage. 1626 * 1627 * pgtable_l5_enabled() can be false here for several reasons: 1628 * - 5-level paging is disabled compile-time; 1629 * - it's 32-bit kernel; 1630 * - machine doesn't support 5-level paging; 1631 * - user specified 'no5lvl' in kernel command line. 1632 */ 1633 if (!pgtable_l5_enabled()) 1634 setup_clear_cpu_cap(X86_FEATURE_LA57); 1635 1636 detect_nopl(); 1637 } 1638 1639 void __init early_cpu_init(void) 1640 { 1641 const struct cpu_dev *const *cdev; 1642 int count = 0; 1643 1644 #ifdef CONFIG_PROCESSOR_SELECT 1645 pr_info("KERNEL supported cpus:\n"); 1646 #endif 1647 1648 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1649 const struct cpu_dev *cpudev = *cdev; 1650 1651 if (count >= X86_VENDOR_NUM) 1652 break; 1653 cpu_devs[count] = cpudev; 1654 count++; 1655 1656 #ifdef CONFIG_PROCESSOR_SELECT 1657 { 1658 unsigned int j; 1659 1660 for (j = 0; j < 2; j++) { 1661 if (!cpudev->c_ident[j]) 1662 continue; 1663 pr_info(" %s %s\n", cpudev->c_vendor, 1664 cpudev->c_ident[j]); 1665 } 1666 } 1667 #endif 1668 } 1669 early_identify_cpu(&boot_cpu_data); 1670 } 1671 1672 static bool detect_null_seg_behavior(void) 1673 { 1674 /* 1675 * Empirically, writing zero to a segment selector on AMD does 1676 * not clear the base, whereas writing zero to a segment 1677 * selector on Intel does clear the base. Intel's behavior 1678 * allows slightly faster context switches in the common case 1679 * where GS is unused by the prev and next threads. 1680 * 1681 * Since neither vendor documents this anywhere that I can see, 1682 * detect it directly instead of hard-coding the choice by 1683 * vendor. 1684 * 1685 * I've designated AMD's behavior as the "bug" because it's 1686 * counterintuitive and less friendly. 1687 */ 1688 1689 unsigned long old_base, tmp; 1690 rdmsrl(MSR_FS_BASE, old_base); 1691 wrmsrl(MSR_FS_BASE, 1); 1692 loadsegment(fs, 0); 1693 rdmsrl(MSR_FS_BASE, tmp); 1694 wrmsrl(MSR_FS_BASE, old_base); 1695 return tmp == 0; 1696 } 1697 1698 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1699 { 1700 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1701 if (!IS_ENABLED(CONFIG_X86_64)) 1702 return; 1703 1704 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1705 return; 1706 1707 /* 1708 * CPUID bit above wasn't set. If this kernel is still running 1709 * as a HV guest, then the HV has decided not to advertize 1710 * that CPUID bit for whatever reason. For example, one 1711 * member of the migration pool might be vulnerable. Which 1712 * means, the bug is present: set the BUG flag and return. 1713 */ 1714 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1715 set_cpu_bug(c, X86_BUG_NULL_SEG); 1716 return; 1717 } 1718 1719 /* 1720 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1721 * 0x18 is the respective family for Hygon. 1722 */ 1723 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1724 detect_null_seg_behavior()) 1725 return; 1726 1727 /* All the remaining ones are affected */ 1728 set_cpu_bug(c, X86_BUG_NULL_SEG); 1729 } 1730 1731 static void generic_identify(struct cpuinfo_x86 *c) 1732 { 1733 c->extended_cpuid_level = 0; 1734 1735 if (!have_cpuid_p()) 1736 identify_cpu_without_cpuid(c); 1737 1738 /* cyrix could have cpuid enabled via c_identify()*/ 1739 if (!have_cpuid_p()) 1740 return; 1741 1742 cpu_detect(c); 1743 1744 get_cpu_vendor(c); 1745 1746 get_cpu_cap(c); 1747 1748 get_cpu_address_sizes(c); 1749 1750 if (c->cpuid_level >= 0x00000001) { 1751 c->topo.initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1752 #ifdef CONFIG_X86_32 1753 # ifdef CONFIG_SMP 1754 c->topo.apicid = apic->phys_pkg_id(c->topo.initial_apicid, 0); 1755 # else 1756 c->topo.apicid = c->topo.initial_apicid; 1757 # endif 1758 #endif 1759 c->topo.pkg_id = c->topo.initial_apicid; 1760 } 1761 1762 get_model_name(c); /* Default name */ 1763 1764 /* 1765 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1766 * systems that run Linux at CPL > 0 may or may not have the 1767 * issue, but, even if they have the issue, there's absolutely 1768 * nothing we can do about it because we can't use the real IRET 1769 * instruction. 1770 * 1771 * NB: For the time being, only 32-bit kernels support 1772 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1773 * whether to apply espfix using paravirt hooks. If any 1774 * non-paravirt system ever shows up that does *not* have the 1775 * ESPFIX issue, we can change this. 1776 */ 1777 #ifdef CONFIG_X86_32 1778 set_cpu_bug(c, X86_BUG_ESPFIX); 1779 #endif 1780 } 1781 1782 /* 1783 * Validate that ACPI/mptables have the same information about the 1784 * effective APIC id and update the package map. 1785 */ 1786 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1787 { 1788 #ifdef CONFIG_SMP 1789 unsigned int cpu = smp_processor_id(); 1790 u32 apicid; 1791 1792 apicid = apic->cpu_present_to_apicid(cpu); 1793 1794 if (apicid != c->topo.apicid) { 1795 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1796 cpu, apicid, c->topo.initial_apicid); 1797 } 1798 BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); 1799 BUG_ON(topology_update_die_map(c->topo.die_id, cpu)); 1800 #else 1801 c->topo.logical_pkg_id = 0; 1802 #endif 1803 } 1804 1805 /* 1806 * This does the hard work of actually picking apart the CPU stuff... 1807 */ 1808 static void identify_cpu(struct cpuinfo_x86 *c) 1809 { 1810 int i; 1811 1812 c->loops_per_jiffy = loops_per_jiffy; 1813 c->x86_cache_size = 0; 1814 c->x86_vendor = X86_VENDOR_UNKNOWN; 1815 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1816 c->x86_vendor_id[0] = '\0'; /* Unset */ 1817 c->x86_model_id[0] = '\0'; /* Unset */ 1818 c->x86_max_cores = 1; 1819 c->x86_coreid_bits = 0; 1820 c->topo.cu_id = 0xff; 1821 c->topo.llc_id = BAD_APICID; 1822 c->topo.l2c_id = BAD_APICID; 1823 #ifdef CONFIG_X86_64 1824 c->x86_clflush_size = 64; 1825 c->x86_phys_bits = 36; 1826 c->x86_virt_bits = 48; 1827 #else 1828 c->cpuid_level = -1; /* CPUID not detected */ 1829 c->x86_clflush_size = 32; 1830 c->x86_phys_bits = 32; 1831 c->x86_virt_bits = 32; 1832 #endif 1833 c->x86_cache_alignment = c->x86_clflush_size; 1834 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1835 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1836 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1837 #endif 1838 1839 generic_identify(c); 1840 1841 if (this_cpu->c_identify) 1842 this_cpu->c_identify(c); 1843 1844 /* Clear/Set all flags overridden by options, after probe */ 1845 apply_forced_caps(c); 1846 1847 #ifdef CONFIG_X86_64 1848 c->topo.apicid = apic->phys_pkg_id(c->topo.initial_apicid, 0); 1849 #endif 1850 1851 1852 /* 1853 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 1854 * Hygon will clear it in ->c_init() below. 1855 */ 1856 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1857 1858 /* 1859 * Vendor-specific initialization. In this section we 1860 * canonicalize the feature flags, meaning if there are 1861 * features a certain CPU supports which CPUID doesn't 1862 * tell us, CPUID claiming incorrect flags, or other bugs, 1863 * we handle them here. 1864 * 1865 * At the end of this section, c->x86_capability better 1866 * indicate the features this CPU genuinely supports! 1867 */ 1868 if (this_cpu->c_init) 1869 this_cpu->c_init(c); 1870 1871 /* Disable the PN if appropriate */ 1872 squash_the_stupid_serial_number(c); 1873 1874 /* Set up SMEP/SMAP/UMIP */ 1875 setup_smep(c); 1876 setup_smap(c); 1877 setup_umip(c); 1878 1879 /* Enable FSGSBASE instructions if available. */ 1880 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1881 cr4_set_bits(X86_CR4_FSGSBASE); 1882 elf_hwcap2 |= HWCAP2_FSGSBASE; 1883 } 1884 1885 /* 1886 * The vendor-specific functions might have changed features. 1887 * Now we do "generic changes." 1888 */ 1889 1890 /* Filter out anything that depends on CPUID levels we don't have */ 1891 filter_cpuid_features(c, true); 1892 1893 /* If the model name is still unset, do table lookup. */ 1894 if (!c->x86_model_id[0]) { 1895 const char *p; 1896 p = table_lookup_model(c); 1897 if (p) 1898 strcpy(c->x86_model_id, p); 1899 else 1900 /* Last resort... */ 1901 sprintf(c->x86_model_id, "%02x/%02x", 1902 c->x86, c->x86_model); 1903 } 1904 1905 #ifdef CONFIG_X86_64 1906 detect_ht(c); 1907 #endif 1908 1909 x86_init_rdrand(c); 1910 setup_pku(c); 1911 setup_cet(c); 1912 1913 /* 1914 * Clear/Set all flags overridden by options, need do it 1915 * before following smp all cpus cap AND. 1916 */ 1917 apply_forced_caps(c); 1918 1919 /* 1920 * On SMP, boot_cpu_data holds the common feature set between 1921 * all CPUs; so make sure that we indicate which features are 1922 * common between the CPUs. The first time this routine gets 1923 * executed, c == &boot_cpu_data. 1924 */ 1925 if (c != &boot_cpu_data) { 1926 /* AND the already accumulated flags with these */ 1927 for (i = 0; i < NCAPINTS; i++) 1928 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1929 1930 /* OR, i.e. replicate the bug flags */ 1931 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1932 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1933 } 1934 1935 ppin_init(c); 1936 1937 /* Init Machine Check Exception if available. */ 1938 mcheck_cpu_init(c); 1939 1940 select_idle_routine(c); 1941 1942 #ifdef CONFIG_NUMA 1943 numa_add_cpu(smp_processor_id()); 1944 #endif 1945 } 1946 1947 /* 1948 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1949 * on 32-bit kernels: 1950 */ 1951 #ifdef CONFIG_X86_32 1952 void enable_sep_cpu(void) 1953 { 1954 struct tss_struct *tss; 1955 int cpu; 1956 1957 if (!boot_cpu_has(X86_FEATURE_SEP)) 1958 return; 1959 1960 cpu = get_cpu(); 1961 tss = &per_cpu(cpu_tss_rw, cpu); 1962 1963 /* 1964 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1965 * see the big comment in struct x86_hw_tss's definition. 1966 */ 1967 1968 tss->x86_tss.ss1 = __KERNEL_CS; 1969 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1970 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1971 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1972 1973 put_cpu(); 1974 } 1975 #endif 1976 1977 static __init void identify_boot_cpu(void) 1978 { 1979 identify_cpu(&boot_cpu_data); 1980 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1981 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1982 #ifdef CONFIG_X86_32 1983 enable_sep_cpu(); 1984 #endif 1985 cpu_detect_tlb(&boot_cpu_data); 1986 setup_cr_pinning(); 1987 1988 tsx_init(); 1989 lkgs_init(); 1990 } 1991 1992 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1993 { 1994 BUG_ON(c == &boot_cpu_data); 1995 identify_cpu(c); 1996 #ifdef CONFIG_X86_32 1997 enable_sep_cpu(); 1998 #endif 1999 validate_apic_and_package_id(c); 2000 x86_spec_ctrl_setup_ap(); 2001 update_srbds_msr(); 2002 if (boot_cpu_has_bug(X86_BUG_GDS)) 2003 update_gds_msr(); 2004 2005 tsx_ap_init(); 2006 } 2007 2008 void print_cpu_info(struct cpuinfo_x86 *c) 2009 { 2010 const char *vendor = NULL; 2011 2012 if (c->x86_vendor < X86_VENDOR_NUM) { 2013 vendor = this_cpu->c_vendor; 2014 } else { 2015 if (c->cpuid_level >= 0) 2016 vendor = c->x86_vendor_id; 2017 } 2018 2019 if (vendor && !strstr(c->x86_model_id, vendor)) 2020 pr_cont("%s ", vendor); 2021 2022 if (c->x86_model_id[0]) 2023 pr_cont("%s", c->x86_model_id); 2024 else 2025 pr_cont("%d86", c->x86); 2026 2027 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 2028 2029 if (c->x86_stepping || c->cpuid_level >= 0) 2030 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 2031 else 2032 pr_cont(")\n"); 2033 } 2034 2035 /* 2036 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 2037 * function prevents it from becoming an environment variable for init. 2038 */ 2039 static __init int setup_clearcpuid(char *arg) 2040 { 2041 return 1; 2042 } 2043 __setup("clearcpuid=", setup_clearcpuid); 2044 2045 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = { 2046 .current_task = &init_task, 2047 .preempt_count = INIT_PREEMPT_COUNT, 2048 .top_of_stack = TOP_OF_INIT_STACK, 2049 }; 2050 EXPORT_PER_CPU_SYMBOL(pcpu_hot); 2051 2052 #ifdef CONFIG_X86_64 2053 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 2054 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 2055 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2056 2057 static void wrmsrl_cstar(unsigned long val) 2058 { 2059 /* 2060 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2061 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2062 * guest. Avoid the pointless write on all Intel CPUs. 2063 */ 2064 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2065 wrmsrl(MSR_CSTAR, val); 2066 } 2067 2068 /* May not be marked __init: used by software suspend */ 2069 void syscall_init(void) 2070 { 2071 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2072 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2073 2074 if (ia32_enabled()) { 2075 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2076 /* 2077 * This only works on Intel CPUs. 2078 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2079 * This does not cause SYSENTER to jump to the wrong location, because 2080 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2081 */ 2082 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2083 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2084 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2085 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2086 } else { 2087 wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore); 2088 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2089 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2090 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2091 } 2092 2093 /* 2094 * Flags to clear on syscall; clear as much as possible 2095 * to minimize user space-kernel interference. 2096 */ 2097 wrmsrl(MSR_SYSCALL_MASK, 2098 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2099 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2100 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2101 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2102 X86_EFLAGS_AC|X86_EFLAGS_ID); 2103 } 2104 2105 #else /* CONFIG_X86_64 */ 2106 2107 #ifdef CONFIG_STACKPROTECTOR 2108 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2109 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2110 #endif 2111 2112 #endif /* CONFIG_X86_64 */ 2113 2114 /* 2115 * Clear all 6 debug registers: 2116 */ 2117 static void clear_all_debug_regs(void) 2118 { 2119 int i; 2120 2121 for (i = 0; i < 8; i++) { 2122 /* Ignore db4, db5 */ 2123 if ((i == 4) || (i == 5)) 2124 continue; 2125 2126 set_debugreg(0, i); 2127 } 2128 } 2129 2130 #ifdef CONFIG_KGDB 2131 /* 2132 * Restore debug regs if using kgdbwait and you have a kernel debugger 2133 * connection established. 2134 */ 2135 static void dbg_restore_debug_regs(void) 2136 { 2137 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2138 arch_kgdb_ops.correct_hw_break(); 2139 } 2140 #else /* ! CONFIG_KGDB */ 2141 #define dbg_restore_debug_regs() 2142 #endif /* ! CONFIG_KGDB */ 2143 2144 static inline void setup_getcpu(int cpu) 2145 { 2146 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2147 struct desc_struct d = { }; 2148 2149 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2150 wrmsr(MSR_TSC_AUX, cpudata, 0); 2151 2152 /* Store CPU and node number in limit. */ 2153 d.limit0 = cpudata; 2154 d.limit1 = cpudata >> 16; 2155 2156 d.type = 5; /* RO data, expand down, accessed */ 2157 d.dpl = 3; /* Visible to user code */ 2158 d.s = 1; /* Not a system segment */ 2159 d.p = 1; /* Present */ 2160 d.d = 1; /* 32-bit */ 2161 2162 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2163 } 2164 2165 #ifdef CONFIG_X86_64 2166 static inline void tss_setup_ist(struct tss_struct *tss) 2167 { 2168 /* Set up the per-CPU TSS IST stacks */ 2169 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2170 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2171 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2172 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2173 /* Only mapped when SEV-ES is active */ 2174 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2175 } 2176 #else /* CONFIG_X86_64 */ 2177 static inline void tss_setup_ist(struct tss_struct *tss) { } 2178 #endif /* !CONFIG_X86_64 */ 2179 2180 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2181 { 2182 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2183 2184 #ifdef CONFIG_X86_IOPL_IOPERM 2185 tss->io_bitmap.prev_max = 0; 2186 tss->io_bitmap.prev_sequence = 0; 2187 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2188 /* 2189 * Invalidate the extra array entry past the end of the all 2190 * permission bitmap as required by the hardware. 2191 */ 2192 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2193 #endif 2194 } 2195 2196 /* 2197 * Setup everything needed to handle exceptions from the IDT, including the IST 2198 * exceptions which use paranoid_entry(). 2199 */ 2200 void cpu_init_exception_handling(void) 2201 { 2202 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2203 int cpu = raw_smp_processor_id(); 2204 2205 /* paranoid_entry() gets the CPU number from the GDT */ 2206 setup_getcpu(cpu); 2207 2208 /* IST vectors need TSS to be set up. */ 2209 tss_setup_ist(tss); 2210 tss_setup_io_bitmap(tss); 2211 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2212 2213 load_TR_desc(); 2214 2215 /* GHCB needs to be setup to handle #VC. */ 2216 setup_ghcb(); 2217 2218 /* Finally load the IDT */ 2219 load_current_idt(); 2220 } 2221 2222 /* 2223 * cpu_init() initializes state that is per-CPU. Some data is already 2224 * initialized (naturally) in the bootstrap process, such as the GDT. We 2225 * reload it nevertheless, this function acts as a 'CPU state barrier', 2226 * nothing should get across. 2227 */ 2228 void cpu_init(void) 2229 { 2230 struct task_struct *cur = current; 2231 int cpu = raw_smp_processor_id(); 2232 2233 #ifdef CONFIG_NUMA 2234 if (this_cpu_read(numa_node) == 0 && 2235 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2236 set_numa_node(early_cpu_to_node(cpu)); 2237 #endif 2238 pr_debug("Initializing CPU#%d\n", cpu); 2239 2240 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2241 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2242 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2243 2244 if (IS_ENABLED(CONFIG_X86_64)) { 2245 loadsegment(fs, 0); 2246 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2247 syscall_init(); 2248 2249 wrmsrl(MSR_FS_BASE, 0); 2250 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2251 barrier(); 2252 2253 x2apic_setup(); 2254 } 2255 2256 mmgrab(&init_mm); 2257 cur->active_mm = &init_mm; 2258 BUG_ON(cur->mm); 2259 initialize_tlbstate_and_flush(); 2260 enter_lazy_tlb(&init_mm, cur); 2261 2262 /* 2263 * sp0 points to the entry trampoline stack regardless of what task 2264 * is running. 2265 */ 2266 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2267 2268 load_mm_ldt(&init_mm); 2269 2270 clear_all_debug_regs(); 2271 dbg_restore_debug_regs(); 2272 2273 doublefault_init_cpu_tss(); 2274 2275 if (is_uv_system()) 2276 uv_cpu_init(); 2277 2278 load_fixmap_gdt(cpu); 2279 } 2280 2281 #ifdef CONFIG_MICROCODE_LATE_LOADING 2282 /** 2283 * store_cpu_caps() - Store a snapshot of CPU capabilities 2284 * @curr_info: Pointer where to store it 2285 * 2286 * Returns: None 2287 */ 2288 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2289 { 2290 /* Reload CPUID max function as it might've changed. */ 2291 curr_info->cpuid_level = cpuid_eax(0); 2292 2293 /* Copy all capability leafs and pick up the synthetic ones. */ 2294 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2295 sizeof(curr_info->x86_capability)); 2296 2297 /* Get the hardware CPUID leafs */ 2298 get_cpu_cap(curr_info); 2299 } 2300 2301 /** 2302 * microcode_check() - Check if any CPU capabilities changed after an update. 2303 * @prev_info: CPU capabilities stored before an update. 2304 * 2305 * The microcode loader calls this upon late microcode load to recheck features, 2306 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2307 * 2308 * Return: None 2309 */ 2310 void microcode_check(struct cpuinfo_x86 *prev_info) 2311 { 2312 struct cpuinfo_x86 curr_info; 2313 2314 perf_check_microcode(); 2315 2316 amd_check_microcode(); 2317 2318 store_cpu_caps(&curr_info); 2319 2320 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2321 sizeof(prev_info->x86_capability))) 2322 return; 2323 2324 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2325 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2326 } 2327 #endif 2328 2329 /* 2330 * Invoked from core CPU hotplug code after hotplug operations 2331 */ 2332 void arch_smt_update(void) 2333 { 2334 /* Handle the speculative execution misfeatures */ 2335 cpu_bugs_smt_update(); 2336 /* Check whether IPI broadcasting can be enabled */ 2337 apic_smt_update(); 2338 } 2339 2340 void __init arch_cpu_finalize_init(void) 2341 { 2342 identify_boot_cpu(); 2343 2344 /* 2345 * identify_boot_cpu() initialized SMT support information, let the 2346 * core code know. 2347 */ 2348 cpu_smt_set_num_threads(smp_num_siblings, smp_num_siblings); 2349 2350 if (!IS_ENABLED(CONFIG_SMP)) { 2351 pr_info("CPU: "); 2352 print_cpu_info(&boot_cpu_data); 2353 } 2354 2355 cpu_select_mitigations(); 2356 2357 arch_smt_update(); 2358 2359 if (IS_ENABLED(CONFIG_X86_32)) { 2360 /* 2361 * Check whether this is a real i386 which is not longer 2362 * supported and fixup the utsname. 2363 */ 2364 if (boot_cpu_data.x86 < 4) 2365 panic("Kernel requires i486+ for 'invlpg' and other features"); 2366 2367 init_utsname()->machine[1] = 2368 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2369 } 2370 2371 /* 2372 * Must be before alternatives because it might set or clear 2373 * feature bits. 2374 */ 2375 fpu__init_system(); 2376 fpu__init_cpu(); 2377 2378 alternative_instructions(); 2379 2380 if (IS_ENABLED(CONFIG_X86_64)) { 2381 /* 2382 * Make sure the first 2MB area is not mapped by huge pages 2383 * There are typically fixed size MTRRs in there and overlapping 2384 * MTRRs into large pages causes slow downs. 2385 * 2386 * Right now we don't do that with gbpages because there seems 2387 * very little benefit for that case. 2388 */ 2389 if (!direct_gbpages) 2390 set_memory_4k((unsigned long)__va(0), 1); 2391 } else { 2392 fpu__init_check_bugs(); 2393 } 2394 2395 /* 2396 * This needs to be called before any devices perform DMA 2397 * operations that might use the SWIOTLB bounce buffers. It will 2398 * mark the bounce buffers as decrypted so that their usage will 2399 * not cause "plain-text" data to be decrypted when accessed. It 2400 * must be called after late_time_init() so that Hyper-V x86/x64 2401 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2402 */ 2403 mem_encrypt_init(); 2404 } 2405