1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 51 #ifdef CONFIG_X86_LOCAL_APIC 52 #include <asm/uv/uv.h> 53 #endif 54 55 #include "cpu.h" 56 57 u32 elf_hwcap2 __read_mostly; 58 59 /* all of these masks are initialized in setup_cpu_local_masks() */ 60 cpumask_var_t cpu_initialized_mask; 61 cpumask_var_t cpu_callout_mask; 62 cpumask_var_t cpu_callin_mask; 63 64 /* representing cpus for which sibling maps can be computed */ 65 cpumask_var_t cpu_sibling_setup_mask; 66 67 /* correctly size the local cpu masks */ 68 void __init setup_cpu_local_masks(void) 69 { 70 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 71 alloc_bootmem_cpumask_var(&cpu_callin_mask); 72 alloc_bootmem_cpumask_var(&cpu_callout_mask); 73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 74 } 75 76 static void default_init(struct cpuinfo_x86 *c) 77 { 78 #ifdef CONFIG_X86_64 79 cpu_detect_cache_sizes(c); 80 #else 81 /* Not much we can do here... */ 82 /* Check if at least it has cpuid */ 83 if (c->cpuid_level == -1) { 84 /* No cpuid. It must be an ancient CPU */ 85 if (c->x86 == 4) 86 strcpy(c->x86_model_id, "486"); 87 else if (c->x86 == 3) 88 strcpy(c->x86_model_id, "386"); 89 } 90 #endif 91 } 92 93 static const struct cpu_dev default_cpu = { 94 .c_init = default_init, 95 .c_vendor = "Unknown", 96 .c_x86_vendor = X86_VENDOR_UNKNOWN, 97 }; 98 99 static const struct cpu_dev *this_cpu = &default_cpu; 100 101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 102 #ifdef CONFIG_X86_64 103 /* 104 * We need valid kernel segments for data and code in long mode too 105 * IRET will check the segment types kkeil 2000/10/28 106 * Also sysret mandates a special GDT layout 107 * 108 * TLS descriptors are currently at a different place compared to i386. 109 * Hopefully nobody expects them at a fixed place (Wine?) 110 */ 111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 117 #else 118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 122 /* 123 * Segments used for calling PnP BIOS have byte granularity. 124 * They code segments and data segments have fixed 64k limits, 125 * the transfer segment sizes are set at run time. 126 */ 127 /* 32-bit code */ 128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 129 /* 16-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 131 /* 16-bit data */ 132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 138 * The APM segments have byte granularity and their bases 139 * are set at run time. All have 64k limits. 140 */ 141 /* 32-bit code */ 142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 143 /* 16-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 145 /* data */ 146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 147 148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 150 GDT_STACK_CANARY_INIT 151 #endif 152 } }; 153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 154 155 static int __init x86_mpx_setup(char *s) 156 { 157 /* require an exact match without trailing characters */ 158 if (strlen(s)) 159 return 0; 160 161 /* do not emit a message if the feature is not present */ 162 if (!boot_cpu_has(X86_FEATURE_MPX)) 163 return 1; 164 165 setup_clear_cpu_cap(X86_FEATURE_MPX); 166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 167 return 1; 168 } 169 __setup("nompx", x86_mpx_setup); 170 171 static int __init x86_noinvpcid_setup(char *s) 172 { 173 /* noinvpcid doesn't accept parameters */ 174 if (s) 175 return -EINVAL; 176 177 /* do not emit a message if the feature is not present */ 178 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 179 return 0; 180 181 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 182 pr_info("noinvpcid: INVPCID feature disabled\n"); 183 return 0; 184 } 185 early_param("noinvpcid", x86_noinvpcid_setup); 186 187 #ifdef CONFIG_X86_32 188 static int cachesize_override = -1; 189 static int disable_x86_serial_nr = 1; 190 191 static int __init cachesize_setup(char *str) 192 { 193 get_option(&str, &cachesize_override); 194 return 1; 195 } 196 __setup("cachesize=", cachesize_setup); 197 198 static int __init x86_sep_setup(char *s) 199 { 200 setup_clear_cpu_cap(X86_FEATURE_SEP); 201 return 1; 202 } 203 __setup("nosep", x86_sep_setup); 204 205 /* Standard macro to see if a specific flag is changeable */ 206 static inline int flag_is_changeable_p(u32 flag) 207 { 208 u32 f1, f2; 209 210 /* 211 * Cyrix and IDT cpus allow disabling of CPUID 212 * so the code below may return different results 213 * when it is executed before and after enabling 214 * the CPUID. Add "volatile" to not allow gcc to 215 * optimize the subsequent calls to this function. 216 */ 217 asm volatile ("pushfl \n\t" 218 "pushfl \n\t" 219 "popl %0 \n\t" 220 "movl %0, %1 \n\t" 221 "xorl %2, %0 \n\t" 222 "pushl %0 \n\t" 223 "popfl \n\t" 224 "pushfl \n\t" 225 "popl %0 \n\t" 226 "popfl \n\t" 227 228 : "=&r" (f1), "=&r" (f2) 229 : "ir" (flag)); 230 231 return ((f1^f2) & flag) != 0; 232 } 233 234 /* Probe for the CPUID instruction */ 235 int have_cpuid_p(void) 236 { 237 return flag_is_changeable_p(X86_EFLAGS_ID); 238 } 239 240 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 241 { 242 unsigned long lo, hi; 243 244 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 245 return; 246 247 /* Disable processor serial number: */ 248 249 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 250 lo |= 0x200000; 251 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 252 253 pr_notice("CPU serial number disabled.\n"); 254 clear_cpu_cap(c, X86_FEATURE_PN); 255 256 /* Disabling the serial number may affect the cpuid level */ 257 c->cpuid_level = cpuid_eax(0); 258 } 259 260 static int __init x86_serial_nr_setup(char *s) 261 { 262 disable_x86_serial_nr = 0; 263 return 1; 264 } 265 __setup("serialnumber", x86_serial_nr_setup); 266 #else 267 static inline int flag_is_changeable_p(u32 flag) 268 { 269 return 1; 270 } 271 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 272 { 273 } 274 #endif 275 276 static __init int setup_disable_smep(char *arg) 277 { 278 setup_clear_cpu_cap(X86_FEATURE_SMEP); 279 /* Check for things that depend on SMEP being enabled: */ 280 check_mpx_erratum(&boot_cpu_data); 281 return 1; 282 } 283 __setup("nosmep", setup_disable_smep); 284 285 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 286 { 287 if (cpu_has(c, X86_FEATURE_SMEP)) 288 cr4_set_bits(X86_CR4_SMEP); 289 } 290 291 static __init int setup_disable_smap(char *arg) 292 { 293 setup_clear_cpu_cap(X86_FEATURE_SMAP); 294 return 1; 295 } 296 __setup("nosmap", setup_disable_smap); 297 298 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 299 { 300 unsigned long eflags = native_save_fl(); 301 302 /* This should have been cleared long ago */ 303 BUG_ON(eflags & X86_EFLAGS_AC); 304 305 if (cpu_has(c, X86_FEATURE_SMAP)) { 306 #ifdef CONFIG_X86_SMAP 307 cr4_set_bits(X86_CR4_SMAP); 308 #else 309 cr4_clear_bits(X86_CR4_SMAP); 310 #endif 311 } 312 } 313 314 /* 315 * Protection Keys are not available in 32-bit mode. 316 */ 317 static bool pku_disabled; 318 319 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 320 { 321 /* check the boot processor, plus compile options for PKU: */ 322 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 323 return; 324 /* checks the actual processor's cpuid bits: */ 325 if (!cpu_has(c, X86_FEATURE_PKU)) 326 return; 327 if (pku_disabled) 328 return; 329 330 cr4_set_bits(X86_CR4_PKE); 331 /* 332 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 333 * cpuid bit to be set. We need to ensure that we 334 * update that bit in this CPU's "cpu_info". 335 */ 336 get_cpu_cap(c); 337 } 338 339 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 340 static __init int setup_disable_pku(char *arg) 341 { 342 /* 343 * Do not clear the X86_FEATURE_PKU bit. All of the 344 * runtime checks are against OSPKE so clearing the 345 * bit does nothing. 346 * 347 * This way, we will see "pku" in cpuinfo, but not 348 * "ospke", which is exactly what we want. It shows 349 * that the CPU has PKU, but the OS has not enabled it. 350 * This happens to be exactly how a system would look 351 * if we disabled the config option. 352 */ 353 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 354 pku_disabled = true; 355 return 1; 356 } 357 __setup("nopku", setup_disable_pku); 358 #endif /* CONFIG_X86_64 */ 359 360 /* 361 * Some CPU features depend on higher CPUID levels, which may not always 362 * be available due to CPUID level capping or broken virtualization 363 * software. Add those features to this table to auto-disable them. 364 */ 365 struct cpuid_dependent_feature { 366 u32 feature; 367 u32 level; 368 }; 369 370 static const struct cpuid_dependent_feature 371 cpuid_dependent_features[] = { 372 { X86_FEATURE_MWAIT, 0x00000005 }, 373 { X86_FEATURE_DCA, 0x00000009 }, 374 { X86_FEATURE_XSAVE, 0x0000000d }, 375 { 0, 0 } 376 }; 377 378 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 379 { 380 const struct cpuid_dependent_feature *df; 381 382 for (df = cpuid_dependent_features; df->feature; df++) { 383 384 if (!cpu_has(c, df->feature)) 385 continue; 386 /* 387 * Note: cpuid_level is set to -1 if unavailable, but 388 * extended_extended_level is set to 0 if unavailable 389 * and the legitimate extended levels are all negative 390 * when signed; hence the weird messing around with 391 * signs here... 392 */ 393 if (!((s32)df->level < 0 ? 394 (u32)df->level > (u32)c->extended_cpuid_level : 395 (s32)df->level > (s32)c->cpuid_level)) 396 continue; 397 398 clear_cpu_cap(c, df->feature); 399 if (!warn) 400 continue; 401 402 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 403 x86_cap_flag(df->feature), df->level); 404 } 405 } 406 407 /* 408 * Naming convention should be: <Name> [(<Codename>)] 409 * This table only is used unless init_<vendor>() below doesn't set it; 410 * in particular, if CPUID levels 0x80000002..4 are supported, this 411 * isn't used 412 */ 413 414 /* Look up CPU names by table lookup. */ 415 static const char *table_lookup_model(struct cpuinfo_x86 *c) 416 { 417 #ifdef CONFIG_X86_32 418 const struct legacy_cpu_model_info *info; 419 420 if (c->x86_model >= 16) 421 return NULL; /* Range check */ 422 423 if (!this_cpu) 424 return NULL; 425 426 info = this_cpu->legacy_models; 427 428 while (info->family) { 429 if (info->family == c->x86) 430 return info->model_names[c->x86_model]; 431 info++; 432 } 433 #endif 434 return NULL; /* Not found */ 435 } 436 437 __u32 cpu_caps_cleared[NCAPINTS]; 438 __u32 cpu_caps_set[NCAPINTS]; 439 440 void load_percpu_segment(int cpu) 441 { 442 #ifdef CONFIG_X86_32 443 loadsegment(fs, __KERNEL_PERCPU); 444 #else 445 __loadsegment_simple(gs, 0); 446 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 447 #endif 448 load_stack_canary_segment(); 449 } 450 451 /* Setup the fixmap mapping only once per-processor */ 452 static inline void setup_fixmap_gdt(int cpu) 453 { 454 #ifdef CONFIG_X86_64 455 /* On 64-bit systems, we use a read-only fixmap GDT. */ 456 pgprot_t prot = PAGE_KERNEL_RO; 457 #else 458 /* 459 * On native 32-bit systems, the GDT cannot be read-only because 460 * our double fault handler uses a task gate, and entering through 461 * a task gate needs to change an available TSS to busy. If the GDT 462 * is read-only, that will triple fault. 463 * 464 * On Xen PV, the GDT must be read-only because the hypervisor requires 465 * it. 466 */ 467 pgprot_t prot = boot_cpu_has(X86_FEATURE_XENPV) ? 468 PAGE_KERNEL_RO : PAGE_KERNEL; 469 #endif 470 471 __set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot); 472 } 473 474 /* Load the original GDT from the per-cpu structure */ 475 void load_direct_gdt(int cpu) 476 { 477 struct desc_ptr gdt_descr; 478 479 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 480 gdt_descr.size = GDT_SIZE - 1; 481 load_gdt(&gdt_descr); 482 } 483 EXPORT_SYMBOL_GPL(load_direct_gdt); 484 485 /* Load a fixmap remapping of the per-cpu GDT */ 486 void load_fixmap_gdt(int cpu) 487 { 488 struct desc_ptr gdt_descr; 489 490 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 491 gdt_descr.size = GDT_SIZE - 1; 492 load_gdt(&gdt_descr); 493 } 494 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 495 496 /* 497 * Current gdt points %fs at the "master" per-cpu area: after this, 498 * it's on the real one. 499 */ 500 void switch_to_new_gdt(int cpu) 501 { 502 /* Load the original GDT */ 503 load_direct_gdt(cpu); 504 /* Reload the per-cpu base */ 505 load_percpu_segment(cpu); 506 } 507 508 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 509 510 static void get_model_name(struct cpuinfo_x86 *c) 511 { 512 unsigned int *v; 513 char *p, *q, *s; 514 515 if (c->extended_cpuid_level < 0x80000004) 516 return; 517 518 v = (unsigned int *)c->x86_model_id; 519 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 520 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 521 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 522 c->x86_model_id[48] = 0; 523 524 /* Trim whitespace */ 525 p = q = s = &c->x86_model_id[0]; 526 527 while (*p == ' ') 528 p++; 529 530 while (*p) { 531 /* Note the last non-whitespace index */ 532 if (!isspace(*p)) 533 s = q; 534 535 *q++ = *p++; 536 } 537 538 *(s + 1) = '\0'; 539 } 540 541 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 542 { 543 unsigned int n, dummy, ebx, ecx, edx, l2size; 544 545 n = c->extended_cpuid_level; 546 547 if (n >= 0x80000005) { 548 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 549 c->x86_cache_size = (ecx>>24) + (edx>>24); 550 #ifdef CONFIG_X86_64 551 /* On K8 L1 TLB is inclusive, so don't count it */ 552 c->x86_tlbsize = 0; 553 #endif 554 } 555 556 if (n < 0x80000006) /* Some chips just has a large L1. */ 557 return; 558 559 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 560 l2size = ecx >> 16; 561 562 #ifdef CONFIG_X86_64 563 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 564 #else 565 /* do processor-specific cache resizing */ 566 if (this_cpu->legacy_cache_size) 567 l2size = this_cpu->legacy_cache_size(c, l2size); 568 569 /* Allow user to override all this if necessary. */ 570 if (cachesize_override != -1) 571 l2size = cachesize_override; 572 573 if (l2size == 0) 574 return; /* Again, no L2 cache is possible */ 575 #endif 576 577 c->x86_cache_size = l2size; 578 } 579 580 u16 __read_mostly tlb_lli_4k[NR_INFO]; 581 u16 __read_mostly tlb_lli_2m[NR_INFO]; 582 u16 __read_mostly tlb_lli_4m[NR_INFO]; 583 u16 __read_mostly tlb_lld_4k[NR_INFO]; 584 u16 __read_mostly tlb_lld_2m[NR_INFO]; 585 u16 __read_mostly tlb_lld_4m[NR_INFO]; 586 u16 __read_mostly tlb_lld_1g[NR_INFO]; 587 588 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 589 { 590 if (this_cpu->c_detect_tlb) 591 this_cpu->c_detect_tlb(c); 592 593 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 594 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 595 tlb_lli_4m[ENTRIES]); 596 597 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 598 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 599 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 600 } 601 602 void detect_ht(struct cpuinfo_x86 *c) 603 { 604 #ifdef CONFIG_SMP 605 u32 eax, ebx, ecx, edx; 606 int index_msb, core_bits; 607 static bool printed; 608 609 if (!cpu_has(c, X86_FEATURE_HT)) 610 return; 611 612 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 613 goto out; 614 615 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 616 return; 617 618 cpuid(1, &eax, &ebx, &ecx, &edx); 619 620 smp_num_siblings = (ebx & 0xff0000) >> 16; 621 622 if (smp_num_siblings == 1) { 623 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 624 goto out; 625 } 626 627 if (smp_num_siblings <= 1) 628 goto out; 629 630 index_msb = get_count_order(smp_num_siblings); 631 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 632 633 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 634 635 index_msb = get_count_order(smp_num_siblings); 636 637 core_bits = get_count_order(c->x86_max_cores); 638 639 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 640 ((1 << core_bits) - 1); 641 642 out: 643 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 644 pr_info("CPU: Physical Processor ID: %d\n", 645 c->phys_proc_id); 646 pr_info("CPU: Processor Core ID: %d\n", 647 c->cpu_core_id); 648 printed = 1; 649 } 650 #endif 651 } 652 653 static void get_cpu_vendor(struct cpuinfo_x86 *c) 654 { 655 char *v = c->x86_vendor_id; 656 int i; 657 658 for (i = 0; i < X86_VENDOR_NUM; i++) { 659 if (!cpu_devs[i]) 660 break; 661 662 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 663 (cpu_devs[i]->c_ident[1] && 664 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 665 666 this_cpu = cpu_devs[i]; 667 c->x86_vendor = this_cpu->c_x86_vendor; 668 return; 669 } 670 } 671 672 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 673 "CPU: Your system may be unstable.\n", v); 674 675 c->x86_vendor = X86_VENDOR_UNKNOWN; 676 this_cpu = &default_cpu; 677 } 678 679 void cpu_detect(struct cpuinfo_x86 *c) 680 { 681 /* Get vendor name */ 682 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 683 (unsigned int *)&c->x86_vendor_id[0], 684 (unsigned int *)&c->x86_vendor_id[8], 685 (unsigned int *)&c->x86_vendor_id[4]); 686 687 c->x86 = 4; 688 /* Intel-defined flags: level 0x00000001 */ 689 if (c->cpuid_level >= 0x00000001) { 690 u32 junk, tfms, cap0, misc; 691 692 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 693 c->x86 = x86_family(tfms); 694 c->x86_model = x86_model(tfms); 695 c->x86_mask = x86_stepping(tfms); 696 697 if (cap0 & (1<<19)) { 698 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 699 c->x86_cache_alignment = c->x86_clflush_size; 700 } 701 } 702 } 703 704 static void apply_forced_caps(struct cpuinfo_x86 *c) 705 { 706 int i; 707 708 for (i = 0; i < NCAPINTS; i++) { 709 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 710 c->x86_capability[i] |= cpu_caps_set[i]; 711 } 712 } 713 714 void get_cpu_cap(struct cpuinfo_x86 *c) 715 { 716 u32 eax, ebx, ecx, edx; 717 718 /* Intel-defined flags: level 0x00000001 */ 719 if (c->cpuid_level >= 0x00000001) { 720 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 721 722 c->x86_capability[CPUID_1_ECX] = ecx; 723 c->x86_capability[CPUID_1_EDX] = edx; 724 } 725 726 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 727 if (c->cpuid_level >= 0x00000006) 728 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 729 730 /* Additional Intel-defined flags: level 0x00000007 */ 731 if (c->cpuid_level >= 0x00000007) { 732 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 733 c->x86_capability[CPUID_7_0_EBX] = ebx; 734 c->x86_capability[CPUID_7_ECX] = ecx; 735 } 736 737 /* Extended state features: level 0x0000000d */ 738 if (c->cpuid_level >= 0x0000000d) { 739 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 740 741 c->x86_capability[CPUID_D_1_EAX] = eax; 742 } 743 744 /* Additional Intel-defined flags: level 0x0000000F */ 745 if (c->cpuid_level >= 0x0000000F) { 746 747 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 748 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 749 c->x86_capability[CPUID_F_0_EDX] = edx; 750 751 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 752 /* will be overridden if occupancy monitoring exists */ 753 c->x86_cache_max_rmid = ebx; 754 755 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 756 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 757 c->x86_capability[CPUID_F_1_EDX] = edx; 758 759 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 760 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 761 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 762 c->x86_cache_max_rmid = ecx; 763 c->x86_cache_occ_scale = ebx; 764 } 765 } else { 766 c->x86_cache_max_rmid = -1; 767 c->x86_cache_occ_scale = -1; 768 } 769 } 770 771 /* AMD-defined flags: level 0x80000001 */ 772 eax = cpuid_eax(0x80000000); 773 c->extended_cpuid_level = eax; 774 775 if ((eax & 0xffff0000) == 0x80000000) { 776 if (eax >= 0x80000001) { 777 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 778 779 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 780 c->x86_capability[CPUID_8000_0001_EDX] = edx; 781 } 782 } 783 784 if (c->extended_cpuid_level >= 0x80000007) { 785 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 786 787 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 788 c->x86_power = edx; 789 } 790 791 if (c->extended_cpuid_level >= 0x80000008) { 792 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 793 794 c->x86_virt_bits = (eax >> 8) & 0xff; 795 c->x86_phys_bits = eax & 0xff; 796 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 797 } 798 #ifdef CONFIG_X86_32 799 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 800 c->x86_phys_bits = 36; 801 #endif 802 803 if (c->extended_cpuid_level >= 0x8000000a) 804 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 805 806 init_scattered_cpuid_features(c); 807 808 /* 809 * Clear/Set all flags overridden by options, after probe. 810 * This needs to happen each time we re-probe, which may happen 811 * several times during CPU initialization. 812 */ 813 apply_forced_caps(c); 814 } 815 816 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 817 { 818 #ifdef CONFIG_X86_32 819 int i; 820 821 /* 822 * First of all, decide if this is a 486 or higher 823 * It's a 486 if we can modify the AC flag 824 */ 825 if (flag_is_changeable_p(X86_EFLAGS_AC)) 826 c->x86 = 4; 827 else 828 c->x86 = 3; 829 830 for (i = 0; i < X86_VENDOR_NUM; i++) 831 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 832 c->x86_vendor_id[0] = 0; 833 cpu_devs[i]->c_identify(c); 834 if (c->x86_vendor_id[0]) { 835 get_cpu_vendor(c); 836 break; 837 } 838 } 839 #endif 840 } 841 842 /* 843 * Do minimum CPU detection early. 844 * Fields really needed: vendor, cpuid_level, family, model, mask, 845 * cache alignment. 846 * The others are not touched to avoid unwanted side effects. 847 * 848 * WARNING: this function is only called on the BP. Don't add code here 849 * that is supposed to run on all CPUs. 850 */ 851 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 852 { 853 #ifdef CONFIG_X86_64 854 c->x86_clflush_size = 64; 855 c->x86_phys_bits = 36; 856 c->x86_virt_bits = 48; 857 #else 858 c->x86_clflush_size = 32; 859 c->x86_phys_bits = 32; 860 c->x86_virt_bits = 32; 861 #endif 862 c->x86_cache_alignment = c->x86_clflush_size; 863 864 memset(&c->x86_capability, 0, sizeof c->x86_capability); 865 c->extended_cpuid_level = 0; 866 867 /* cyrix could have cpuid enabled via c_identify()*/ 868 if (have_cpuid_p()) { 869 cpu_detect(c); 870 get_cpu_vendor(c); 871 get_cpu_cap(c); 872 setup_force_cpu_cap(X86_FEATURE_CPUID); 873 874 if (this_cpu->c_early_init) 875 this_cpu->c_early_init(c); 876 877 c->cpu_index = 0; 878 filter_cpuid_features(c, false); 879 880 if (this_cpu->c_bsp_init) 881 this_cpu->c_bsp_init(c); 882 } else { 883 identify_cpu_without_cpuid(c); 884 setup_clear_cpu_cap(X86_FEATURE_CPUID); 885 } 886 887 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 888 fpu__init_system(c); 889 } 890 891 void __init early_cpu_init(void) 892 { 893 const struct cpu_dev *const *cdev; 894 int count = 0; 895 896 #ifdef CONFIG_PROCESSOR_SELECT 897 pr_info("KERNEL supported cpus:\n"); 898 #endif 899 900 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 901 const struct cpu_dev *cpudev = *cdev; 902 903 if (count >= X86_VENDOR_NUM) 904 break; 905 cpu_devs[count] = cpudev; 906 count++; 907 908 #ifdef CONFIG_PROCESSOR_SELECT 909 { 910 unsigned int j; 911 912 for (j = 0; j < 2; j++) { 913 if (!cpudev->c_ident[j]) 914 continue; 915 pr_info(" %s %s\n", cpudev->c_vendor, 916 cpudev->c_ident[j]); 917 } 918 } 919 #endif 920 } 921 early_identify_cpu(&boot_cpu_data); 922 } 923 924 /* 925 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 926 * unfortunately, that's not true in practice because of early VIA 927 * chips and (more importantly) broken virtualizers that are not easy 928 * to detect. In the latter case it doesn't even *fail* reliably, so 929 * probing for it doesn't even work. Disable it completely on 32-bit 930 * unless we can find a reliable way to detect all the broken cases. 931 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 932 */ 933 static void detect_nopl(struct cpuinfo_x86 *c) 934 { 935 #ifdef CONFIG_X86_32 936 clear_cpu_cap(c, X86_FEATURE_NOPL); 937 #else 938 set_cpu_cap(c, X86_FEATURE_NOPL); 939 #endif 940 } 941 942 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 943 { 944 #ifdef CONFIG_X86_64 945 /* 946 * Empirically, writing zero to a segment selector on AMD does 947 * not clear the base, whereas writing zero to a segment 948 * selector on Intel does clear the base. Intel's behavior 949 * allows slightly faster context switches in the common case 950 * where GS is unused by the prev and next threads. 951 * 952 * Since neither vendor documents this anywhere that I can see, 953 * detect it directly instead of hardcoding the choice by 954 * vendor. 955 * 956 * I've designated AMD's behavior as the "bug" because it's 957 * counterintuitive and less friendly. 958 */ 959 960 unsigned long old_base, tmp; 961 rdmsrl(MSR_FS_BASE, old_base); 962 wrmsrl(MSR_FS_BASE, 1); 963 loadsegment(fs, 0); 964 rdmsrl(MSR_FS_BASE, tmp); 965 if (tmp != 0) 966 set_cpu_bug(c, X86_BUG_NULL_SEG); 967 wrmsrl(MSR_FS_BASE, old_base); 968 #endif 969 } 970 971 static void generic_identify(struct cpuinfo_x86 *c) 972 { 973 c->extended_cpuid_level = 0; 974 975 if (!have_cpuid_p()) 976 identify_cpu_without_cpuid(c); 977 978 /* cyrix could have cpuid enabled via c_identify()*/ 979 if (!have_cpuid_p()) 980 return; 981 982 cpu_detect(c); 983 984 get_cpu_vendor(c); 985 986 get_cpu_cap(c); 987 988 if (c->cpuid_level >= 0x00000001) { 989 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 990 #ifdef CONFIG_X86_32 991 # ifdef CONFIG_SMP 992 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 993 # else 994 c->apicid = c->initial_apicid; 995 # endif 996 #endif 997 c->phys_proc_id = c->initial_apicid; 998 } 999 1000 get_model_name(c); /* Default name */ 1001 1002 detect_nopl(c); 1003 1004 detect_null_seg_behavior(c); 1005 1006 /* 1007 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1008 * systems that run Linux at CPL > 0 may or may not have the 1009 * issue, but, even if they have the issue, there's absolutely 1010 * nothing we can do about it because we can't use the real IRET 1011 * instruction. 1012 * 1013 * NB: For the time being, only 32-bit kernels support 1014 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1015 * whether to apply espfix using paravirt hooks. If any 1016 * non-paravirt system ever shows up that does *not* have the 1017 * ESPFIX issue, we can change this. 1018 */ 1019 #ifdef CONFIG_X86_32 1020 # ifdef CONFIG_PARAVIRT 1021 do { 1022 extern void native_iret(void); 1023 if (pv_cpu_ops.iret == native_iret) 1024 set_cpu_bug(c, X86_BUG_ESPFIX); 1025 } while (0); 1026 # else 1027 set_cpu_bug(c, X86_BUG_ESPFIX); 1028 # endif 1029 #endif 1030 } 1031 1032 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1033 { 1034 /* 1035 * The heavy lifting of max_rmid and cache_occ_scale are handled 1036 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1037 * in case CQM bits really aren't there in this CPU. 1038 */ 1039 if (c != &boot_cpu_data) { 1040 boot_cpu_data.x86_cache_max_rmid = 1041 min(boot_cpu_data.x86_cache_max_rmid, 1042 c->x86_cache_max_rmid); 1043 } 1044 } 1045 1046 /* 1047 * Validate that ACPI/mptables have the same information about the 1048 * effective APIC id and update the package map. 1049 */ 1050 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1051 { 1052 #ifdef CONFIG_SMP 1053 unsigned int apicid, cpu = smp_processor_id(); 1054 1055 apicid = apic->cpu_present_to_apicid(cpu); 1056 1057 if (apicid != c->apicid) { 1058 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1059 cpu, apicid, c->initial_apicid); 1060 } 1061 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1062 #else 1063 c->logical_proc_id = 0; 1064 #endif 1065 } 1066 1067 /* 1068 * This does the hard work of actually picking apart the CPU stuff... 1069 */ 1070 static void identify_cpu(struct cpuinfo_x86 *c) 1071 { 1072 int i; 1073 1074 c->loops_per_jiffy = loops_per_jiffy; 1075 c->x86_cache_size = -1; 1076 c->x86_vendor = X86_VENDOR_UNKNOWN; 1077 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 1078 c->x86_vendor_id[0] = '\0'; /* Unset */ 1079 c->x86_model_id[0] = '\0'; /* Unset */ 1080 c->x86_max_cores = 1; 1081 c->x86_coreid_bits = 0; 1082 c->cu_id = 0xff; 1083 #ifdef CONFIG_X86_64 1084 c->x86_clflush_size = 64; 1085 c->x86_phys_bits = 36; 1086 c->x86_virt_bits = 48; 1087 #else 1088 c->cpuid_level = -1; /* CPUID not detected */ 1089 c->x86_clflush_size = 32; 1090 c->x86_phys_bits = 32; 1091 c->x86_virt_bits = 32; 1092 #endif 1093 c->x86_cache_alignment = c->x86_clflush_size; 1094 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1095 1096 generic_identify(c); 1097 1098 if (this_cpu->c_identify) 1099 this_cpu->c_identify(c); 1100 1101 /* Clear/Set all flags overridden by options, after probe */ 1102 apply_forced_caps(c); 1103 1104 #ifdef CONFIG_X86_64 1105 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1106 #endif 1107 1108 /* 1109 * Vendor-specific initialization. In this section we 1110 * canonicalize the feature flags, meaning if there are 1111 * features a certain CPU supports which CPUID doesn't 1112 * tell us, CPUID claiming incorrect flags, or other bugs, 1113 * we handle them here. 1114 * 1115 * At the end of this section, c->x86_capability better 1116 * indicate the features this CPU genuinely supports! 1117 */ 1118 if (this_cpu->c_init) 1119 this_cpu->c_init(c); 1120 1121 /* Disable the PN if appropriate */ 1122 squash_the_stupid_serial_number(c); 1123 1124 /* Set up SMEP/SMAP */ 1125 setup_smep(c); 1126 setup_smap(c); 1127 1128 /* 1129 * The vendor-specific functions might have changed features. 1130 * Now we do "generic changes." 1131 */ 1132 1133 /* Filter out anything that depends on CPUID levels we don't have */ 1134 filter_cpuid_features(c, true); 1135 1136 /* If the model name is still unset, do table lookup. */ 1137 if (!c->x86_model_id[0]) { 1138 const char *p; 1139 p = table_lookup_model(c); 1140 if (p) 1141 strcpy(c->x86_model_id, p); 1142 else 1143 /* Last resort... */ 1144 sprintf(c->x86_model_id, "%02x/%02x", 1145 c->x86, c->x86_model); 1146 } 1147 1148 #ifdef CONFIG_X86_64 1149 detect_ht(c); 1150 #endif 1151 1152 init_hypervisor(c); 1153 x86_init_rdrand(c); 1154 x86_init_cache_qos(c); 1155 setup_pku(c); 1156 1157 /* 1158 * Clear/Set all flags overridden by options, need do it 1159 * before following smp all cpus cap AND. 1160 */ 1161 apply_forced_caps(c); 1162 1163 /* 1164 * On SMP, boot_cpu_data holds the common feature set between 1165 * all CPUs; so make sure that we indicate which features are 1166 * common between the CPUs. The first time this routine gets 1167 * executed, c == &boot_cpu_data. 1168 */ 1169 if (c != &boot_cpu_data) { 1170 /* AND the already accumulated flags with these */ 1171 for (i = 0; i < NCAPINTS; i++) 1172 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1173 1174 /* OR, i.e. replicate the bug flags */ 1175 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1176 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1177 } 1178 1179 /* Init Machine Check Exception if available. */ 1180 mcheck_cpu_init(c); 1181 1182 select_idle_routine(c); 1183 1184 #ifdef CONFIG_NUMA 1185 numa_add_cpu(smp_processor_id()); 1186 #endif 1187 } 1188 1189 /* 1190 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1191 * on 32-bit kernels: 1192 */ 1193 #ifdef CONFIG_X86_32 1194 void enable_sep_cpu(void) 1195 { 1196 struct tss_struct *tss; 1197 int cpu; 1198 1199 if (!boot_cpu_has(X86_FEATURE_SEP)) 1200 return; 1201 1202 cpu = get_cpu(); 1203 tss = &per_cpu(cpu_tss, cpu); 1204 1205 /* 1206 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1207 * see the big comment in struct x86_hw_tss's definition. 1208 */ 1209 1210 tss->x86_tss.ss1 = __KERNEL_CS; 1211 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1212 1213 wrmsr(MSR_IA32_SYSENTER_ESP, 1214 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1215 0); 1216 1217 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1218 1219 put_cpu(); 1220 } 1221 #endif 1222 1223 void __init identify_boot_cpu(void) 1224 { 1225 identify_cpu(&boot_cpu_data); 1226 #ifdef CONFIG_X86_32 1227 sysenter_setup(); 1228 enable_sep_cpu(); 1229 #endif 1230 cpu_detect_tlb(&boot_cpu_data); 1231 } 1232 1233 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1234 { 1235 BUG_ON(c == &boot_cpu_data); 1236 identify_cpu(c); 1237 #ifdef CONFIG_X86_32 1238 enable_sep_cpu(); 1239 #endif 1240 mtrr_ap_init(); 1241 validate_apic_and_package_id(c); 1242 } 1243 1244 static __init int setup_noclflush(char *arg) 1245 { 1246 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1247 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1248 return 1; 1249 } 1250 __setup("noclflush", setup_noclflush); 1251 1252 void print_cpu_info(struct cpuinfo_x86 *c) 1253 { 1254 const char *vendor = NULL; 1255 1256 if (c->x86_vendor < X86_VENDOR_NUM) { 1257 vendor = this_cpu->c_vendor; 1258 } else { 1259 if (c->cpuid_level >= 0) 1260 vendor = c->x86_vendor_id; 1261 } 1262 1263 if (vendor && !strstr(c->x86_model_id, vendor)) 1264 pr_cont("%s ", vendor); 1265 1266 if (c->x86_model_id[0]) 1267 pr_cont("%s", c->x86_model_id); 1268 else 1269 pr_cont("%d86", c->x86); 1270 1271 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1272 1273 if (c->x86_mask || c->cpuid_level >= 0) 1274 pr_cont(", stepping: 0x%x)\n", c->x86_mask); 1275 else 1276 pr_cont(")\n"); 1277 } 1278 1279 static __init int setup_disablecpuid(char *arg) 1280 { 1281 int bit; 1282 1283 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32) 1284 setup_clear_cpu_cap(bit); 1285 else 1286 return 0; 1287 1288 return 1; 1289 } 1290 __setup("clearcpuid=", setup_disablecpuid); 1291 1292 #ifdef CONFIG_X86_64 1293 struct desc_ptr idt_descr __ro_after_init = { 1294 .size = NR_VECTORS * 16 - 1, 1295 .address = (unsigned long) idt_table, 1296 }; 1297 const struct desc_ptr debug_idt_descr = { 1298 .size = NR_VECTORS * 16 - 1, 1299 .address = (unsigned long) debug_idt_table, 1300 }; 1301 1302 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1303 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1304 1305 /* 1306 * The following percpu variables are hot. Align current_task to 1307 * cacheline size such that they fall in the same cacheline. 1308 */ 1309 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1310 &init_task; 1311 EXPORT_PER_CPU_SYMBOL(current_task); 1312 1313 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1314 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1315 1316 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1317 1318 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1319 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1320 1321 /* 1322 * Special IST stacks which the CPU switches to when it calls 1323 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1324 * limit), all of them are 4K, except the debug stack which 1325 * is 8K. 1326 */ 1327 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1328 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1329 [DEBUG_STACK - 1] = DEBUG_STKSZ 1330 }; 1331 1332 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1333 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1334 1335 /* May not be marked __init: used by software suspend */ 1336 void syscall_init(void) 1337 { 1338 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1339 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1340 1341 #ifdef CONFIG_IA32_EMULATION 1342 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1343 /* 1344 * This only works on Intel CPUs. 1345 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1346 * This does not cause SYSENTER to jump to the wrong location, because 1347 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1348 */ 1349 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1350 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1351 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1352 #else 1353 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1354 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1355 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1356 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1357 #endif 1358 1359 /* Flags to clear on syscall */ 1360 wrmsrl(MSR_SYSCALL_MASK, 1361 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1362 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1363 } 1364 1365 /* 1366 * Copies of the original ist values from the tss are only accessed during 1367 * debugging, no special alignment required. 1368 */ 1369 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1370 1371 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1372 DEFINE_PER_CPU(int, debug_stack_usage); 1373 1374 int is_debug_stack(unsigned long addr) 1375 { 1376 return __this_cpu_read(debug_stack_usage) || 1377 (addr <= __this_cpu_read(debug_stack_addr) && 1378 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1379 } 1380 NOKPROBE_SYMBOL(is_debug_stack); 1381 1382 DEFINE_PER_CPU(u32, debug_idt_ctr); 1383 1384 void debug_stack_set_zero(void) 1385 { 1386 this_cpu_inc(debug_idt_ctr); 1387 load_current_idt(); 1388 } 1389 NOKPROBE_SYMBOL(debug_stack_set_zero); 1390 1391 void debug_stack_reset(void) 1392 { 1393 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1394 return; 1395 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1396 load_current_idt(); 1397 } 1398 NOKPROBE_SYMBOL(debug_stack_reset); 1399 1400 #else /* CONFIG_X86_64 */ 1401 1402 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1403 EXPORT_PER_CPU_SYMBOL(current_task); 1404 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1405 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1406 1407 /* 1408 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1409 * the top of the kernel stack. Use an extra percpu variable to track the 1410 * top of the kernel stack directly. 1411 */ 1412 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1413 (unsigned long)&init_thread_union + THREAD_SIZE; 1414 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1415 1416 #ifdef CONFIG_CC_STACKPROTECTOR 1417 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1418 #endif 1419 1420 #endif /* CONFIG_X86_64 */ 1421 1422 /* 1423 * Clear all 6 debug registers: 1424 */ 1425 static void clear_all_debug_regs(void) 1426 { 1427 int i; 1428 1429 for (i = 0; i < 8; i++) { 1430 /* Ignore db4, db5 */ 1431 if ((i == 4) || (i == 5)) 1432 continue; 1433 1434 set_debugreg(0, i); 1435 } 1436 } 1437 1438 #ifdef CONFIG_KGDB 1439 /* 1440 * Restore debug regs if using kgdbwait and you have a kernel debugger 1441 * connection established. 1442 */ 1443 static void dbg_restore_debug_regs(void) 1444 { 1445 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1446 arch_kgdb_ops.correct_hw_break(); 1447 } 1448 #else /* ! CONFIG_KGDB */ 1449 #define dbg_restore_debug_regs() 1450 #endif /* ! CONFIG_KGDB */ 1451 1452 static void wait_for_master_cpu(int cpu) 1453 { 1454 #ifdef CONFIG_SMP 1455 /* 1456 * wait for ACK from master CPU before continuing 1457 * with AP initialization 1458 */ 1459 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1460 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1461 cpu_relax(); 1462 #endif 1463 } 1464 1465 /* 1466 * cpu_init() initializes state that is per-CPU. Some data is already 1467 * initialized (naturally) in the bootstrap process, such as the GDT 1468 * and IDT. We reload them nevertheless, this function acts as a 1469 * 'CPU state barrier', nothing should get across. 1470 * A lot of state is already set up in PDA init for 64 bit 1471 */ 1472 #ifdef CONFIG_X86_64 1473 1474 void cpu_init(void) 1475 { 1476 struct orig_ist *oist; 1477 struct task_struct *me; 1478 struct tss_struct *t; 1479 unsigned long v; 1480 int cpu = raw_smp_processor_id(); 1481 int i; 1482 1483 wait_for_master_cpu(cpu); 1484 1485 /* 1486 * Initialize the CR4 shadow before doing anything that could 1487 * try to read it. 1488 */ 1489 cr4_init_shadow(); 1490 1491 if (cpu) 1492 load_ucode_ap(); 1493 1494 t = &per_cpu(cpu_tss, cpu); 1495 oist = &per_cpu(orig_ist, cpu); 1496 1497 #ifdef CONFIG_NUMA 1498 if (this_cpu_read(numa_node) == 0 && 1499 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1500 set_numa_node(early_cpu_to_node(cpu)); 1501 #endif 1502 1503 me = current; 1504 1505 pr_debug("Initializing CPU#%d\n", cpu); 1506 1507 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1508 1509 /* 1510 * Initialize the per-CPU GDT with the boot GDT, 1511 * and set up the GDT descriptor: 1512 */ 1513 1514 switch_to_new_gdt(cpu); 1515 loadsegment(fs, 0); 1516 1517 load_current_idt(); 1518 1519 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1520 syscall_init(); 1521 1522 wrmsrl(MSR_FS_BASE, 0); 1523 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1524 barrier(); 1525 1526 x86_configure_nx(); 1527 x2apic_setup(); 1528 1529 /* 1530 * set up and load the per-CPU TSS 1531 */ 1532 if (!oist->ist[0]) { 1533 char *estacks = per_cpu(exception_stacks, cpu); 1534 1535 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1536 estacks += exception_stack_sizes[v]; 1537 oist->ist[v] = t->x86_tss.ist[v] = 1538 (unsigned long)estacks; 1539 if (v == DEBUG_STACK-1) 1540 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1541 } 1542 } 1543 1544 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1545 1546 /* 1547 * <= is required because the CPU will access up to 1548 * 8 bits beyond the end of the IO permission bitmap. 1549 */ 1550 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1551 t->io_bitmap[i] = ~0UL; 1552 1553 mmgrab(&init_mm); 1554 me->active_mm = &init_mm; 1555 BUG_ON(me->mm); 1556 enter_lazy_tlb(&init_mm, me); 1557 1558 load_sp0(t, ¤t->thread); 1559 set_tss_desc(cpu, t); 1560 load_TR_desc(); 1561 load_mm_ldt(&init_mm); 1562 1563 clear_all_debug_regs(); 1564 dbg_restore_debug_regs(); 1565 1566 fpu__init_cpu(); 1567 1568 if (is_uv_system()) 1569 uv_cpu_init(); 1570 1571 setup_fixmap_gdt(cpu); 1572 load_fixmap_gdt(cpu); 1573 } 1574 1575 #else 1576 1577 void cpu_init(void) 1578 { 1579 int cpu = smp_processor_id(); 1580 struct task_struct *curr = current; 1581 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1582 struct thread_struct *thread = &curr->thread; 1583 1584 wait_for_master_cpu(cpu); 1585 1586 /* 1587 * Initialize the CR4 shadow before doing anything that could 1588 * try to read it. 1589 */ 1590 cr4_init_shadow(); 1591 1592 show_ucode_info_early(); 1593 1594 pr_info("Initializing CPU#%d\n", cpu); 1595 1596 if (cpu_feature_enabled(X86_FEATURE_VME) || 1597 boot_cpu_has(X86_FEATURE_TSC) || 1598 boot_cpu_has(X86_FEATURE_DE)) 1599 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1600 1601 load_current_idt(); 1602 switch_to_new_gdt(cpu); 1603 1604 /* 1605 * Set up and load the per-CPU TSS and LDT 1606 */ 1607 mmgrab(&init_mm); 1608 curr->active_mm = &init_mm; 1609 BUG_ON(curr->mm); 1610 enter_lazy_tlb(&init_mm, curr); 1611 1612 load_sp0(t, thread); 1613 set_tss_desc(cpu, t); 1614 load_TR_desc(); 1615 load_mm_ldt(&init_mm); 1616 1617 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1618 1619 #ifdef CONFIG_DOUBLEFAULT 1620 /* Set up doublefault TSS pointer in the GDT */ 1621 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1622 #endif 1623 1624 clear_all_debug_regs(); 1625 dbg_restore_debug_regs(); 1626 1627 fpu__init_cpu(); 1628 1629 setup_fixmap_gdt(cpu); 1630 load_fixmap_gdt(cpu); 1631 } 1632 #endif 1633 1634 static void bsp_resume(void) 1635 { 1636 if (this_cpu->c_bsp_resume) 1637 this_cpu->c_bsp_resume(&boot_cpu_data); 1638 } 1639 1640 static struct syscore_ops cpu_syscore_ops = { 1641 .resume = bsp_resume, 1642 }; 1643 1644 static int __init init_cpu_syscore(void) 1645 { 1646 register_syscore_ops(&cpu_syscore_ops); 1647 return 0; 1648 } 1649 core_initcall(init_cpu_syscore); 1650