1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/delay.h> 9 #include <linux/sched.h> 10 #include <linux/init.h> 11 #include <linux/kgdb.h> 12 #include <linux/smp.h> 13 #include <linux/io.h> 14 15 #include <asm/stackprotector.h> 16 #include <asm/perf_counter.h> 17 #include <asm/mmu_context.h> 18 #include <asm/hypervisor.h> 19 #include <asm/processor.h> 20 #include <asm/sections.h> 21 #include <asm/topology.h> 22 #include <asm/cpumask.h> 23 #include <asm/pgtable.h> 24 #include <asm/atomic.h> 25 #include <asm/proto.h> 26 #include <asm/setup.h> 27 #include <asm/apic.h> 28 #include <asm/desc.h> 29 #include <asm/i387.h> 30 #include <asm/mtrr.h> 31 #include <asm/numa.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/mce.h> 35 #include <asm/msr.h> 36 #include <asm/pat.h> 37 #include <asm/smp.h> 38 39 #ifdef CONFIG_X86_LOCAL_APIC 40 #include <asm/uv/uv.h> 41 #endif 42 43 #include "cpu.h" 44 45 /* all of these masks are initialized in setup_cpu_local_masks() */ 46 cpumask_var_t cpu_initialized_mask; 47 cpumask_var_t cpu_callout_mask; 48 cpumask_var_t cpu_callin_mask; 49 50 /* representing cpus for which sibling maps can be computed */ 51 cpumask_var_t cpu_sibling_setup_mask; 52 53 /* correctly size the local cpu masks */ 54 void __init setup_cpu_local_masks(void) 55 { 56 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 57 alloc_bootmem_cpumask_var(&cpu_callin_mask); 58 alloc_bootmem_cpumask_var(&cpu_callout_mask); 59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 60 } 61 62 static const struct cpu_dev *this_cpu __cpuinitdata; 63 64 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 65 #ifdef CONFIG_X86_64 66 /* 67 * We need valid kernel segments for data and code in long mode too 68 * IRET will check the segment types kkeil 2000/10/28 69 * Also sysret mandates a special GDT layout 70 * 71 * TLS descriptors are currently at a different place compared to i386. 72 * Hopefully nobody expects them at a fixed place (Wine?) 73 */ 74 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, 75 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, 76 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, 77 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, 78 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, 79 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, 80 #else 81 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 82 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 83 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 84 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 85 /* 86 * Segments used for calling PnP BIOS have byte granularity. 87 * They code segments and data segments have fixed 64k limits, 88 * the transfer segment sizes are set at run time. 89 */ 90 /* 32-bit code */ 91 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 92 /* 16-bit code */ 93 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 94 /* 16-bit data */ 95 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 96 /* 16-bit data */ 97 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 98 /* 16-bit data */ 99 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 100 /* 101 * The APM segments have byte granularity and their bases 102 * are set at run time. All have 64k limits. 103 */ 104 /* 32-bit code */ 105 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 106 /* 16-bit code */ 107 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 108 /* data */ 109 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 110 111 [GDT_ENTRY_ESPFIX_SS] = { { { 0x0000ffff, 0x00cf9200 } } }, 112 [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, 113 GDT_STACK_CANARY_INIT 114 #endif 115 } }; 116 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 117 118 static int __init x86_xsave_setup(char *s) 119 { 120 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 121 return 1; 122 } 123 __setup("noxsave", x86_xsave_setup); 124 125 #ifdef CONFIG_X86_32 126 static int cachesize_override __cpuinitdata = -1; 127 static int disable_x86_serial_nr __cpuinitdata = 1; 128 129 static int __init cachesize_setup(char *str) 130 { 131 get_option(&str, &cachesize_override); 132 return 1; 133 } 134 __setup("cachesize=", cachesize_setup); 135 136 static int __init x86_fxsr_setup(char *s) 137 { 138 setup_clear_cpu_cap(X86_FEATURE_FXSR); 139 setup_clear_cpu_cap(X86_FEATURE_XMM); 140 return 1; 141 } 142 __setup("nofxsr", x86_fxsr_setup); 143 144 static int __init x86_sep_setup(char *s) 145 { 146 setup_clear_cpu_cap(X86_FEATURE_SEP); 147 return 1; 148 } 149 __setup("nosep", x86_sep_setup); 150 151 /* Standard macro to see if a specific flag is changeable */ 152 static inline int flag_is_changeable_p(u32 flag) 153 { 154 u32 f1, f2; 155 156 /* 157 * Cyrix and IDT cpus allow disabling of CPUID 158 * so the code below may return different results 159 * when it is executed before and after enabling 160 * the CPUID. Add "volatile" to not allow gcc to 161 * optimize the subsequent calls to this function. 162 */ 163 asm volatile ("pushfl \n\t" 164 "pushfl \n\t" 165 "popl %0 \n\t" 166 "movl %0, %1 \n\t" 167 "xorl %2, %0 \n\t" 168 "pushl %0 \n\t" 169 "popfl \n\t" 170 "pushfl \n\t" 171 "popl %0 \n\t" 172 "popfl \n\t" 173 174 : "=&r" (f1), "=&r" (f2) 175 : "ir" (flag)); 176 177 return ((f1^f2) & flag) != 0; 178 } 179 180 /* Probe for the CPUID instruction */ 181 static int __cpuinit have_cpuid_p(void) 182 { 183 return flag_is_changeable_p(X86_EFLAGS_ID); 184 } 185 186 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 187 { 188 unsigned long lo, hi; 189 190 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 191 return; 192 193 /* Disable processor serial number: */ 194 195 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 196 lo |= 0x200000; 197 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 198 199 printk(KERN_NOTICE "CPU serial number disabled.\n"); 200 clear_cpu_cap(c, X86_FEATURE_PN); 201 202 /* Disabling the serial number may affect the cpuid level */ 203 c->cpuid_level = cpuid_eax(0); 204 } 205 206 static int __init x86_serial_nr_setup(char *s) 207 { 208 disable_x86_serial_nr = 0; 209 return 1; 210 } 211 __setup("serialnumber", x86_serial_nr_setup); 212 #else 213 static inline int flag_is_changeable_p(u32 flag) 214 { 215 return 1; 216 } 217 /* Probe for the CPUID instruction */ 218 static inline int have_cpuid_p(void) 219 { 220 return 1; 221 } 222 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 223 { 224 } 225 #endif 226 227 /* 228 * Some CPU features depend on higher CPUID levels, which may not always 229 * be available due to CPUID level capping or broken virtualization 230 * software. Add those features to this table to auto-disable them. 231 */ 232 struct cpuid_dependent_feature { 233 u32 feature; 234 u32 level; 235 }; 236 237 static const struct cpuid_dependent_feature __cpuinitconst 238 cpuid_dependent_features[] = { 239 { X86_FEATURE_MWAIT, 0x00000005 }, 240 { X86_FEATURE_DCA, 0x00000009 }, 241 { X86_FEATURE_XSAVE, 0x0000000d }, 242 { 0, 0 } 243 }; 244 245 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 246 { 247 const struct cpuid_dependent_feature *df; 248 249 for (df = cpuid_dependent_features; df->feature; df++) { 250 251 if (!cpu_has(c, df->feature)) 252 continue; 253 /* 254 * Note: cpuid_level is set to -1 if unavailable, but 255 * extended_extended_level is set to 0 if unavailable 256 * and the legitimate extended levels are all negative 257 * when signed; hence the weird messing around with 258 * signs here... 259 */ 260 if (!((s32)df->level < 0 ? 261 (u32)df->level > (u32)c->extended_cpuid_level : 262 (s32)df->level > (s32)c->cpuid_level)) 263 continue; 264 265 clear_cpu_cap(c, df->feature); 266 if (!warn) 267 continue; 268 269 printk(KERN_WARNING 270 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", 271 x86_cap_flags[df->feature], df->level); 272 } 273 } 274 275 /* 276 * Naming convention should be: <Name> [(<Codename>)] 277 * This table only is used unless init_<vendor>() below doesn't set it; 278 * in particular, if CPUID levels 0x80000002..4 are supported, this 279 * isn't used 280 */ 281 282 /* Look up CPU names by table lookup. */ 283 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) 284 { 285 const struct cpu_model_info *info; 286 287 if (c->x86_model >= 16) 288 return NULL; /* Range check */ 289 290 if (!this_cpu) 291 return NULL; 292 293 info = this_cpu->c_models; 294 295 while (info && info->family) { 296 if (info->family == c->x86) 297 return info->model_names[c->x86_model]; 298 info++; 299 } 300 return NULL; /* Not found */ 301 } 302 303 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; 304 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; 305 306 void load_percpu_segment(int cpu) 307 { 308 #ifdef CONFIG_X86_32 309 loadsegment(fs, __KERNEL_PERCPU); 310 #else 311 loadsegment(gs, 0); 312 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 313 #endif 314 load_stack_canary_segment(); 315 } 316 317 /* 318 * Current gdt points %fs at the "master" per-cpu area: after this, 319 * it's on the real one. 320 */ 321 void switch_to_new_gdt(int cpu) 322 { 323 struct desc_ptr gdt_descr; 324 325 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 326 gdt_descr.size = GDT_SIZE - 1; 327 load_gdt(&gdt_descr); 328 /* Reload the per-cpu base */ 329 330 load_percpu_segment(cpu); 331 } 332 333 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; 334 335 static void __cpuinit default_init(struct cpuinfo_x86 *c) 336 { 337 #ifdef CONFIG_X86_64 338 display_cacheinfo(c); 339 #else 340 /* Not much we can do here... */ 341 /* Check if at least it has cpuid */ 342 if (c->cpuid_level == -1) { 343 /* No cpuid. It must be an ancient CPU */ 344 if (c->x86 == 4) 345 strcpy(c->x86_model_id, "486"); 346 else if (c->x86 == 3) 347 strcpy(c->x86_model_id, "386"); 348 } 349 #endif 350 } 351 352 static const struct cpu_dev __cpuinitconst default_cpu = { 353 .c_init = default_init, 354 .c_vendor = "Unknown", 355 .c_x86_vendor = X86_VENDOR_UNKNOWN, 356 }; 357 358 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 359 { 360 unsigned int *v; 361 char *p, *q; 362 363 if (c->extended_cpuid_level < 0x80000004) 364 return; 365 366 v = (unsigned int *)c->x86_model_id; 367 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 368 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 369 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 370 c->x86_model_id[48] = 0; 371 372 /* 373 * Intel chips right-justify this string for some dumb reason; 374 * undo that brain damage: 375 */ 376 p = q = &c->x86_model_id[0]; 377 while (*p == ' ') 378 p++; 379 if (p != q) { 380 while (*p) 381 *q++ = *p++; 382 while (q <= &c->x86_model_id[48]) 383 *q++ = '\0'; /* Zero-pad the rest */ 384 } 385 } 386 387 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 388 { 389 unsigned int n, dummy, ebx, ecx, edx, l2size; 390 391 n = c->extended_cpuid_level; 392 393 if (n >= 0x80000005) { 394 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 395 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 396 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 397 c->x86_cache_size = (ecx>>24) + (edx>>24); 398 #ifdef CONFIG_X86_64 399 /* On K8 L1 TLB is inclusive, so don't count it */ 400 c->x86_tlbsize = 0; 401 #endif 402 } 403 404 if (n < 0x80000006) /* Some chips just has a large L1. */ 405 return; 406 407 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 408 l2size = ecx >> 16; 409 410 #ifdef CONFIG_X86_64 411 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 412 #else 413 /* do processor-specific cache resizing */ 414 if (this_cpu->c_size_cache) 415 l2size = this_cpu->c_size_cache(c, l2size); 416 417 /* Allow user to override all this if necessary. */ 418 if (cachesize_override != -1) 419 l2size = cachesize_override; 420 421 if (l2size == 0) 422 return; /* Again, no L2 cache is possible */ 423 #endif 424 425 c->x86_cache_size = l2size; 426 427 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 428 l2size, ecx & 0xFF); 429 } 430 431 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 432 { 433 #ifdef CONFIG_X86_HT 434 u32 eax, ebx, ecx, edx; 435 int index_msb, core_bits; 436 437 if (!cpu_has(c, X86_FEATURE_HT)) 438 return; 439 440 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 441 goto out; 442 443 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 444 return; 445 446 cpuid(1, &eax, &ebx, &ecx, &edx); 447 448 smp_num_siblings = (ebx & 0xff0000) >> 16; 449 450 if (smp_num_siblings == 1) { 451 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 452 goto out; 453 } 454 455 if (smp_num_siblings <= 1) 456 goto out; 457 458 if (smp_num_siblings > nr_cpu_ids) { 459 pr_warning("CPU: Unsupported number of siblings %d", 460 smp_num_siblings); 461 smp_num_siblings = 1; 462 return; 463 } 464 465 index_msb = get_count_order(smp_num_siblings); 466 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 467 468 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 469 470 index_msb = get_count_order(smp_num_siblings); 471 472 core_bits = get_count_order(c->x86_max_cores); 473 474 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 475 ((1 << core_bits) - 1); 476 477 out: 478 if ((c->x86_max_cores * smp_num_siblings) > 1) { 479 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 480 c->phys_proc_id); 481 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 482 c->cpu_core_id); 483 } 484 #endif 485 } 486 487 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 488 { 489 char *v = c->x86_vendor_id; 490 int i; 491 492 for (i = 0; i < X86_VENDOR_NUM; i++) { 493 if (!cpu_devs[i]) 494 break; 495 496 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 497 (cpu_devs[i]->c_ident[1] && 498 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 499 500 this_cpu = cpu_devs[i]; 501 c->x86_vendor = this_cpu->c_x86_vendor; 502 return; 503 } 504 } 505 506 printk_once(KERN_ERR 507 "CPU: vendor_id '%s' unknown, using generic init.\n" \ 508 "CPU: Your system may be unstable.\n", v); 509 510 c->x86_vendor = X86_VENDOR_UNKNOWN; 511 this_cpu = &default_cpu; 512 } 513 514 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 515 { 516 /* Get vendor name */ 517 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 518 (unsigned int *)&c->x86_vendor_id[0], 519 (unsigned int *)&c->x86_vendor_id[8], 520 (unsigned int *)&c->x86_vendor_id[4]); 521 522 c->x86 = 4; 523 /* Intel-defined flags: level 0x00000001 */ 524 if (c->cpuid_level >= 0x00000001) { 525 u32 junk, tfms, cap0, misc; 526 527 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 528 c->x86 = (tfms >> 8) & 0xf; 529 c->x86_model = (tfms >> 4) & 0xf; 530 c->x86_mask = tfms & 0xf; 531 532 if (c->x86 == 0xf) 533 c->x86 += (tfms >> 20) & 0xff; 534 if (c->x86 >= 0x6) 535 c->x86_model += ((tfms >> 16) & 0xf) << 4; 536 537 if (cap0 & (1<<19)) { 538 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 539 c->x86_cache_alignment = c->x86_clflush_size; 540 } 541 } 542 } 543 544 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 545 { 546 u32 tfms, xlvl; 547 u32 ebx; 548 549 /* Intel-defined flags: level 0x00000001 */ 550 if (c->cpuid_level >= 0x00000001) { 551 u32 capability, excap; 552 553 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 554 c->x86_capability[0] = capability; 555 c->x86_capability[4] = excap; 556 } 557 558 /* AMD-defined flags: level 0x80000001 */ 559 xlvl = cpuid_eax(0x80000000); 560 c->extended_cpuid_level = xlvl; 561 562 if ((xlvl & 0xffff0000) == 0x80000000) { 563 if (xlvl >= 0x80000001) { 564 c->x86_capability[1] = cpuid_edx(0x80000001); 565 c->x86_capability[6] = cpuid_ecx(0x80000001); 566 } 567 } 568 569 if (c->extended_cpuid_level >= 0x80000008) { 570 u32 eax = cpuid_eax(0x80000008); 571 572 c->x86_virt_bits = (eax >> 8) & 0xff; 573 c->x86_phys_bits = eax & 0xff; 574 } 575 #ifdef CONFIG_X86_32 576 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 577 c->x86_phys_bits = 36; 578 #endif 579 580 if (c->extended_cpuid_level >= 0x80000007) 581 c->x86_power = cpuid_edx(0x80000007); 582 583 } 584 585 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 586 { 587 #ifdef CONFIG_X86_32 588 int i; 589 590 /* 591 * First of all, decide if this is a 486 or higher 592 * It's a 486 if we can modify the AC flag 593 */ 594 if (flag_is_changeable_p(X86_EFLAGS_AC)) 595 c->x86 = 4; 596 else 597 c->x86 = 3; 598 599 for (i = 0; i < X86_VENDOR_NUM; i++) 600 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 601 c->x86_vendor_id[0] = 0; 602 cpu_devs[i]->c_identify(c); 603 if (c->x86_vendor_id[0]) { 604 get_cpu_vendor(c); 605 break; 606 } 607 } 608 #endif 609 } 610 611 /* 612 * Do minimum CPU detection early. 613 * Fields really needed: vendor, cpuid_level, family, model, mask, 614 * cache alignment. 615 * The others are not touched to avoid unwanted side effects. 616 * 617 * WARNING: this function is only called on the BP. Don't add code here 618 * that is supposed to run on all CPUs. 619 */ 620 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 621 { 622 #ifdef CONFIG_X86_64 623 c->x86_clflush_size = 64; 624 c->x86_phys_bits = 36; 625 c->x86_virt_bits = 48; 626 #else 627 c->x86_clflush_size = 32; 628 c->x86_phys_bits = 32; 629 c->x86_virt_bits = 32; 630 #endif 631 c->x86_cache_alignment = c->x86_clflush_size; 632 633 memset(&c->x86_capability, 0, sizeof c->x86_capability); 634 c->extended_cpuid_level = 0; 635 636 if (!have_cpuid_p()) 637 identify_cpu_without_cpuid(c); 638 639 /* cyrix could have cpuid enabled via c_identify()*/ 640 if (!have_cpuid_p()) 641 return; 642 643 cpu_detect(c); 644 645 get_cpu_vendor(c); 646 647 get_cpu_cap(c); 648 649 if (this_cpu->c_early_init) 650 this_cpu->c_early_init(c); 651 652 #ifdef CONFIG_SMP 653 c->cpu_index = boot_cpu_id; 654 #endif 655 filter_cpuid_features(c, false); 656 } 657 658 void __init early_cpu_init(void) 659 { 660 const struct cpu_dev *const *cdev; 661 int count = 0; 662 663 printk(KERN_INFO "KERNEL supported cpus:\n"); 664 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 665 const struct cpu_dev *cpudev = *cdev; 666 unsigned int j; 667 668 if (count >= X86_VENDOR_NUM) 669 break; 670 cpu_devs[count] = cpudev; 671 count++; 672 673 for (j = 0; j < 2; j++) { 674 if (!cpudev->c_ident[j]) 675 continue; 676 printk(KERN_INFO " %s %s\n", cpudev->c_vendor, 677 cpudev->c_ident[j]); 678 } 679 } 680 681 early_identify_cpu(&boot_cpu_data); 682 } 683 684 /* 685 * The NOPL instruction is supposed to exist on all CPUs with 686 * family >= 6; unfortunately, that's not true in practice because 687 * of early VIA chips and (more importantly) broken virtualizers that 688 * are not easy to detect. In the latter case it doesn't even *fail* 689 * reliably, so probing for it doesn't even work. Disable it completely 690 * unless we can find a reliable way to detect all the broken cases. 691 */ 692 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 693 { 694 clear_cpu_cap(c, X86_FEATURE_NOPL); 695 } 696 697 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 698 { 699 c->extended_cpuid_level = 0; 700 701 if (!have_cpuid_p()) 702 identify_cpu_without_cpuid(c); 703 704 /* cyrix could have cpuid enabled via c_identify()*/ 705 if (!have_cpuid_p()) 706 return; 707 708 cpu_detect(c); 709 710 get_cpu_vendor(c); 711 712 get_cpu_cap(c); 713 714 if (c->cpuid_level >= 0x00000001) { 715 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 716 #ifdef CONFIG_X86_32 717 # ifdef CONFIG_X86_HT 718 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 719 # else 720 c->apicid = c->initial_apicid; 721 # endif 722 #endif 723 724 #ifdef CONFIG_X86_HT 725 c->phys_proc_id = c->initial_apicid; 726 #endif 727 } 728 729 get_model_name(c); /* Default name */ 730 731 init_scattered_cpuid_features(c); 732 detect_nopl(c); 733 } 734 735 /* 736 * This does the hard work of actually picking apart the CPU stuff... 737 */ 738 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 739 { 740 int i; 741 742 c->loops_per_jiffy = loops_per_jiffy; 743 c->x86_cache_size = -1; 744 c->x86_vendor = X86_VENDOR_UNKNOWN; 745 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 746 c->x86_vendor_id[0] = '\0'; /* Unset */ 747 c->x86_model_id[0] = '\0'; /* Unset */ 748 c->x86_max_cores = 1; 749 c->x86_coreid_bits = 0; 750 #ifdef CONFIG_X86_64 751 c->x86_clflush_size = 64; 752 c->x86_phys_bits = 36; 753 c->x86_virt_bits = 48; 754 #else 755 c->cpuid_level = -1; /* CPUID not detected */ 756 c->x86_clflush_size = 32; 757 c->x86_phys_bits = 32; 758 c->x86_virt_bits = 32; 759 #endif 760 c->x86_cache_alignment = c->x86_clflush_size; 761 memset(&c->x86_capability, 0, sizeof c->x86_capability); 762 763 generic_identify(c); 764 765 if (this_cpu->c_identify) 766 this_cpu->c_identify(c); 767 768 /* Clear/Set all flags overriden by options, after probe */ 769 for (i = 0; i < NCAPINTS; i++) { 770 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 771 c->x86_capability[i] |= cpu_caps_set[i]; 772 } 773 774 #ifdef CONFIG_X86_64 775 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 776 #endif 777 778 /* 779 * Vendor-specific initialization. In this section we 780 * canonicalize the feature flags, meaning if there are 781 * features a certain CPU supports which CPUID doesn't 782 * tell us, CPUID claiming incorrect flags, or other bugs, 783 * we handle them here. 784 * 785 * At the end of this section, c->x86_capability better 786 * indicate the features this CPU genuinely supports! 787 */ 788 if (this_cpu->c_init) 789 this_cpu->c_init(c); 790 791 /* Disable the PN if appropriate */ 792 squash_the_stupid_serial_number(c); 793 794 /* 795 * The vendor-specific functions might have changed features. 796 * Now we do "generic changes." 797 */ 798 799 /* Filter out anything that depends on CPUID levels we don't have */ 800 filter_cpuid_features(c, true); 801 802 /* If the model name is still unset, do table lookup. */ 803 if (!c->x86_model_id[0]) { 804 const char *p; 805 p = table_lookup_model(c); 806 if (p) 807 strcpy(c->x86_model_id, p); 808 else 809 /* Last resort... */ 810 sprintf(c->x86_model_id, "%02x/%02x", 811 c->x86, c->x86_model); 812 } 813 814 #ifdef CONFIG_X86_64 815 detect_ht(c); 816 #endif 817 818 init_hypervisor(c); 819 820 /* 821 * Clear/Set all flags overriden by options, need do it 822 * before following smp all cpus cap AND. 823 */ 824 for (i = 0; i < NCAPINTS; i++) { 825 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 826 c->x86_capability[i] |= cpu_caps_set[i]; 827 } 828 829 /* 830 * On SMP, boot_cpu_data holds the common feature set between 831 * all CPUs; so make sure that we indicate which features are 832 * common between the CPUs. The first time this routine gets 833 * executed, c == &boot_cpu_data. 834 */ 835 if (c != &boot_cpu_data) { 836 /* AND the already accumulated flags with these */ 837 for (i = 0; i < NCAPINTS; i++) 838 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 839 } 840 841 #ifdef CONFIG_X86_MCE 842 /* Init Machine Check Exception if available. */ 843 mcheck_init(c); 844 #endif 845 846 select_idle_routine(c); 847 848 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 849 numa_add_cpu(smp_processor_id()); 850 #endif 851 852 /* Cap the iomem address space to what is addressable on all CPUs */ 853 iomem_resource.end &= (1ULL << c->x86_phys_bits) - 1; 854 } 855 856 #ifdef CONFIG_X86_64 857 static void vgetcpu_set_mode(void) 858 { 859 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 860 vgetcpu_mode = VGETCPU_RDTSCP; 861 else 862 vgetcpu_mode = VGETCPU_LSL; 863 } 864 #endif 865 866 void __init identify_boot_cpu(void) 867 { 868 identify_cpu(&boot_cpu_data); 869 init_c1e_mask(); 870 #ifdef CONFIG_X86_32 871 sysenter_setup(); 872 enable_sep_cpu(); 873 #else 874 vgetcpu_set_mode(); 875 #endif 876 init_hw_perf_counters(); 877 } 878 879 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 880 { 881 BUG_ON(c == &boot_cpu_data); 882 identify_cpu(c); 883 #ifdef CONFIG_X86_32 884 enable_sep_cpu(); 885 #endif 886 mtrr_ap_init(); 887 } 888 889 struct msr_range { 890 unsigned min; 891 unsigned max; 892 }; 893 894 static const struct msr_range msr_range_array[] __cpuinitconst = { 895 { 0x00000000, 0x00000418}, 896 { 0xc0000000, 0xc000040b}, 897 { 0xc0010000, 0xc0010142}, 898 { 0xc0011000, 0xc001103b}, 899 }; 900 901 static void __cpuinit print_cpu_msr(void) 902 { 903 unsigned index_min, index_max; 904 unsigned index; 905 u64 val; 906 int i; 907 908 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 909 index_min = msr_range_array[i].min; 910 index_max = msr_range_array[i].max; 911 912 for (index = index_min; index < index_max; index++) { 913 if (rdmsrl_amd_safe(index, &val)) 914 continue; 915 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 916 } 917 } 918 } 919 920 static int show_msr __cpuinitdata; 921 922 static __init int setup_show_msr(char *arg) 923 { 924 int num; 925 926 get_option(&arg, &num); 927 928 if (num > 0) 929 show_msr = num; 930 return 1; 931 } 932 __setup("show_msr=", setup_show_msr); 933 934 static __init int setup_noclflush(char *arg) 935 { 936 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 937 return 1; 938 } 939 __setup("noclflush", setup_noclflush); 940 941 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 942 { 943 const char *vendor = NULL; 944 945 if (c->x86_vendor < X86_VENDOR_NUM) { 946 vendor = this_cpu->c_vendor; 947 } else { 948 if (c->cpuid_level >= 0) 949 vendor = c->x86_vendor_id; 950 } 951 952 if (vendor && !strstr(c->x86_model_id, vendor)) 953 printk(KERN_CONT "%s ", vendor); 954 955 if (c->x86_model_id[0]) 956 printk(KERN_CONT "%s", c->x86_model_id); 957 else 958 printk(KERN_CONT "%d86", c->x86); 959 960 if (c->x86_mask || c->cpuid_level >= 0) 961 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 962 else 963 printk(KERN_CONT "\n"); 964 965 #ifdef CONFIG_SMP 966 if (c->cpu_index < show_msr) 967 print_cpu_msr(); 968 #else 969 if (show_msr) 970 print_cpu_msr(); 971 #endif 972 } 973 974 static __init int setup_disablecpuid(char *arg) 975 { 976 int bit; 977 978 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 979 setup_clear_cpu_cap(bit); 980 else 981 return 0; 982 983 return 1; 984 } 985 __setup("clearcpuid=", setup_disablecpuid); 986 987 #ifdef CONFIG_X86_64 988 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; 989 990 DEFINE_PER_CPU_FIRST(union irq_stack_union, 991 irq_stack_union) __aligned(PAGE_SIZE); 992 993 DEFINE_PER_CPU(char *, irq_stack_ptr) = 994 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 995 996 DEFINE_PER_CPU(unsigned long, kernel_stack) = 997 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; 998 EXPORT_PER_CPU_SYMBOL(kernel_stack); 999 1000 DEFINE_PER_CPU(unsigned int, irq_count) = -1; 1001 1002 /* 1003 * Special IST stacks which the CPU switches to when it calls 1004 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1005 * limit), all of them are 4K, except the debug stack which 1006 * is 8K. 1007 */ 1008 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1009 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1010 [DEBUG_STACK - 1] = DEBUG_STKSZ 1011 }; 1012 1013 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1014 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) 1015 __aligned(PAGE_SIZE); 1016 1017 /* May not be marked __init: used by software suspend */ 1018 void syscall_init(void) 1019 { 1020 /* 1021 * LSTAR and STAR live in a bit strange symbiosis. 1022 * They both write to the same internal register. STAR allows to 1023 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1024 */ 1025 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 1026 wrmsrl(MSR_LSTAR, system_call); 1027 wrmsrl(MSR_CSTAR, ignore_sysret); 1028 1029 #ifdef CONFIG_IA32_EMULATION 1030 syscall32_cpu_init(); 1031 #endif 1032 1033 /* Flags to clear on syscall */ 1034 wrmsrl(MSR_SYSCALL_MASK, 1035 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 1036 } 1037 1038 unsigned long kernel_eflags; 1039 1040 /* 1041 * Copies of the original ist values from the tss are only accessed during 1042 * debugging, no special alignment required. 1043 */ 1044 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1045 1046 #else /* CONFIG_X86_64 */ 1047 1048 #ifdef CONFIG_CC_STACKPROTECTOR 1049 DEFINE_PER_CPU(unsigned long, stack_canary); 1050 #endif 1051 1052 /* Make sure %fs and %gs are initialized properly in idle threads */ 1053 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 1054 { 1055 memset(regs, 0, sizeof(struct pt_regs)); 1056 regs->fs = __KERNEL_PERCPU; 1057 regs->gs = __KERNEL_STACK_CANARY; 1058 1059 return regs; 1060 } 1061 #endif /* CONFIG_X86_64 */ 1062 1063 /* 1064 * Clear all 6 debug registers: 1065 */ 1066 static void clear_all_debug_regs(void) 1067 { 1068 int i; 1069 1070 for (i = 0; i < 8; i++) { 1071 /* Ignore db4, db5 */ 1072 if ((i == 4) || (i == 5)) 1073 continue; 1074 1075 set_debugreg(0, i); 1076 } 1077 } 1078 1079 /* 1080 * cpu_init() initializes state that is per-CPU. Some data is already 1081 * initialized (naturally) in the bootstrap process, such as the GDT 1082 * and IDT. We reload them nevertheless, this function acts as a 1083 * 'CPU state barrier', nothing should get across. 1084 * A lot of state is already set up in PDA init for 64 bit 1085 */ 1086 #ifdef CONFIG_X86_64 1087 1088 void __cpuinit cpu_init(void) 1089 { 1090 struct orig_ist *orig_ist; 1091 struct task_struct *me; 1092 struct tss_struct *t; 1093 unsigned long v; 1094 int cpu; 1095 int i; 1096 1097 cpu = stack_smp_processor_id(); 1098 t = &per_cpu(init_tss, cpu); 1099 orig_ist = &per_cpu(orig_ist, cpu); 1100 1101 #ifdef CONFIG_NUMA 1102 if (cpu != 0 && percpu_read(node_number) == 0 && 1103 cpu_to_node(cpu) != NUMA_NO_NODE) 1104 percpu_write(node_number, cpu_to_node(cpu)); 1105 #endif 1106 1107 me = current; 1108 1109 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) 1110 panic("CPU#%d already initialized!\n", cpu); 1111 1112 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1113 1114 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1115 1116 /* 1117 * Initialize the per-CPU GDT with the boot GDT, 1118 * and set up the GDT descriptor: 1119 */ 1120 1121 switch_to_new_gdt(cpu); 1122 loadsegment(fs, 0); 1123 1124 load_idt((const struct desc_ptr *)&idt_descr); 1125 1126 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1127 syscall_init(); 1128 1129 wrmsrl(MSR_FS_BASE, 0); 1130 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1131 barrier(); 1132 1133 check_efer(); 1134 if (cpu != 0) 1135 enable_x2apic(); 1136 1137 /* 1138 * set up and load the per-CPU TSS 1139 */ 1140 if (!orig_ist->ist[0]) { 1141 char *estacks = per_cpu(exception_stacks, cpu); 1142 1143 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1144 estacks += exception_stack_sizes[v]; 1145 orig_ist->ist[v] = t->x86_tss.ist[v] = 1146 (unsigned long)estacks; 1147 } 1148 } 1149 1150 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1151 1152 /* 1153 * <= is required because the CPU will access up to 1154 * 8 bits beyond the end of the IO permission bitmap. 1155 */ 1156 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1157 t->io_bitmap[i] = ~0UL; 1158 1159 atomic_inc(&init_mm.mm_count); 1160 me->active_mm = &init_mm; 1161 BUG_ON(me->mm); 1162 enter_lazy_tlb(&init_mm, me); 1163 1164 load_sp0(t, ¤t->thread); 1165 set_tss_desc(cpu, t); 1166 load_TR_desc(); 1167 load_LDT(&init_mm.context); 1168 1169 #ifdef CONFIG_KGDB 1170 /* 1171 * If the kgdb is connected no debug regs should be altered. This 1172 * is only applicable when KGDB and a KGDB I/O module are built 1173 * into the kernel and you are using early debugging with 1174 * kgdbwait. KGDB will control the kernel HW breakpoint registers. 1175 */ 1176 if (kgdb_connected && arch_kgdb_ops.correct_hw_break) 1177 arch_kgdb_ops.correct_hw_break(); 1178 else 1179 #endif 1180 clear_all_debug_regs(); 1181 1182 fpu_init(); 1183 1184 raw_local_save_flags(kernel_eflags); 1185 1186 if (is_uv_system()) 1187 uv_cpu_init(); 1188 } 1189 1190 #else 1191 1192 void __cpuinit cpu_init(void) 1193 { 1194 int cpu = smp_processor_id(); 1195 struct task_struct *curr = current; 1196 struct tss_struct *t = &per_cpu(init_tss, cpu); 1197 struct thread_struct *thread = &curr->thread; 1198 1199 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { 1200 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1201 for (;;) 1202 local_irq_enable(); 1203 } 1204 1205 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1206 1207 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1208 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1209 1210 load_idt(&idt_descr); 1211 switch_to_new_gdt(cpu); 1212 1213 /* 1214 * Set up and load the per-CPU TSS and LDT 1215 */ 1216 atomic_inc(&init_mm.mm_count); 1217 curr->active_mm = &init_mm; 1218 BUG_ON(curr->mm); 1219 enter_lazy_tlb(&init_mm, curr); 1220 1221 load_sp0(t, thread); 1222 set_tss_desc(cpu, t); 1223 load_TR_desc(); 1224 load_LDT(&init_mm.context); 1225 1226 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1227 1228 #ifdef CONFIG_DOUBLEFAULT 1229 /* Set up doublefault TSS pointer in the GDT */ 1230 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1231 #endif 1232 1233 clear_all_debug_regs(); 1234 1235 /* 1236 * Force FPU initialization: 1237 */ 1238 if (cpu_has_xsave) 1239 current_thread_info()->status = TS_XSAVE; 1240 else 1241 current_thread_info()->status = 0; 1242 clear_used_math(); 1243 mxcsr_feature_mask_init(); 1244 1245 /* 1246 * Boot processor to setup the FP and extended state context info. 1247 */ 1248 if (smp_processor_id() == boot_cpu_id) 1249 init_thread_xstate(); 1250 1251 xsave_init(); 1252 } 1253 #endif 1254