1 #include <linux/init.h> 2 #include <linux/string.h> 3 #include <linux/delay.h> 4 #include <linux/smp.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/bootmem.h> 8 #include <asm/processor.h> 9 #include <asm/i387.h> 10 #include <asm/msr.h> 11 #include <asm/io.h> 12 #include <asm/mmu_context.h> 13 #include <asm/mtrr.h> 14 #include <asm/mce.h> 15 #include <asm/pat.h> 16 #include <asm/asm.h> 17 #ifdef CONFIG_X86_LOCAL_APIC 18 #include <asm/mpspec.h> 19 #include <asm/apic.h> 20 #include <mach_apic.h> 21 #endif 22 23 #include "cpu.h" 24 25 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { 26 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 27 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 28 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 29 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 30 /* 31 * Segments used for calling PnP BIOS have byte granularity. 32 * They code segments and data segments have fixed 64k limits, 33 * the transfer segment sizes are set at run time. 34 */ 35 /* 32-bit code */ 36 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 37 /* 16-bit code */ 38 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 39 /* 16-bit data */ 40 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 41 /* 16-bit data */ 42 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 43 /* 16-bit data */ 44 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 45 /* 46 * The APM segments have byte granularity and their bases 47 * are set at run time. All have 64k limits. 48 */ 49 /* 32-bit code */ 50 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 51 /* 16-bit code */ 52 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 53 /* data */ 54 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 55 56 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, 57 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, 58 } }; 59 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 60 61 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; 62 63 static int cachesize_override __cpuinitdata = -1; 64 static int disable_x86_serial_nr __cpuinitdata = 1; 65 66 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 67 68 static void __cpuinit default_init(struct cpuinfo_x86 *c) 69 { 70 /* Not much we can do here... */ 71 /* Check if at least it has cpuid */ 72 if (c->cpuid_level == -1) { 73 /* No cpuid. It must be an ancient CPU */ 74 if (c->x86 == 4) 75 strcpy(c->x86_model_id, "486"); 76 else if (c->x86 == 3) 77 strcpy(c->x86_model_id, "386"); 78 } 79 } 80 81 static struct cpu_dev __cpuinitdata default_cpu = { 82 .c_init = default_init, 83 .c_vendor = "Unknown", 84 }; 85 static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; 86 87 static int __init cachesize_setup(char *str) 88 { 89 get_option(&str, &cachesize_override); 90 return 1; 91 } 92 __setup("cachesize=", cachesize_setup); 93 94 int __cpuinit get_model_name(struct cpuinfo_x86 *c) 95 { 96 unsigned int *v; 97 char *p, *q; 98 99 if (cpuid_eax(0x80000000) < 0x80000004) 100 return 0; 101 102 v = (unsigned int *) c->x86_model_id; 103 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 104 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 105 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 106 c->x86_model_id[48] = 0; 107 108 /* Intel chips right-justify this string for some dumb reason; 109 undo that brain damage */ 110 p = q = &c->x86_model_id[0]; 111 while (*p == ' ') 112 p++; 113 if (p != q) { 114 while (*p) 115 *q++ = *p++; 116 while (q <= &c->x86_model_id[48]) 117 *q++ = '\0'; /* Zero-pad the rest */ 118 } 119 120 return 1; 121 } 122 123 124 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 125 { 126 unsigned int n, dummy, ecx, edx, l2size; 127 128 n = cpuid_eax(0x80000000); 129 130 if (n >= 0x80000005) { 131 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); 132 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 133 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 134 c->x86_cache_size = (ecx>>24)+(edx>>24); 135 } 136 137 if (n < 0x80000006) /* Some chips just has a large L1. */ 138 return; 139 140 ecx = cpuid_ecx(0x80000006); 141 l2size = ecx >> 16; 142 143 /* do processor-specific cache resizing */ 144 if (this_cpu->c_size_cache) 145 l2size = this_cpu->c_size_cache(c, l2size); 146 147 /* Allow user to override all this if necessary. */ 148 if (cachesize_override != -1) 149 l2size = cachesize_override; 150 151 if (l2size == 0) 152 return; /* Again, no L2 cache is possible */ 153 154 c->x86_cache_size = l2size; 155 156 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 157 l2size, ecx & 0xFF); 158 } 159 160 /* 161 * Naming convention should be: <Name> [(<Codename>)] 162 * This table only is used unless init_<vendor>() below doesn't set it; 163 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used 164 * 165 */ 166 167 /* Look up CPU names by table lookup. */ 168 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) 169 { 170 struct cpu_model_info *info; 171 172 if (c->x86_model >= 16) 173 return NULL; /* Range check */ 174 175 if (!this_cpu) 176 return NULL; 177 178 info = this_cpu->c_models; 179 180 while (info && info->family) { 181 if (info->family == c->x86) 182 return info->model_names[c->x86_model]; 183 info++; 184 } 185 return NULL; /* Not found */ 186 } 187 188 189 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) 190 { 191 char *v = c->x86_vendor_id; 192 int i; 193 static int printed; 194 195 for (i = 0; i < X86_VENDOR_NUM; i++) { 196 if (cpu_devs[i]) { 197 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 198 (cpu_devs[i]->c_ident[1] && 199 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 200 c->x86_vendor = i; 201 if (!early) 202 this_cpu = cpu_devs[i]; 203 return; 204 } 205 } 206 } 207 if (!printed) { 208 printed++; 209 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); 210 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 211 } 212 c->x86_vendor = X86_VENDOR_UNKNOWN; 213 this_cpu = &default_cpu; 214 } 215 216 217 static int __init x86_fxsr_setup(char *s) 218 { 219 setup_clear_cpu_cap(X86_FEATURE_FXSR); 220 setup_clear_cpu_cap(X86_FEATURE_XMM); 221 return 1; 222 } 223 __setup("nofxsr", x86_fxsr_setup); 224 225 226 static int __init x86_sep_setup(char *s) 227 { 228 setup_clear_cpu_cap(X86_FEATURE_SEP); 229 return 1; 230 } 231 __setup("nosep", x86_sep_setup); 232 233 234 /* Standard macro to see if a specific flag is changeable */ 235 static inline int flag_is_changeable_p(u32 flag) 236 { 237 u32 f1, f2; 238 239 asm("pushfl\n\t" 240 "pushfl\n\t" 241 "popl %0\n\t" 242 "movl %0,%1\n\t" 243 "xorl %2,%0\n\t" 244 "pushl %0\n\t" 245 "popfl\n\t" 246 "pushfl\n\t" 247 "popl %0\n\t" 248 "popfl\n\t" 249 : "=&r" (f1), "=&r" (f2) 250 : "ir" (flag)); 251 252 return ((f1^f2) & flag) != 0; 253 } 254 255 256 /* Probe for the CPUID instruction */ 257 static int __cpuinit have_cpuid_p(void) 258 { 259 return flag_is_changeable_p(X86_EFLAGS_ID); 260 } 261 262 void __init cpu_detect(struct cpuinfo_x86 *c) 263 { 264 /* Get vendor name */ 265 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 266 (unsigned int *)&c->x86_vendor_id[0], 267 (unsigned int *)&c->x86_vendor_id[8], 268 (unsigned int *)&c->x86_vendor_id[4]); 269 270 c->x86 = 4; 271 if (c->cpuid_level >= 0x00000001) { 272 u32 junk, tfms, cap0, misc; 273 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 274 c->x86 = (tfms >> 8) & 15; 275 c->x86_model = (tfms >> 4) & 15; 276 if (c->x86 == 0xf) 277 c->x86 += (tfms >> 20) & 0xff; 278 if (c->x86 >= 0x6) 279 c->x86_model += ((tfms >> 16) & 0xF) << 4; 280 c->x86_mask = tfms & 15; 281 if (cap0 & (1<<19)) { 282 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; 283 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 284 } 285 } 286 } 287 static void __cpuinit early_get_cap(struct cpuinfo_x86 *c) 288 { 289 u32 tfms, xlvl; 290 unsigned int ebx; 291 292 memset(&c->x86_capability, 0, sizeof c->x86_capability); 293 if (have_cpuid_p()) { 294 /* Intel-defined flags: level 0x00000001 */ 295 if (c->cpuid_level >= 0x00000001) { 296 u32 capability, excap; 297 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 298 c->x86_capability[0] = capability; 299 c->x86_capability[4] = excap; 300 } 301 302 /* AMD-defined flags: level 0x80000001 */ 303 xlvl = cpuid_eax(0x80000000); 304 if ((xlvl & 0xffff0000) == 0x80000000) { 305 if (xlvl >= 0x80000001) { 306 c->x86_capability[1] = cpuid_edx(0x80000001); 307 c->x86_capability[6] = cpuid_ecx(0x80000001); 308 } 309 } 310 311 } 312 313 } 314 315 /* 316 * Do minimum CPU detection early. 317 * Fields really needed: vendor, cpuid_level, family, model, mask, 318 * cache alignment. 319 * The others are not touched to avoid unwanted side effects. 320 * 321 * WARNING: this function is only called on the BP. Don't add code here 322 * that is supposed to run on all CPUs. 323 */ 324 static void __init early_cpu_detect(void) 325 { 326 struct cpuinfo_x86 *c = &boot_cpu_data; 327 328 c->x86_cache_alignment = 32; 329 c->x86_clflush_size = 32; 330 331 if (!have_cpuid_p()) 332 return; 333 334 cpu_detect(c); 335 336 get_cpu_vendor(c, 1); 337 338 early_get_cap(c); 339 340 if (c->x86_vendor != X86_VENDOR_UNKNOWN && 341 cpu_devs[c->x86_vendor]->c_early_init) 342 cpu_devs[c->x86_vendor]->c_early_init(c); 343 } 344 345 /* 346 * The NOPL instruction is supposed to exist on all CPUs with 347 * family >= 6, unfortunately, that's not true in practice because 348 * of early VIA chips and (more importantly) broken virtualizers that 349 * are not easy to detect. Hence, probe for it based on first 350 * principles. 351 */ 352 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 353 { 354 const u32 nopl_signature = 0x888c53b1; /* Random number */ 355 u32 has_nopl = nopl_signature; 356 357 clear_cpu_cap(c, X86_FEATURE_NOPL); 358 if (c->x86 >= 6) { 359 asm volatile("\n" 360 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ 361 "2:\n" 362 " .section .fixup,\"ax\"\n" 363 "3: xor %0,%0\n" 364 " jmp 2b\n" 365 " .previous\n" 366 _ASM_EXTABLE(1b,3b) 367 : "+a" (has_nopl)); 368 369 if (has_nopl == nopl_signature) 370 set_cpu_cap(c, X86_FEATURE_NOPL); 371 } 372 } 373 374 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 375 { 376 u32 tfms, xlvl; 377 unsigned int ebx; 378 379 if (have_cpuid_p()) { 380 /* Get vendor name */ 381 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 382 (unsigned int *)&c->x86_vendor_id[0], 383 (unsigned int *)&c->x86_vendor_id[8], 384 (unsigned int *)&c->x86_vendor_id[4]); 385 386 get_cpu_vendor(c, 0); 387 /* Initialize the standard set of capabilities */ 388 /* Note that the vendor-specific code below might override */ 389 /* Intel-defined flags: level 0x00000001 */ 390 if (c->cpuid_level >= 0x00000001) { 391 u32 capability, excap; 392 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 393 c->x86_capability[0] = capability; 394 c->x86_capability[4] = excap; 395 c->x86 = (tfms >> 8) & 15; 396 c->x86_model = (tfms >> 4) & 15; 397 if (c->x86 == 0xf) 398 c->x86 += (tfms >> 20) & 0xff; 399 if (c->x86 >= 0x6) 400 c->x86_model += ((tfms >> 16) & 0xF) << 4; 401 c->x86_mask = tfms & 15; 402 c->initial_apicid = (ebx >> 24) & 0xFF; 403 #ifdef CONFIG_X86_HT 404 c->apicid = phys_pkg_id(c->initial_apicid, 0); 405 c->phys_proc_id = c->initial_apicid; 406 #else 407 c->apicid = c->initial_apicid; 408 #endif 409 if (test_cpu_cap(c, X86_FEATURE_CLFLSH)) 410 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; 411 } else { 412 /* Have CPUID level 0 only - unheard of */ 413 c->x86 = 4; 414 } 415 416 /* AMD-defined flags: level 0x80000001 */ 417 xlvl = cpuid_eax(0x80000000); 418 if ((xlvl & 0xffff0000) == 0x80000000) { 419 if (xlvl >= 0x80000001) { 420 c->x86_capability[1] = cpuid_edx(0x80000001); 421 c->x86_capability[6] = cpuid_ecx(0x80000001); 422 } 423 if (xlvl >= 0x80000004) 424 get_model_name(c); /* Default name */ 425 } 426 427 init_scattered_cpuid_features(c); 428 detect_nopl(c); 429 } 430 } 431 432 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 433 { 434 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { 435 /* Disable processor serial number */ 436 unsigned long lo, hi; 437 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 438 lo |= 0x200000; 439 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 440 printk(KERN_NOTICE "CPU serial number disabled.\n"); 441 clear_cpu_cap(c, X86_FEATURE_PN); 442 443 /* Disabling the serial number may affect the cpuid level */ 444 c->cpuid_level = cpuid_eax(0); 445 } 446 } 447 448 static int __init x86_serial_nr_setup(char *s) 449 { 450 disable_x86_serial_nr = 0; 451 return 1; 452 } 453 __setup("serialnumber", x86_serial_nr_setup); 454 455 456 457 /* 458 * This does the hard work of actually picking apart the CPU stuff... 459 */ 460 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 461 { 462 int i; 463 464 c->loops_per_jiffy = loops_per_jiffy; 465 c->x86_cache_size = -1; 466 c->x86_vendor = X86_VENDOR_UNKNOWN; 467 c->cpuid_level = -1; /* CPUID not detected */ 468 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 469 c->x86_vendor_id[0] = '\0'; /* Unset */ 470 c->x86_model_id[0] = '\0'; /* Unset */ 471 c->x86_max_cores = 1; 472 c->x86_clflush_size = 32; 473 memset(&c->x86_capability, 0, sizeof c->x86_capability); 474 475 if (!have_cpuid_p()) { 476 /* 477 * First of all, decide if this is a 486 or higher 478 * It's a 486 if we can modify the AC flag 479 */ 480 if (flag_is_changeable_p(X86_EFLAGS_AC)) 481 c->x86 = 4; 482 else 483 c->x86 = 3; 484 } 485 486 generic_identify(c); 487 488 if (this_cpu->c_identify) 489 this_cpu->c_identify(c); 490 491 /* 492 * Vendor-specific initialization. In this section we 493 * canonicalize the feature flags, meaning if there are 494 * features a certain CPU supports which CPUID doesn't 495 * tell us, CPUID claiming incorrect flags, or other bugs, 496 * we handle them here. 497 * 498 * At the end of this section, c->x86_capability better 499 * indicate the features this CPU genuinely supports! 500 */ 501 if (this_cpu->c_init) 502 this_cpu->c_init(c); 503 504 /* Disable the PN if appropriate */ 505 squash_the_stupid_serial_number(c); 506 507 /* 508 * The vendor-specific functions might have changed features. Now 509 * we do "generic changes." 510 */ 511 512 /* If the model name is still unset, do table lookup. */ 513 if (!c->x86_model_id[0]) { 514 char *p; 515 p = table_lookup_model(c); 516 if (p) 517 strcpy(c->x86_model_id, p); 518 else 519 /* Last resort... */ 520 sprintf(c->x86_model_id, "%02x/%02x", 521 c->x86, c->x86_model); 522 } 523 524 /* 525 * On SMP, boot_cpu_data holds the common feature set between 526 * all CPUs; so make sure that we indicate which features are 527 * common between the CPUs. The first time this routine gets 528 * executed, c == &boot_cpu_data. 529 */ 530 if (c != &boot_cpu_data) { 531 /* AND the already accumulated flags with these */ 532 for (i = 0 ; i < NCAPINTS ; i++) 533 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 534 } 535 536 /* Clear all flags overriden by options */ 537 for (i = 0; i < NCAPINTS; i++) 538 c->x86_capability[i] &= ~cleared_cpu_caps[i]; 539 540 /* Init Machine Check Exception if available. */ 541 mcheck_init(c); 542 543 select_idle_routine(c); 544 } 545 546 void __init identify_boot_cpu(void) 547 { 548 identify_cpu(&boot_cpu_data); 549 sysenter_setup(); 550 enable_sep_cpu(); 551 } 552 553 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 554 { 555 BUG_ON(c == &boot_cpu_data); 556 identify_cpu(c); 557 enable_sep_cpu(); 558 mtrr_ap_init(); 559 } 560 561 #ifdef CONFIG_X86_HT 562 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 563 { 564 u32 eax, ebx, ecx, edx; 565 int index_msb, core_bits; 566 567 cpuid(1, &eax, &ebx, &ecx, &edx); 568 569 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) 570 return; 571 572 smp_num_siblings = (ebx & 0xff0000) >> 16; 573 574 if (smp_num_siblings == 1) { 575 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 576 } else if (smp_num_siblings > 1) { 577 578 if (smp_num_siblings > NR_CPUS) { 579 printk(KERN_WARNING "CPU: Unsupported number of the " 580 "siblings %d", smp_num_siblings); 581 smp_num_siblings = 1; 582 return; 583 } 584 585 index_msb = get_count_order(smp_num_siblings); 586 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); 587 588 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 589 c->phys_proc_id); 590 591 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 592 593 index_msb = get_count_order(smp_num_siblings) ; 594 595 core_bits = get_count_order(c->x86_max_cores); 596 597 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & 598 ((1 << core_bits) - 1); 599 600 if (c->x86_max_cores > 1) 601 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 602 c->cpu_core_id); 603 } 604 } 605 #endif 606 607 static __init int setup_noclflush(char *arg) 608 { 609 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 610 return 1; 611 } 612 __setup("noclflush", setup_noclflush); 613 614 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 615 { 616 char *vendor = NULL; 617 618 if (c->x86_vendor < X86_VENDOR_NUM) 619 vendor = this_cpu->c_vendor; 620 else if (c->cpuid_level >= 0) 621 vendor = c->x86_vendor_id; 622 623 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) 624 printk("%s ", vendor); 625 626 if (!c->x86_model_id[0]) 627 printk("%d86", c->x86); 628 else 629 printk("%s", c->x86_model_id); 630 631 if (c->x86_mask || c->cpuid_level >= 0) 632 printk(" stepping %02x\n", c->x86_mask); 633 else 634 printk("\n"); 635 } 636 637 static __init int setup_disablecpuid(char *arg) 638 { 639 int bit; 640 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 641 setup_clear_cpu_cap(bit); 642 else 643 return 0; 644 return 1; 645 } 646 __setup("clearcpuid=", setup_disablecpuid); 647 648 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; 649 650 void __init early_cpu_init(void) 651 { 652 struct cpu_vendor_dev *cvdev; 653 654 for (cvdev = __x86cpuvendor_start ; 655 cvdev < __x86cpuvendor_end ; 656 cvdev++) 657 cpu_devs[cvdev->vendor] = cvdev->cpu_dev; 658 659 early_cpu_detect(); 660 validate_pat_support(&boot_cpu_data); 661 } 662 663 /* Make sure %fs is initialized properly in idle threads */ 664 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 665 { 666 memset(regs, 0, sizeof(struct pt_regs)); 667 regs->fs = __KERNEL_PERCPU; 668 return regs; 669 } 670 671 /* Current gdt points %fs at the "master" per-cpu area: after this, 672 * it's on the real one. */ 673 void switch_to_new_gdt(void) 674 { 675 struct desc_ptr gdt_descr; 676 677 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); 678 gdt_descr.size = GDT_SIZE - 1; 679 load_gdt(&gdt_descr); 680 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); 681 } 682 683 /* 684 * cpu_init() initializes state that is per-CPU. Some data is already 685 * initialized (naturally) in the bootstrap process, such as the GDT 686 * and IDT. We reload them nevertheless, this function acts as a 687 * 'CPU state barrier', nothing should get across. 688 */ 689 void __cpuinit cpu_init(void) 690 { 691 int cpu = smp_processor_id(); 692 struct task_struct *curr = current; 693 struct tss_struct *t = &per_cpu(init_tss, cpu); 694 struct thread_struct *thread = &curr->thread; 695 696 if (cpu_test_and_set(cpu, cpu_initialized)) { 697 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 698 for (;;) local_irq_enable(); 699 } 700 701 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 702 703 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 704 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 705 706 load_idt(&idt_descr); 707 switch_to_new_gdt(); 708 709 /* 710 * Set up and load the per-CPU TSS and LDT 711 */ 712 atomic_inc(&init_mm.mm_count); 713 curr->active_mm = &init_mm; 714 if (curr->mm) 715 BUG(); 716 enter_lazy_tlb(&init_mm, curr); 717 718 load_sp0(t, thread); 719 set_tss_desc(cpu, t); 720 load_TR_desc(); 721 load_LDT(&init_mm.context); 722 723 #ifdef CONFIG_DOUBLEFAULT 724 /* Set up doublefault TSS pointer in the GDT */ 725 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 726 #endif 727 728 /* Clear %gs. */ 729 asm volatile ("mov %0, %%gs" : : "r" (0)); 730 731 /* Clear all 6 debug registers: */ 732 set_debugreg(0, 0); 733 set_debugreg(0, 1); 734 set_debugreg(0, 2); 735 set_debugreg(0, 3); 736 set_debugreg(0, 6); 737 set_debugreg(0, 7); 738 739 /* 740 * Force FPU initialization: 741 */ 742 current_thread_info()->status = 0; 743 clear_used_math(); 744 mxcsr_feature_mask_init(); 745 } 746 747 #ifdef CONFIG_HOTPLUG_CPU 748 void __cpuinit cpu_uninit(void) 749 { 750 int cpu = raw_smp_processor_id(); 751 cpu_clear(cpu, cpu_initialized); 752 753 /* lazy TLB state */ 754 per_cpu(cpu_tlbstate, cpu).state = 0; 755 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; 756 } 757 #endif 758