1 #include <linux/init.h> 2 #include <linux/kernel.h> 3 #include <linux/sched.h> 4 #include <linux/string.h> 5 #include <linux/bootmem.h> 6 #include <linux/bitops.h> 7 #include <linux/module.h> 8 #include <linux/kgdb.h> 9 #include <linux/topology.h> 10 #include <linux/delay.h> 11 #include <linux/smp.h> 12 #include <linux/percpu.h> 13 #include <asm/i387.h> 14 #include <asm/msr.h> 15 #include <asm/io.h> 16 #include <asm/linkage.h> 17 #include <asm/mmu_context.h> 18 #include <asm/mtrr.h> 19 #include <asm/mce.h> 20 #include <asm/pat.h> 21 #include <asm/asm.h> 22 #include <asm/numa.h> 23 #ifdef CONFIG_X86_LOCAL_APIC 24 #include <asm/mpspec.h> 25 #include <asm/apic.h> 26 #include <mach_apic.h> 27 #include <asm/genapic.h> 28 #endif 29 30 #include <asm/pda.h> 31 #include <asm/pgtable.h> 32 #include <asm/processor.h> 33 #include <asm/desc.h> 34 #include <asm/atomic.h> 35 #include <asm/proto.h> 36 #include <asm/sections.h> 37 #include <asm/setup.h> 38 39 #include "cpu.h" 40 41 static struct cpu_dev *this_cpu __cpuinitdata; 42 43 #ifdef CONFIG_X86_64 44 /* We need valid kernel segments for data and code in long mode too 45 * IRET will check the segment types kkeil 2000/10/28 46 * Also sysret mandates a special GDT layout 47 */ 48 /* The TLS descriptors are currently at a different place compared to i386. 49 Hopefully nobody expects them at a fixed place (Wine?) */ 50 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { 51 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, 52 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, 53 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, 54 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, 55 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, 56 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, 57 } }; 58 #else 59 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 60 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, 61 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, 62 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, 63 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, 64 /* 65 * Segments used for calling PnP BIOS have byte granularity. 66 * They code segments and data segments have fixed 64k limits, 67 * the transfer segment sizes are set at run time. 68 */ 69 /* 32-bit code */ 70 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, 71 /* 16-bit code */ 72 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, 73 /* 16-bit data */ 74 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, 75 /* 16-bit data */ 76 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, 77 /* 16-bit data */ 78 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, 79 /* 80 * The APM segments have byte granularity and their bases 81 * are set at run time. All have 64k limits. 82 */ 83 /* 32-bit code */ 84 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, 85 /* 16-bit code */ 86 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, 87 /* data */ 88 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, 89 90 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, 91 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, 92 } }; 93 #endif 94 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 95 96 #ifdef CONFIG_X86_32 97 static int cachesize_override __cpuinitdata = -1; 98 static int disable_x86_serial_nr __cpuinitdata = 1; 99 100 static int __init cachesize_setup(char *str) 101 { 102 get_option(&str, &cachesize_override); 103 return 1; 104 } 105 __setup("cachesize=", cachesize_setup); 106 107 static int __init x86_fxsr_setup(char *s) 108 { 109 setup_clear_cpu_cap(X86_FEATURE_FXSR); 110 setup_clear_cpu_cap(X86_FEATURE_XMM); 111 return 1; 112 } 113 __setup("nofxsr", x86_fxsr_setup); 114 115 static int __init x86_sep_setup(char *s) 116 { 117 setup_clear_cpu_cap(X86_FEATURE_SEP); 118 return 1; 119 } 120 __setup("nosep", x86_sep_setup); 121 122 /* Standard macro to see if a specific flag is changeable */ 123 static inline int flag_is_changeable_p(u32 flag) 124 { 125 u32 f1, f2; 126 127 /* 128 * Cyrix and IDT cpus allow disabling of CPUID 129 * so the code below may return different results 130 * when it is executed before and after enabling 131 * the CPUID. Add "volatile" to not allow gcc to 132 * optimize the subsequent calls to this function. 133 */ 134 asm volatile ("pushfl\n\t" 135 "pushfl\n\t" 136 "popl %0\n\t" 137 "movl %0,%1\n\t" 138 "xorl %2,%0\n\t" 139 "pushl %0\n\t" 140 "popfl\n\t" 141 "pushfl\n\t" 142 "popl %0\n\t" 143 "popfl\n\t" 144 : "=&r" (f1), "=&r" (f2) 145 : "ir" (flag)); 146 147 return ((f1^f2) & flag) != 0; 148 } 149 150 /* Probe for the CPUID instruction */ 151 static int __cpuinit have_cpuid_p(void) 152 { 153 return flag_is_changeable_p(X86_EFLAGS_ID); 154 } 155 156 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 157 { 158 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { 159 /* Disable processor serial number */ 160 unsigned long lo, hi; 161 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 162 lo |= 0x200000; 163 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 164 printk(KERN_NOTICE "CPU serial number disabled.\n"); 165 clear_cpu_cap(c, X86_FEATURE_PN); 166 167 /* Disabling the serial number may affect the cpuid level */ 168 c->cpuid_level = cpuid_eax(0); 169 } 170 } 171 172 static int __init x86_serial_nr_setup(char *s) 173 { 174 disable_x86_serial_nr = 0; 175 return 1; 176 } 177 __setup("serialnumber", x86_serial_nr_setup); 178 #else 179 static inline int flag_is_changeable_p(u32 flag) 180 { 181 return 1; 182 } 183 /* Probe for the CPUID instruction */ 184 static inline int have_cpuid_p(void) 185 { 186 return 1; 187 } 188 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 189 { 190 } 191 #endif 192 193 /* 194 * Naming convention should be: <Name> [(<Codename>)] 195 * This table only is used unless init_<vendor>() below doesn't set it; 196 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used 197 * 198 */ 199 200 /* Look up CPU names by table lookup. */ 201 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) 202 { 203 struct cpu_model_info *info; 204 205 if (c->x86_model >= 16) 206 return NULL; /* Range check */ 207 208 if (!this_cpu) 209 return NULL; 210 211 info = this_cpu->c_models; 212 213 while (info && info->family) { 214 if (info->family == c->x86) 215 return info->model_names[c->x86_model]; 216 info++; 217 } 218 return NULL; /* Not found */ 219 } 220 221 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; 222 223 /* Current gdt points %fs at the "master" per-cpu area: after this, 224 * it's on the real one. */ 225 void switch_to_new_gdt(void) 226 { 227 struct desc_ptr gdt_descr; 228 229 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); 230 gdt_descr.size = GDT_SIZE - 1; 231 load_gdt(&gdt_descr); 232 #ifdef CONFIG_X86_32 233 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); 234 #endif 235 } 236 237 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 238 239 static void __cpuinit default_init(struct cpuinfo_x86 *c) 240 { 241 #ifdef CONFIG_X86_64 242 display_cacheinfo(c); 243 #else 244 /* Not much we can do here... */ 245 /* Check if at least it has cpuid */ 246 if (c->cpuid_level == -1) { 247 /* No cpuid. It must be an ancient CPU */ 248 if (c->x86 == 4) 249 strcpy(c->x86_model_id, "486"); 250 else if (c->x86 == 3) 251 strcpy(c->x86_model_id, "386"); 252 } 253 #endif 254 } 255 256 static struct cpu_dev __cpuinitdata default_cpu = { 257 .c_init = default_init, 258 .c_vendor = "Unknown", 259 .c_x86_vendor = X86_VENDOR_UNKNOWN, 260 }; 261 262 static void __cpuinit get_model_name(struct cpuinfo_x86 *c) 263 { 264 unsigned int *v; 265 char *p, *q; 266 267 if (c->extended_cpuid_level < 0x80000004) 268 return; 269 270 v = (unsigned int *) c->x86_model_id; 271 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 272 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 273 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 274 c->x86_model_id[48] = 0; 275 276 /* Intel chips right-justify this string for some dumb reason; 277 undo that brain damage */ 278 p = q = &c->x86_model_id[0]; 279 while (*p == ' ') 280 p++; 281 if (p != q) { 282 while (*p) 283 *q++ = *p++; 284 while (q <= &c->x86_model_id[48]) 285 *q++ = '\0'; /* Zero-pad the rest */ 286 } 287 } 288 289 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 290 { 291 unsigned int n, dummy, ebx, ecx, edx, l2size; 292 293 n = c->extended_cpuid_level; 294 295 if (n >= 0x80000005) { 296 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 297 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 298 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 299 c->x86_cache_size = (ecx>>24) + (edx>>24); 300 #ifdef CONFIG_X86_64 301 /* On K8 L1 TLB is inclusive, so don't count it */ 302 c->x86_tlbsize = 0; 303 #endif 304 } 305 306 if (n < 0x80000006) /* Some chips just has a large L1. */ 307 return; 308 309 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 310 l2size = ecx >> 16; 311 312 #ifdef CONFIG_X86_64 313 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 314 #else 315 /* do processor-specific cache resizing */ 316 if (this_cpu->c_size_cache) 317 l2size = this_cpu->c_size_cache(c, l2size); 318 319 /* Allow user to override all this if necessary. */ 320 if (cachesize_override != -1) 321 l2size = cachesize_override; 322 323 if (l2size == 0) 324 return; /* Again, no L2 cache is possible */ 325 #endif 326 327 c->x86_cache_size = l2size; 328 329 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", 330 l2size, ecx & 0xFF); 331 } 332 333 void __cpuinit detect_ht(struct cpuinfo_x86 *c) 334 { 335 #ifdef CONFIG_X86_HT 336 u32 eax, ebx, ecx, edx; 337 int index_msb, core_bits; 338 339 if (!cpu_has(c, X86_FEATURE_HT)) 340 return; 341 342 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 343 goto out; 344 345 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 346 return; 347 348 cpuid(1, &eax, &ebx, &ecx, &edx); 349 350 smp_num_siblings = (ebx & 0xff0000) >> 16; 351 352 if (smp_num_siblings == 1) { 353 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); 354 } else if (smp_num_siblings > 1) { 355 356 if (smp_num_siblings > NR_CPUS) { 357 printk(KERN_WARNING "CPU: Unsupported number of siblings %d", 358 smp_num_siblings); 359 smp_num_siblings = 1; 360 return; 361 } 362 363 index_msb = get_count_order(smp_num_siblings); 364 #ifdef CONFIG_X86_64 365 c->phys_proc_id = phys_pkg_id(index_msb); 366 #else 367 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); 368 #endif 369 370 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 371 372 index_msb = get_count_order(smp_num_siblings); 373 374 core_bits = get_count_order(c->x86_max_cores); 375 376 #ifdef CONFIG_X86_64 377 c->cpu_core_id = phys_pkg_id(index_msb) & 378 ((1 << core_bits) - 1); 379 #else 380 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & 381 ((1 << core_bits) - 1); 382 #endif 383 } 384 385 out: 386 if ((c->x86_max_cores * smp_num_siblings) > 1) { 387 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", 388 c->phys_proc_id); 389 printk(KERN_INFO "CPU: Processor Core ID: %d\n", 390 c->cpu_core_id); 391 } 392 #endif 393 } 394 395 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 396 { 397 char *v = c->x86_vendor_id; 398 int i; 399 static int printed; 400 401 for (i = 0; i < X86_VENDOR_NUM; i++) { 402 if (!cpu_devs[i]) 403 break; 404 405 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 406 (cpu_devs[i]->c_ident[1] && 407 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 408 this_cpu = cpu_devs[i]; 409 c->x86_vendor = this_cpu->c_x86_vendor; 410 return; 411 } 412 } 413 414 if (!printed) { 415 printed++; 416 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); 417 printk(KERN_ERR "CPU: Your system may be unstable.\n"); 418 } 419 420 c->x86_vendor = X86_VENDOR_UNKNOWN; 421 this_cpu = &default_cpu; 422 } 423 424 void __cpuinit cpu_detect(struct cpuinfo_x86 *c) 425 { 426 /* Get vendor name */ 427 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 428 (unsigned int *)&c->x86_vendor_id[0], 429 (unsigned int *)&c->x86_vendor_id[8], 430 (unsigned int *)&c->x86_vendor_id[4]); 431 432 c->x86 = 4; 433 /* Intel-defined flags: level 0x00000001 */ 434 if (c->cpuid_level >= 0x00000001) { 435 u32 junk, tfms, cap0, misc; 436 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 437 c->x86 = (tfms >> 8) & 0xf; 438 c->x86_model = (tfms >> 4) & 0xf; 439 c->x86_mask = tfms & 0xf; 440 if (c->x86 == 0xf) 441 c->x86 += (tfms >> 20) & 0xff; 442 if (c->x86 >= 0x6) 443 c->x86_model += ((tfms >> 16) & 0xf) << 4; 444 if (cap0 & (1<<19)) { 445 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 446 c->x86_cache_alignment = c->x86_clflush_size; 447 } 448 } 449 } 450 451 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 452 { 453 u32 tfms, xlvl; 454 u32 ebx; 455 456 /* Intel-defined flags: level 0x00000001 */ 457 if (c->cpuid_level >= 0x00000001) { 458 u32 capability, excap; 459 cpuid(0x00000001, &tfms, &ebx, &excap, &capability); 460 c->x86_capability[0] = capability; 461 c->x86_capability[4] = excap; 462 } 463 464 /* AMD-defined flags: level 0x80000001 */ 465 xlvl = cpuid_eax(0x80000000); 466 c->extended_cpuid_level = xlvl; 467 if ((xlvl & 0xffff0000) == 0x80000000) { 468 if (xlvl >= 0x80000001) { 469 c->x86_capability[1] = cpuid_edx(0x80000001); 470 c->x86_capability[6] = cpuid_ecx(0x80000001); 471 } 472 } 473 474 #ifdef CONFIG_X86_64 475 if (c->extended_cpuid_level >= 0x80000008) { 476 u32 eax = cpuid_eax(0x80000008); 477 478 c->x86_virt_bits = (eax >> 8) & 0xff; 479 c->x86_phys_bits = eax & 0xff; 480 } 481 #endif 482 483 if (c->extended_cpuid_level >= 0x80000007) 484 c->x86_power = cpuid_edx(0x80000007); 485 486 } 487 488 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 489 { 490 #ifdef CONFIG_X86_32 491 int i; 492 493 /* 494 * First of all, decide if this is a 486 or higher 495 * It's a 486 if we can modify the AC flag 496 */ 497 if (flag_is_changeable_p(X86_EFLAGS_AC)) 498 c->x86 = 4; 499 else 500 c->x86 = 3; 501 502 for (i = 0; i < X86_VENDOR_NUM; i++) 503 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 504 c->x86_vendor_id[0] = 0; 505 cpu_devs[i]->c_identify(c); 506 if (c->x86_vendor_id[0]) { 507 get_cpu_vendor(c); 508 break; 509 } 510 } 511 #endif 512 } 513 514 /* 515 * Do minimum CPU detection early. 516 * Fields really needed: vendor, cpuid_level, family, model, mask, 517 * cache alignment. 518 * The others are not touched to avoid unwanted side effects. 519 * 520 * WARNING: this function is only called on the BP. Don't add code here 521 * that is supposed to run on all CPUs. 522 */ 523 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 524 { 525 #ifdef CONFIG_X86_64 526 c->x86_clflush_size = 64; 527 #else 528 c->x86_clflush_size = 32; 529 #endif 530 c->x86_cache_alignment = c->x86_clflush_size; 531 532 memset(&c->x86_capability, 0, sizeof c->x86_capability); 533 c->extended_cpuid_level = 0; 534 535 if (!have_cpuid_p()) 536 identify_cpu_without_cpuid(c); 537 538 /* cyrix could have cpuid enabled via c_identify()*/ 539 if (!have_cpuid_p()) 540 return; 541 542 cpu_detect(c); 543 544 get_cpu_vendor(c); 545 546 get_cpu_cap(c); 547 548 if (this_cpu->c_early_init) 549 this_cpu->c_early_init(c); 550 551 validate_pat_support(c); 552 } 553 554 void __init early_cpu_init(void) 555 { 556 struct cpu_dev **cdev; 557 int count = 0; 558 559 printk("KERNEL supported cpus:\n"); 560 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 561 struct cpu_dev *cpudev = *cdev; 562 unsigned int j; 563 564 if (count >= X86_VENDOR_NUM) 565 break; 566 cpu_devs[count] = cpudev; 567 count++; 568 569 for (j = 0; j < 2; j++) { 570 if (!cpudev->c_ident[j]) 571 continue; 572 printk(" %s %s\n", cpudev->c_vendor, 573 cpudev->c_ident[j]); 574 } 575 } 576 577 early_identify_cpu(&boot_cpu_data); 578 } 579 580 /* 581 * The NOPL instruction is supposed to exist on all CPUs with 582 * family >= 6; unfortunately, that's not true in practice because 583 * of early VIA chips and (more importantly) broken virtualizers that 584 * are not easy to detect. In the latter case it doesn't even *fail* 585 * reliably, so probing for it doesn't even work. Disable it completely 586 * unless we can find a reliable way to detect all the broken cases. 587 */ 588 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) 589 { 590 clear_cpu_cap(c, X86_FEATURE_NOPL); 591 } 592 593 static void __cpuinit generic_identify(struct cpuinfo_x86 *c) 594 { 595 c->extended_cpuid_level = 0; 596 597 if (!have_cpuid_p()) 598 identify_cpu_without_cpuid(c); 599 600 /* cyrix could have cpuid enabled via c_identify()*/ 601 if (!have_cpuid_p()) 602 return; 603 604 cpu_detect(c); 605 606 get_cpu_vendor(c); 607 608 get_cpu_cap(c); 609 610 if (c->cpuid_level >= 0x00000001) { 611 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 612 #ifdef CONFIG_X86_32 613 # ifdef CONFIG_X86_HT 614 c->apicid = phys_pkg_id(c->initial_apicid, 0); 615 # else 616 c->apicid = c->initial_apicid; 617 # endif 618 #endif 619 620 #ifdef CONFIG_X86_HT 621 c->phys_proc_id = c->initial_apicid; 622 #endif 623 } 624 625 get_model_name(c); /* Default name */ 626 627 init_scattered_cpuid_features(c); 628 detect_nopl(c); 629 } 630 631 /* 632 * This does the hard work of actually picking apart the CPU stuff... 633 */ 634 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) 635 { 636 int i; 637 638 c->loops_per_jiffy = loops_per_jiffy; 639 c->x86_cache_size = -1; 640 c->x86_vendor = X86_VENDOR_UNKNOWN; 641 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 642 c->x86_vendor_id[0] = '\0'; /* Unset */ 643 c->x86_model_id[0] = '\0'; /* Unset */ 644 c->x86_max_cores = 1; 645 c->x86_coreid_bits = 0; 646 #ifdef CONFIG_X86_64 647 c->x86_clflush_size = 64; 648 #else 649 c->cpuid_level = -1; /* CPUID not detected */ 650 c->x86_clflush_size = 32; 651 #endif 652 c->x86_cache_alignment = c->x86_clflush_size; 653 memset(&c->x86_capability, 0, sizeof c->x86_capability); 654 655 generic_identify(c); 656 657 if (this_cpu->c_identify) 658 this_cpu->c_identify(c); 659 660 #ifdef CONFIG_X86_64 661 c->apicid = phys_pkg_id(0); 662 #endif 663 664 /* 665 * Vendor-specific initialization. In this section we 666 * canonicalize the feature flags, meaning if there are 667 * features a certain CPU supports which CPUID doesn't 668 * tell us, CPUID claiming incorrect flags, or other bugs, 669 * we handle them here. 670 * 671 * At the end of this section, c->x86_capability better 672 * indicate the features this CPU genuinely supports! 673 */ 674 if (this_cpu->c_init) 675 this_cpu->c_init(c); 676 677 /* Disable the PN if appropriate */ 678 squash_the_stupid_serial_number(c); 679 680 /* 681 * The vendor-specific functions might have changed features. Now 682 * we do "generic changes." 683 */ 684 685 /* If the model name is still unset, do table lookup. */ 686 if (!c->x86_model_id[0]) { 687 char *p; 688 p = table_lookup_model(c); 689 if (p) 690 strcpy(c->x86_model_id, p); 691 else 692 /* Last resort... */ 693 sprintf(c->x86_model_id, "%02x/%02x", 694 c->x86, c->x86_model); 695 } 696 697 #ifdef CONFIG_X86_64 698 detect_ht(c); 699 #endif 700 701 /* 702 * On SMP, boot_cpu_data holds the common feature set between 703 * all CPUs; so make sure that we indicate which features are 704 * common between the CPUs. The first time this routine gets 705 * executed, c == &boot_cpu_data. 706 */ 707 if (c != &boot_cpu_data) { 708 /* AND the already accumulated flags with these */ 709 for (i = 0; i < NCAPINTS; i++) 710 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 711 } 712 713 /* Clear all flags overriden by options */ 714 for (i = 0; i < NCAPINTS; i++) 715 c->x86_capability[i] &= ~cleared_cpu_caps[i]; 716 717 #ifdef CONFIG_X86_MCE 718 /* Init Machine Check Exception if available. */ 719 mcheck_init(c); 720 #endif 721 722 select_idle_routine(c); 723 724 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) 725 numa_add_cpu(smp_processor_id()); 726 #endif 727 } 728 729 #ifdef CONFIG_X86_64 730 static void vgetcpu_set_mode(void) 731 { 732 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) 733 vgetcpu_mode = VGETCPU_RDTSCP; 734 else 735 vgetcpu_mode = VGETCPU_LSL; 736 } 737 #endif 738 739 void __init identify_boot_cpu(void) 740 { 741 identify_cpu(&boot_cpu_data); 742 #ifdef CONFIG_X86_32 743 sysenter_setup(); 744 enable_sep_cpu(); 745 #else 746 vgetcpu_set_mode(); 747 #endif 748 } 749 750 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) 751 { 752 BUG_ON(c == &boot_cpu_data); 753 identify_cpu(c); 754 #ifdef CONFIG_X86_32 755 enable_sep_cpu(); 756 #endif 757 mtrr_ap_init(); 758 } 759 760 struct msr_range { 761 unsigned min; 762 unsigned max; 763 }; 764 765 static struct msr_range msr_range_array[] __cpuinitdata = { 766 { 0x00000000, 0x00000418}, 767 { 0xc0000000, 0xc000040b}, 768 { 0xc0010000, 0xc0010142}, 769 { 0xc0011000, 0xc001103b}, 770 }; 771 772 static void __cpuinit print_cpu_msr(void) 773 { 774 unsigned index; 775 u64 val; 776 int i; 777 unsigned index_min, index_max; 778 779 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 780 index_min = msr_range_array[i].min; 781 index_max = msr_range_array[i].max; 782 for (index = index_min; index < index_max; index++) { 783 if (rdmsrl_amd_safe(index, &val)) 784 continue; 785 printk(KERN_INFO " MSR%08x: %016llx\n", index, val); 786 } 787 } 788 } 789 790 static int show_msr __cpuinitdata; 791 static __init int setup_show_msr(char *arg) 792 { 793 int num; 794 795 get_option(&arg, &num); 796 797 if (num > 0) 798 show_msr = num; 799 return 1; 800 } 801 __setup("show_msr=", setup_show_msr); 802 803 static __init int setup_noclflush(char *arg) 804 { 805 setup_clear_cpu_cap(X86_FEATURE_CLFLSH); 806 return 1; 807 } 808 __setup("noclflush", setup_noclflush); 809 810 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) 811 { 812 char *vendor = NULL; 813 814 if (c->x86_vendor < X86_VENDOR_NUM) 815 vendor = this_cpu->c_vendor; 816 else if (c->cpuid_level >= 0) 817 vendor = c->x86_vendor_id; 818 819 if (vendor && !strstr(c->x86_model_id, vendor)) 820 printk(KERN_CONT "%s ", vendor); 821 822 if (c->x86_model_id[0]) 823 printk(KERN_CONT "%s", c->x86_model_id); 824 else 825 printk(KERN_CONT "%d86", c->x86); 826 827 if (c->x86_mask || c->cpuid_level >= 0) 828 printk(KERN_CONT " stepping %02x\n", c->x86_mask); 829 else 830 printk(KERN_CONT "\n"); 831 832 #ifdef CONFIG_SMP 833 if (c->cpu_index < show_msr) 834 print_cpu_msr(); 835 #else 836 if (show_msr) 837 print_cpu_msr(); 838 #endif 839 } 840 841 static __init int setup_disablecpuid(char *arg) 842 { 843 int bit; 844 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 845 setup_clear_cpu_cap(bit); 846 else 847 return 0; 848 return 1; 849 } 850 __setup("clearcpuid=", setup_disablecpuid); 851 852 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; 853 854 #ifdef CONFIG_X86_64 855 struct x8664_pda **_cpu_pda __read_mostly; 856 EXPORT_SYMBOL(_cpu_pda); 857 858 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; 859 860 char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; 861 862 void __cpuinit pda_init(int cpu) 863 { 864 struct x8664_pda *pda = cpu_pda(cpu); 865 866 /* Setup up data that may be needed in __get_free_pages early */ 867 loadsegment(fs, 0); 868 loadsegment(gs, 0); 869 /* Memory clobbers used to order PDA accessed */ 870 mb(); 871 wrmsrl(MSR_GS_BASE, pda); 872 mb(); 873 874 pda->cpunumber = cpu; 875 pda->irqcount = -1; 876 pda->kernelstack = (unsigned long)stack_thread_info() - 877 PDA_STACKOFFSET + THREAD_SIZE; 878 pda->active_mm = &init_mm; 879 pda->mmu_state = 0; 880 881 if (cpu == 0) { 882 /* others are initialized in smpboot.c */ 883 pda->pcurrent = &init_task; 884 pda->irqstackptr = boot_cpu_stack; 885 pda->irqstackptr += IRQSTACKSIZE - 64; 886 } else { 887 if (!pda->irqstackptr) { 888 pda->irqstackptr = (char *) 889 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); 890 if (!pda->irqstackptr) 891 panic("cannot allocate irqstack for cpu %d", 892 cpu); 893 pda->irqstackptr += IRQSTACKSIZE - 64; 894 } 895 896 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) 897 pda->nodenumber = cpu_to_node(cpu); 898 } 899 } 900 901 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + 902 DEBUG_STKSZ] __page_aligned_bss; 903 904 extern asmlinkage void ignore_sysret(void); 905 906 /* May not be marked __init: used by software suspend */ 907 void syscall_init(void) 908 { 909 /* 910 * LSTAR and STAR live in a bit strange symbiosis. 911 * They both write to the same internal register. STAR allows to 912 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 913 */ 914 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); 915 wrmsrl(MSR_LSTAR, system_call); 916 wrmsrl(MSR_CSTAR, ignore_sysret); 917 918 #ifdef CONFIG_IA32_EMULATION 919 syscall32_cpu_init(); 920 #endif 921 922 /* Flags to clear on syscall */ 923 wrmsrl(MSR_SYSCALL_MASK, 924 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); 925 } 926 927 unsigned long kernel_eflags; 928 929 /* 930 * Copies of the original ist values from the tss are only accessed during 931 * debugging, no special alignment required. 932 */ 933 DEFINE_PER_CPU(struct orig_ist, orig_ist); 934 935 #else 936 937 /* Make sure %fs is initialized properly in idle threads */ 938 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) 939 { 940 memset(regs, 0, sizeof(struct pt_regs)); 941 regs->fs = __KERNEL_PERCPU; 942 return regs; 943 } 944 #endif 945 946 /* 947 * cpu_init() initializes state that is per-CPU. Some data is already 948 * initialized (naturally) in the bootstrap process, such as the GDT 949 * and IDT. We reload them nevertheless, this function acts as a 950 * 'CPU state barrier', nothing should get across. 951 * A lot of state is already set up in PDA init for 64 bit 952 */ 953 #ifdef CONFIG_X86_64 954 void __cpuinit cpu_init(void) 955 { 956 int cpu = stack_smp_processor_id(); 957 struct tss_struct *t = &per_cpu(init_tss, cpu); 958 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); 959 unsigned long v; 960 char *estacks = NULL; 961 struct task_struct *me; 962 int i; 963 964 /* CPU 0 is initialised in head64.c */ 965 if (cpu != 0) 966 pda_init(cpu); 967 else 968 estacks = boot_exception_stacks; 969 970 me = current; 971 972 if (cpu_test_and_set(cpu, cpu_initialized)) 973 panic("CPU#%d already initialized!\n", cpu); 974 975 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 976 977 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 978 979 /* 980 * Initialize the per-CPU GDT with the boot GDT, 981 * and set up the GDT descriptor: 982 */ 983 984 switch_to_new_gdt(); 985 load_idt((const struct desc_ptr *)&idt_descr); 986 987 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 988 syscall_init(); 989 990 wrmsrl(MSR_FS_BASE, 0); 991 wrmsrl(MSR_KERNEL_GS_BASE, 0); 992 barrier(); 993 994 check_efer(); 995 if (cpu != 0 && x2apic) 996 enable_x2apic(); 997 998 /* 999 * set up and load the per-CPU TSS 1000 */ 1001 if (!orig_ist->ist[0]) { 1002 static const unsigned int order[N_EXCEPTION_STACKS] = { 1003 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, 1004 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER 1005 }; 1006 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1007 if (cpu) { 1008 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); 1009 if (!estacks) 1010 panic("Cannot allocate exception " 1011 "stack %ld %d\n", v, cpu); 1012 } 1013 estacks += PAGE_SIZE << order[v]; 1014 orig_ist->ist[v] = t->x86_tss.ist[v] = 1015 (unsigned long)estacks; 1016 } 1017 } 1018 1019 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1020 /* 1021 * <= is required because the CPU will access up to 1022 * 8 bits beyond the end of the IO permission bitmap. 1023 */ 1024 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1025 t->io_bitmap[i] = ~0UL; 1026 1027 atomic_inc(&init_mm.mm_count); 1028 me->active_mm = &init_mm; 1029 if (me->mm) 1030 BUG(); 1031 enter_lazy_tlb(&init_mm, me); 1032 1033 load_sp0(t, ¤t->thread); 1034 set_tss_desc(cpu, t); 1035 load_TR_desc(); 1036 load_LDT(&init_mm.context); 1037 1038 #ifdef CONFIG_KGDB 1039 /* 1040 * If the kgdb is connected no debug regs should be altered. This 1041 * is only applicable when KGDB and a KGDB I/O module are built 1042 * into the kernel and you are using early debugging with 1043 * kgdbwait. KGDB will control the kernel HW breakpoint registers. 1044 */ 1045 if (kgdb_connected && arch_kgdb_ops.correct_hw_break) 1046 arch_kgdb_ops.correct_hw_break(); 1047 else { 1048 #endif 1049 /* 1050 * Clear all 6 debug registers: 1051 */ 1052 1053 set_debugreg(0UL, 0); 1054 set_debugreg(0UL, 1); 1055 set_debugreg(0UL, 2); 1056 set_debugreg(0UL, 3); 1057 set_debugreg(0UL, 6); 1058 set_debugreg(0UL, 7); 1059 #ifdef CONFIG_KGDB 1060 /* If the kgdb is connected no debug regs should be altered. */ 1061 } 1062 #endif 1063 1064 fpu_init(); 1065 1066 raw_local_save_flags(kernel_eflags); 1067 1068 if (is_uv_system()) 1069 uv_cpu_init(); 1070 } 1071 1072 #else 1073 1074 void __cpuinit cpu_init(void) 1075 { 1076 int cpu = smp_processor_id(); 1077 struct task_struct *curr = current; 1078 struct tss_struct *t = &per_cpu(init_tss, cpu); 1079 struct thread_struct *thread = &curr->thread; 1080 1081 if (cpu_test_and_set(cpu, cpu_initialized)) { 1082 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1083 for (;;) local_irq_enable(); 1084 } 1085 1086 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1087 1088 if (cpu_has_vme || cpu_has_tsc || cpu_has_de) 1089 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1090 1091 load_idt(&idt_descr); 1092 switch_to_new_gdt(); 1093 1094 /* 1095 * Set up and load the per-CPU TSS and LDT 1096 */ 1097 atomic_inc(&init_mm.mm_count); 1098 curr->active_mm = &init_mm; 1099 if (curr->mm) 1100 BUG(); 1101 enter_lazy_tlb(&init_mm, curr); 1102 1103 load_sp0(t, thread); 1104 set_tss_desc(cpu, t); 1105 load_TR_desc(); 1106 load_LDT(&init_mm.context); 1107 1108 #ifdef CONFIG_DOUBLEFAULT 1109 /* Set up doublefault TSS pointer in the GDT */ 1110 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1111 #endif 1112 1113 /* Clear %gs. */ 1114 asm volatile ("mov %0, %%gs" : : "r" (0)); 1115 1116 /* Clear all 6 debug registers: */ 1117 set_debugreg(0, 0); 1118 set_debugreg(0, 1); 1119 set_debugreg(0, 2); 1120 set_debugreg(0, 3); 1121 set_debugreg(0, 6); 1122 set_debugreg(0, 7); 1123 1124 /* 1125 * Force FPU initialization: 1126 */ 1127 if (cpu_has_xsave) 1128 current_thread_info()->status = TS_XSAVE; 1129 else 1130 current_thread_info()->status = 0; 1131 clear_used_math(); 1132 mxcsr_feature_mask_init(); 1133 1134 /* 1135 * Boot processor to setup the FP and extended state context info. 1136 */ 1137 if (!smp_processor_id()) 1138 init_thread_xstate(); 1139 1140 xsave_init(); 1141 } 1142 1143 1144 #endif 1145