1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 #include <linux/syscore_ops.h> 24 #include <linux/pgtable.h> 25 #include <linux/stackprotector.h> 26 27 #include <asm/cmdline.h> 28 #include <asm/perf_event.h> 29 #include <asm/mmu_context.h> 30 #include <asm/doublefault.h> 31 #include <asm/archrandom.h> 32 #include <asm/hypervisor.h> 33 #include <asm/processor.h> 34 #include <asm/tlbflush.h> 35 #include <asm/debugreg.h> 36 #include <asm/sections.h> 37 #include <asm/vsyscall.h> 38 #include <linux/topology.h> 39 #include <linux/cpumask.h> 40 #include <linux/atomic.h> 41 #include <asm/proto.h> 42 #include <asm/setup.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/fpu/api.h> 46 #include <asm/mtrr.h> 47 #include <asm/hwcap2.h> 48 #include <linux/numa.h> 49 #include <asm/numa.h> 50 #include <asm/asm.h> 51 #include <asm/bugs.h> 52 #include <asm/cpu.h> 53 #include <asm/mce.h> 54 #include <asm/msr.h> 55 #include <asm/cacheinfo.h> 56 #include <asm/memtype.h> 57 #include <asm/microcode.h> 58 #include <asm/microcode_intel.h> 59 #include <asm/intel-family.h> 60 #include <asm/cpu_device_id.h> 61 #include <asm/uv/uv.h> 62 #include <asm/sigframe.h> 63 #include <asm/traps.h> 64 #include <asm/sev.h> 65 66 #include "cpu.h" 67 68 u32 elf_hwcap2 __read_mostly; 69 70 /* all of these masks are initialized in setup_cpu_local_masks() */ 71 cpumask_var_t cpu_initialized_mask; 72 cpumask_var_t cpu_callout_mask; 73 cpumask_var_t cpu_callin_mask; 74 75 /* representing cpus for which sibling maps can be computed */ 76 cpumask_var_t cpu_sibling_setup_mask; 77 78 /* Number of siblings per CPU package */ 79 int smp_num_siblings = 1; 80 EXPORT_SYMBOL(smp_num_siblings); 81 82 /* Last level cache ID of each logical CPU */ 83 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 84 85 u16 get_llc_id(unsigned int cpu) 86 { 87 return per_cpu(cpu_llc_id, cpu); 88 } 89 EXPORT_SYMBOL_GPL(get_llc_id); 90 91 /* L2 cache ID of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; 93 94 static struct ppin_info { 95 int feature; 96 int msr_ppin_ctl; 97 int msr_ppin; 98 } ppin_info[] = { 99 [X86_VENDOR_INTEL] = { 100 .feature = X86_FEATURE_INTEL_PPIN, 101 .msr_ppin_ctl = MSR_PPIN_CTL, 102 .msr_ppin = MSR_PPIN 103 }, 104 [X86_VENDOR_AMD] = { 105 .feature = X86_FEATURE_AMD_PPIN, 106 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 107 .msr_ppin = MSR_AMD_PPIN 108 }, 109 }; 110 111 static const struct x86_cpu_id ppin_cpuids[] = { 112 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 113 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 114 115 /* Legacy models without CPUID enumeration */ 116 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 117 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 125 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 126 127 {} 128 }; 129 130 static void ppin_init(struct cpuinfo_x86 *c) 131 { 132 const struct x86_cpu_id *id; 133 unsigned long long val; 134 struct ppin_info *info; 135 136 id = x86_match_cpu(ppin_cpuids); 137 if (!id) 138 return; 139 140 /* 141 * Testing the presence of the MSR is not enough. Need to check 142 * that the PPIN_CTL allows reading of the PPIN. 143 */ 144 info = (struct ppin_info *)id->driver_data; 145 146 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 147 goto clear_ppin; 148 149 if ((val & 3UL) == 1UL) { 150 /* PPIN locked in disabled mode */ 151 goto clear_ppin; 152 } 153 154 /* If PPIN is disabled, try to enable */ 155 if (!(val & 2UL)) { 156 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 157 rdmsrl_safe(info->msr_ppin_ctl, &val); 158 } 159 160 /* Is the enable bit set? */ 161 if (val & 2UL) { 162 c->ppin = __rdmsr(info->msr_ppin); 163 set_cpu_cap(c, info->feature); 164 return; 165 } 166 167 clear_ppin: 168 clear_cpu_cap(c, info->feature); 169 } 170 171 /* correctly size the local cpu masks */ 172 void __init setup_cpu_local_masks(void) 173 { 174 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 175 alloc_bootmem_cpumask_var(&cpu_callin_mask); 176 alloc_bootmem_cpumask_var(&cpu_callout_mask); 177 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 178 } 179 180 static void default_init(struct cpuinfo_x86 *c) 181 { 182 #ifdef CONFIG_X86_64 183 cpu_detect_cache_sizes(c); 184 #else 185 /* Not much we can do here... */ 186 /* Check if at least it has cpuid */ 187 if (c->cpuid_level == -1) { 188 /* No cpuid. It must be an ancient CPU */ 189 if (c->x86 == 4) 190 strcpy(c->x86_model_id, "486"); 191 else if (c->x86 == 3) 192 strcpy(c->x86_model_id, "386"); 193 } 194 #endif 195 } 196 197 static const struct cpu_dev default_cpu = { 198 .c_init = default_init, 199 .c_vendor = "Unknown", 200 .c_x86_vendor = X86_VENDOR_UNKNOWN, 201 }; 202 203 static const struct cpu_dev *this_cpu = &default_cpu; 204 205 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 206 #ifdef CONFIG_X86_64 207 /* 208 * We need valid kernel segments for data and code in long mode too 209 * IRET will check the segment types kkeil 2000/10/28 210 * Also sysret mandates a special GDT layout 211 * 212 * TLS descriptors are currently at a different place compared to i386. 213 * Hopefully nobody expects them at a fixed place (Wine?) 214 */ 215 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 216 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 217 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 218 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 219 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 220 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 221 #else 222 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 223 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 224 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 225 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 226 /* 227 * Segments used for calling PnP BIOS have byte granularity. 228 * They code segments and data segments have fixed 64k limits, 229 * the transfer segment sizes are set at run time. 230 */ 231 /* 32-bit code */ 232 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 233 /* 16-bit code */ 234 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 235 /* 16-bit data */ 236 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 237 /* 16-bit data */ 238 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 239 /* 16-bit data */ 240 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 241 /* 242 * The APM segments have byte granularity and their bases 243 * are set at run time. All have 64k limits. 244 */ 245 /* 32-bit code */ 246 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 247 /* 16-bit code */ 248 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 249 /* data */ 250 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 251 252 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 253 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 254 #endif 255 } }; 256 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 257 258 #ifdef CONFIG_X86_64 259 static int __init x86_nopcid_setup(char *s) 260 { 261 /* nopcid doesn't accept parameters */ 262 if (s) 263 return -EINVAL; 264 265 /* do not emit a message if the feature is not present */ 266 if (!boot_cpu_has(X86_FEATURE_PCID)) 267 return 0; 268 269 setup_clear_cpu_cap(X86_FEATURE_PCID); 270 pr_info("nopcid: PCID feature disabled\n"); 271 return 0; 272 } 273 early_param("nopcid", x86_nopcid_setup); 274 #endif 275 276 static int __init x86_noinvpcid_setup(char *s) 277 { 278 /* noinvpcid doesn't accept parameters */ 279 if (s) 280 return -EINVAL; 281 282 /* do not emit a message if the feature is not present */ 283 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 284 return 0; 285 286 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 287 pr_info("noinvpcid: INVPCID feature disabled\n"); 288 return 0; 289 } 290 early_param("noinvpcid", x86_noinvpcid_setup); 291 292 #ifdef CONFIG_X86_32 293 static int cachesize_override = -1; 294 static int disable_x86_serial_nr = 1; 295 296 static int __init cachesize_setup(char *str) 297 { 298 get_option(&str, &cachesize_override); 299 return 1; 300 } 301 __setup("cachesize=", cachesize_setup); 302 303 /* Standard macro to see if a specific flag is changeable */ 304 static inline int flag_is_changeable_p(u32 flag) 305 { 306 u32 f1, f2; 307 308 /* 309 * Cyrix and IDT cpus allow disabling of CPUID 310 * so the code below may return different results 311 * when it is executed before and after enabling 312 * the CPUID. Add "volatile" to not allow gcc to 313 * optimize the subsequent calls to this function. 314 */ 315 asm volatile ("pushfl \n\t" 316 "pushfl \n\t" 317 "popl %0 \n\t" 318 "movl %0, %1 \n\t" 319 "xorl %2, %0 \n\t" 320 "pushl %0 \n\t" 321 "popfl \n\t" 322 "pushfl \n\t" 323 "popl %0 \n\t" 324 "popfl \n\t" 325 326 : "=&r" (f1), "=&r" (f2) 327 : "ir" (flag)); 328 329 return ((f1^f2) & flag) != 0; 330 } 331 332 /* Probe for the CPUID instruction */ 333 int have_cpuid_p(void) 334 { 335 return flag_is_changeable_p(X86_EFLAGS_ID); 336 } 337 338 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 339 { 340 unsigned long lo, hi; 341 342 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 343 return; 344 345 /* Disable processor serial number: */ 346 347 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 348 lo |= 0x200000; 349 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 350 351 pr_notice("CPU serial number disabled.\n"); 352 clear_cpu_cap(c, X86_FEATURE_PN); 353 354 /* Disabling the serial number may affect the cpuid level */ 355 c->cpuid_level = cpuid_eax(0); 356 } 357 358 static int __init x86_serial_nr_setup(char *s) 359 { 360 disable_x86_serial_nr = 0; 361 return 1; 362 } 363 __setup("serialnumber", x86_serial_nr_setup); 364 #else 365 static inline int flag_is_changeable_p(u32 flag) 366 { 367 return 1; 368 } 369 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 370 { 371 } 372 #endif 373 374 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 375 { 376 if (cpu_has(c, X86_FEATURE_SMEP)) 377 cr4_set_bits(X86_CR4_SMEP); 378 } 379 380 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 381 { 382 unsigned long eflags = native_save_fl(); 383 384 /* This should have been cleared long ago */ 385 BUG_ON(eflags & X86_EFLAGS_AC); 386 387 if (cpu_has(c, X86_FEATURE_SMAP)) 388 cr4_set_bits(X86_CR4_SMAP); 389 } 390 391 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 392 { 393 /* Check the boot processor, plus build option for UMIP. */ 394 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 395 goto out; 396 397 /* Check the current processor's cpuid bits. */ 398 if (!cpu_has(c, X86_FEATURE_UMIP)) 399 goto out; 400 401 cr4_set_bits(X86_CR4_UMIP); 402 403 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 404 405 return; 406 407 out: 408 /* 409 * Make sure UMIP is disabled in case it was enabled in a 410 * previous boot (e.g., via kexec). 411 */ 412 cr4_clear_bits(X86_CR4_UMIP); 413 } 414 415 /* These bits should not change their value after CPU init is finished. */ 416 static const unsigned long cr4_pinned_mask = 417 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 418 X86_CR4_FSGSBASE | X86_CR4_CET; 419 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 420 static unsigned long cr4_pinned_bits __ro_after_init; 421 422 void native_write_cr0(unsigned long val) 423 { 424 unsigned long bits_missing = 0; 425 426 set_register: 427 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 428 429 if (static_branch_likely(&cr_pinning)) { 430 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 431 bits_missing = X86_CR0_WP; 432 val |= bits_missing; 433 goto set_register; 434 } 435 /* Warn after we've set the missing bits. */ 436 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 437 } 438 } 439 EXPORT_SYMBOL(native_write_cr0); 440 441 void __no_profile native_write_cr4(unsigned long val) 442 { 443 unsigned long bits_changed = 0; 444 445 set_register: 446 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 447 448 if (static_branch_likely(&cr_pinning)) { 449 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 450 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 451 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 452 goto set_register; 453 } 454 /* Warn after we've corrected the changed bits. */ 455 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 456 bits_changed); 457 } 458 } 459 #if IS_MODULE(CONFIG_LKDTM) 460 EXPORT_SYMBOL_GPL(native_write_cr4); 461 #endif 462 463 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 464 { 465 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 466 467 lockdep_assert_irqs_disabled(); 468 469 newval = (cr4 & ~clear) | set; 470 if (newval != cr4) { 471 this_cpu_write(cpu_tlbstate.cr4, newval); 472 __write_cr4(newval); 473 } 474 } 475 EXPORT_SYMBOL(cr4_update_irqsoff); 476 477 /* Read the CR4 shadow. */ 478 unsigned long cr4_read_shadow(void) 479 { 480 return this_cpu_read(cpu_tlbstate.cr4); 481 } 482 EXPORT_SYMBOL_GPL(cr4_read_shadow); 483 484 void cr4_init(void) 485 { 486 unsigned long cr4 = __read_cr4(); 487 488 if (boot_cpu_has(X86_FEATURE_PCID)) 489 cr4 |= X86_CR4_PCIDE; 490 if (static_branch_likely(&cr_pinning)) 491 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 492 493 __write_cr4(cr4); 494 495 /* Initialize cr4 shadow for this CPU. */ 496 this_cpu_write(cpu_tlbstate.cr4, cr4); 497 } 498 499 /* 500 * Once CPU feature detection is finished (and boot params have been 501 * parsed), record any of the sensitive CR bits that are set, and 502 * enable CR pinning. 503 */ 504 static void __init setup_cr_pinning(void) 505 { 506 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 507 static_key_enable(&cr_pinning.key); 508 } 509 510 static __init int x86_nofsgsbase_setup(char *arg) 511 { 512 /* Require an exact match without trailing characters. */ 513 if (strlen(arg)) 514 return 0; 515 516 /* Do not emit a message if the feature is not present. */ 517 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 518 return 1; 519 520 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 521 pr_info("FSGSBASE disabled via kernel command line\n"); 522 return 1; 523 } 524 __setup("nofsgsbase", x86_nofsgsbase_setup); 525 526 /* 527 * Protection Keys are not available in 32-bit mode. 528 */ 529 static bool pku_disabled; 530 531 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 532 { 533 if (c == &boot_cpu_data) { 534 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 535 return; 536 /* 537 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 538 * bit to be set. Enforce it. 539 */ 540 setup_force_cpu_cap(X86_FEATURE_OSPKE); 541 542 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 543 return; 544 } 545 546 cr4_set_bits(X86_CR4_PKE); 547 /* Load the default PKRU value */ 548 pkru_write_default(); 549 } 550 551 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 552 static __init int setup_disable_pku(char *arg) 553 { 554 /* 555 * Do not clear the X86_FEATURE_PKU bit. All of the 556 * runtime checks are against OSPKE so clearing the 557 * bit does nothing. 558 * 559 * This way, we will see "pku" in cpuinfo, but not 560 * "ospke", which is exactly what we want. It shows 561 * that the CPU has PKU, but the OS has not enabled it. 562 * This happens to be exactly how a system would look 563 * if we disabled the config option. 564 */ 565 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 566 pku_disabled = true; 567 return 1; 568 } 569 __setup("nopku", setup_disable_pku); 570 #endif /* CONFIG_X86_64 */ 571 572 #ifdef CONFIG_X86_KERNEL_IBT 573 574 __noendbr u64 ibt_save(void) 575 { 576 u64 msr = 0; 577 578 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 579 rdmsrl(MSR_IA32_S_CET, msr); 580 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 581 } 582 583 return msr; 584 } 585 586 __noendbr void ibt_restore(u64 save) 587 { 588 u64 msr; 589 590 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 591 rdmsrl(MSR_IA32_S_CET, msr); 592 msr &= ~CET_ENDBR_EN; 593 msr |= (save & CET_ENDBR_EN); 594 wrmsrl(MSR_IA32_S_CET, msr); 595 } 596 } 597 598 #endif 599 600 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 601 { 602 u64 msr = CET_ENDBR_EN; 603 604 if (!HAS_KERNEL_IBT || 605 !cpu_feature_enabled(X86_FEATURE_IBT)) 606 return; 607 608 wrmsrl(MSR_IA32_S_CET, msr); 609 cr4_set_bits(X86_CR4_CET); 610 611 if (!ibt_selftest()) { 612 pr_err("IBT selftest: Failed!\n"); 613 setup_clear_cpu_cap(X86_FEATURE_IBT); 614 return; 615 } 616 } 617 618 __noendbr void cet_disable(void) 619 { 620 if (cpu_feature_enabled(X86_FEATURE_IBT)) 621 wrmsrl(MSR_IA32_S_CET, 0); 622 } 623 624 /* 625 * Some CPU features depend on higher CPUID levels, which may not always 626 * be available due to CPUID level capping or broken virtualization 627 * software. Add those features to this table to auto-disable them. 628 */ 629 struct cpuid_dependent_feature { 630 u32 feature; 631 u32 level; 632 }; 633 634 static const struct cpuid_dependent_feature 635 cpuid_dependent_features[] = { 636 { X86_FEATURE_MWAIT, 0x00000005 }, 637 { X86_FEATURE_DCA, 0x00000009 }, 638 { X86_FEATURE_XSAVE, 0x0000000d }, 639 { 0, 0 } 640 }; 641 642 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 643 { 644 const struct cpuid_dependent_feature *df; 645 646 for (df = cpuid_dependent_features; df->feature; df++) { 647 648 if (!cpu_has(c, df->feature)) 649 continue; 650 /* 651 * Note: cpuid_level is set to -1 if unavailable, but 652 * extended_extended_level is set to 0 if unavailable 653 * and the legitimate extended levels are all negative 654 * when signed; hence the weird messing around with 655 * signs here... 656 */ 657 if (!((s32)df->level < 0 ? 658 (u32)df->level > (u32)c->extended_cpuid_level : 659 (s32)df->level > (s32)c->cpuid_level)) 660 continue; 661 662 clear_cpu_cap(c, df->feature); 663 if (!warn) 664 continue; 665 666 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 667 x86_cap_flag(df->feature), df->level); 668 } 669 } 670 671 /* 672 * Naming convention should be: <Name> [(<Codename>)] 673 * This table only is used unless init_<vendor>() below doesn't set it; 674 * in particular, if CPUID levels 0x80000002..4 are supported, this 675 * isn't used 676 */ 677 678 /* Look up CPU names by table lookup. */ 679 static const char *table_lookup_model(struct cpuinfo_x86 *c) 680 { 681 #ifdef CONFIG_X86_32 682 const struct legacy_cpu_model_info *info; 683 684 if (c->x86_model >= 16) 685 return NULL; /* Range check */ 686 687 if (!this_cpu) 688 return NULL; 689 690 info = this_cpu->legacy_models; 691 692 while (info->family) { 693 if (info->family == c->x86) 694 return info->model_names[c->x86_model]; 695 info++; 696 } 697 #endif 698 return NULL; /* Not found */ 699 } 700 701 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 702 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 703 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 704 705 void load_percpu_segment(int cpu) 706 { 707 #ifdef CONFIG_X86_32 708 loadsegment(fs, __KERNEL_PERCPU); 709 #else 710 __loadsegment_simple(gs, 0); 711 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 712 #endif 713 } 714 715 #ifdef CONFIG_X86_32 716 /* The 32-bit entry code needs to find cpu_entry_area. */ 717 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 718 #endif 719 720 /* Load the original GDT from the per-cpu structure */ 721 void load_direct_gdt(int cpu) 722 { 723 struct desc_ptr gdt_descr; 724 725 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 726 gdt_descr.size = GDT_SIZE - 1; 727 load_gdt(&gdt_descr); 728 } 729 EXPORT_SYMBOL_GPL(load_direct_gdt); 730 731 /* Load a fixmap remapping of the per-cpu GDT */ 732 void load_fixmap_gdt(int cpu) 733 { 734 struct desc_ptr gdt_descr; 735 736 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 737 gdt_descr.size = GDT_SIZE - 1; 738 load_gdt(&gdt_descr); 739 } 740 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 741 742 /* 743 * Current gdt points %fs at the "master" per-cpu area: after this, 744 * it's on the real one. 745 */ 746 void switch_to_new_gdt(int cpu) 747 { 748 /* Load the original GDT */ 749 load_direct_gdt(cpu); 750 /* Reload the per-cpu base */ 751 load_percpu_segment(cpu); 752 } 753 754 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 755 756 static void get_model_name(struct cpuinfo_x86 *c) 757 { 758 unsigned int *v; 759 char *p, *q, *s; 760 761 if (c->extended_cpuid_level < 0x80000004) 762 return; 763 764 v = (unsigned int *)c->x86_model_id; 765 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 766 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 767 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 768 c->x86_model_id[48] = 0; 769 770 /* Trim whitespace */ 771 p = q = s = &c->x86_model_id[0]; 772 773 while (*p == ' ') 774 p++; 775 776 while (*p) { 777 /* Note the last non-whitespace index */ 778 if (!isspace(*p)) 779 s = q; 780 781 *q++ = *p++; 782 } 783 784 *(s + 1) = '\0'; 785 } 786 787 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 788 { 789 unsigned int eax, ebx, ecx, edx; 790 791 c->x86_max_cores = 1; 792 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 793 return; 794 795 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 796 if (eax & 0x1f) 797 c->x86_max_cores = (eax >> 26) + 1; 798 } 799 800 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 801 { 802 unsigned int n, dummy, ebx, ecx, edx, l2size; 803 804 n = c->extended_cpuid_level; 805 806 if (n >= 0x80000005) { 807 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 808 c->x86_cache_size = (ecx>>24) + (edx>>24); 809 #ifdef CONFIG_X86_64 810 /* On K8 L1 TLB is inclusive, so don't count it */ 811 c->x86_tlbsize = 0; 812 #endif 813 } 814 815 if (n < 0x80000006) /* Some chips just has a large L1. */ 816 return; 817 818 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 819 l2size = ecx >> 16; 820 821 #ifdef CONFIG_X86_64 822 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 823 #else 824 /* do processor-specific cache resizing */ 825 if (this_cpu->legacy_cache_size) 826 l2size = this_cpu->legacy_cache_size(c, l2size); 827 828 /* Allow user to override all this if necessary. */ 829 if (cachesize_override != -1) 830 l2size = cachesize_override; 831 832 if (l2size == 0) 833 return; /* Again, no L2 cache is possible */ 834 #endif 835 836 c->x86_cache_size = l2size; 837 } 838 839 u16 __read_mostly tlb_lli_4k[NR_INFO]; 840 u16 __read_mostly tlb_lli_2m[NR_INFO]; 841 u16 __read_mostly tlb_lli_4m[NR_INFO]; 842 u16 __read_mostly tlb_lld_4k[NR_INFO]; 843 u16 __read_mostly tlb_lld_2m[NR_INFO]; 844 u16 __read_mostly tlb_lld_4m[NR_INFO]; 845 u16 __read_mostly tlb_lld_1g[NR_INFO]; 846 847 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 848 { 849 if (this_cpu->c_detect_tlb) 850 this_cpu->c_detect_tlb(c); 851 852 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 853 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 854 tlb_lli_4m[ENTRIES]); 855 856 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 857 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 858 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 859 } 860 861 int detect_ht_early(struct cpuinfo_x86 *c) 862 { 863 #ifdef CONFIG_SMP 864 u32 eax, ebx, ecx, edx; 865 866 if (!cpu_has(c, X86_FEATURE_HT)) 867 return -1; 868 869 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 870 return -1; 871 872 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 873 return -1; 874 875 cpuid(1, &eax, &ebx, &ecx, &edx); 876 877 smp_num_siblings = (ebx & 0xff0000) >> 16; 878 if (smp_num_siblings == 1) 879 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 880 #endif 881 return 0; 882 } 883 884 void detect_ht(struct cpuinfo_x86 *c) 885 { 886 #ifdef CONFIG_SMP 887 int index_msb, core_bits; 888 889 if (detect_ht_early(c) < 0) 890 return; 891 892 index_msb = get_count_order(smp_num_siblings); 893 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 894 895 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 896 897 index_msb = get_count_order(smp_num_siblings); 898 899 core_bits = get_count_order(c->x86_max_cores); 900 901 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 902 ((1 << core_bits) - 1); 903 #endif 904 } 905 906 static void get_cpu_vendor(struct cpuinfo_x86 *c) 907 { 908 char *v = c->x86_vendor_id; 909 int i; 910 911 for (i = 0; i < X86_VENDOR_NUM; i++) { 912 if (!cpu_devs[i]) 913 break; 914 915 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 916 (cpu_devs[i]->c_ident[1] && 917 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 918 919 this_cpu = cpu_devs[i]; 920 c->x86_vendor = this_cpu->c_x86_vendor; 921 return; 922 } 923 } 924 925 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 926 "CPU: Your system may be unstable.\n", v); 927 928 c->x86_vendor = X86_VENDOR_UNKNOWN; 929 this_cpu = &default_cpu; 930 } 931 932 void cpu_detect(struct cpuinfo_x86 *c) 933 { 934 /* Get vendor name */ 935 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 936 (unsigned int *)&c->x86_vendor_id[0], 937 (unsigned int *)&c->x86_vendor_id[8], 938 (unsigned int *)&c->x86_vendor_id[4]); 939 940 c->x86 = 4; 941 /* Intel-defined flags: level 0x00000001 */ 942 if (c->cpuid_level >= 0x00000001) { 943 u32 junk, tfms, cap0, misc; 944 945 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 946 c->x86 = x86_family(tfms); 947 c->x86_model = x86_model(tfms); 948 c->x86_stepping = x86_stepping(tfms); 949 950 if (cap0 & (1<<19)) { 951 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 952 c->x86_cache_alignment = c->x86_clflush_size; 953 } 954 } 955 } 956 957 static void apply_forced_caps(struct cpuinfo_x86 *c) 958 { 959 int i; 960 961 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 962 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 963 c->x86_capability[i] |= cpu_caps_set[i]; 964 } 965 } 966 967 static void init_speculation_control(struct cpuinfo_x86 *c) 968 { 969 /* 970 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 971 * and they also have a different bit for STIBP support. Also, 972 * a hypervisor might have set the individual AMD bits even on 973 * Intel CPUs, for finer-grained selection of what's available. 974 */ 975 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 976 set_cpu_cap(c, X86_FEATURE_IBRS); 977 set_cpu_cap(c, X86_FEATURE_IBPB); 978 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 979 } 980 981 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 982 set_cpu_cap(c, X86_FEATURE_STIBP); 983 984 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 985 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 986 set_cpu_cap(c, X86_FEATURE_SSBD); 987 988 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 989 set_cpu_cap(c, X86_FEATURE_IBRS); 990 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 991 } 992 993 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 994 set_cpu_cap(c, X86_FEATURE_IBPB); 995 996 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 997 set_cpu_cap(c, X86_FEATURE_STIBP); 998 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 999 } 1000 1001 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 1002 set_cpu_cap(c, X86_FEATURE_SSBD); 1003 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 1004 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 1005 } 1006 } 1007 1008 void get_cpu_cap(struct cpuinfo_x86 *c) 1009 { 1010 u32 eax, ebx, ecx, edx; 1011 1012 /* Intel-defined flags: level 0x00000001 */ 1013 if (c->cpuid_level >= 0x00000001) { 1014 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 1015 1016 c->x86_capability[CPUID_1_ECX] = ecx; 1017 c->x86_capability[CPUID_1_EDX] = edx; 1018 } 1019 1020 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 1021 if (c->cpuid_level >= 0x00000006) 1022 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 1023 1024 /* Additional Intel-defined flags: level 0x00000007 */ 1025 if (c->cpuid_level >= 0x00000007) { 1026 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 1027 c->x86_capability[CPUID_7_0_EBX] = ebx; 1028 c->x86_capability[CPUID_7_ECX] = ecx; 1029 c->x86_capability[CPUID_7_EDX] = edx; 1030 1031 /* Check valid sub-leaf index before accessing it */ 1032 if (eax >= 1) { 1033 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 1034 c->x86_capability[CPUID_7_1_EAX] = eax; 1035 } 1036 } 1037 1038 /* Extended state features: level 0x0000000d */ 1039 if (c->cpuid_level >= 0x0000000d) { 1040 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1041 1042 c->x86_capability[CPUID_D_1_EAX] = eax; 1043 } 1044 1045 /* AMD-defined flags: level 0x80000001 */ 1046 eax = cpuid_eax(0x80000000); 1047 c->extended_cpuid_level = eax; 1048 1049 if ((eax & 0xffff0000) == 0x80000000) { 1050 if (eax >= 0x80000001) { 1051 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1052 1053 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1054 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1055 } 1056 } 1057 1058 if (c->extended_cpuid_level >= 0x80000007) { 1059 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1060 1061 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1062 c->x86_power = edx; 1063 } 1064 1065 if (c->extended_cpuid_level >= 0x80000008) { 1066 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1067 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1068 } 1069 1070 if (c->extended_cpuid_level >= 0x8000000a) 1071 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1072 1073 if (c->extended_cpuid_level >= 0x8000001f) 1074 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1075 1076 init_scattered_cpuid_features(c); 1077 init_speculation_control(c); 1078 1079 /* 1080 * Clear/Set all flags overridden by options, after probe. 1081 * This needs to happen each time we re-probe, which may happen 1082 * several times during CPU initialization. 1083 */ 1084 apply_forced_caps(c); 1085 } 1086 1087 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1088 { 1089 u32 eax, ebx, ecx, edx; 1090 1091 if (c->extended_cpuid_level >= 0x80000008) { 1092 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1093 1094 c->x86_virt_bits = (eax >> 8) & 0xff; 1095 c->x86_phys_bits = eax & 0xff; 1096 } 1097 #ifdef CONFIG_X86_32 1098 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 1099 c->x86_phys_bits = 36; 1100 #endif 1101 c->x86_cache_bits = c->x86_phys_bits; 1102 } 1103 1104 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1105 { 1106 #ifdef CONFIG_X86_32 1107 int i; 1108 1109 /* 1110 * First of all, decide if this is a 486 or higher 1111 * It's a 486 if we can modify the AC flag 1112 */ 1113 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1114 c->x86 = 4; 1115 else 1116 c->x86 = 3; 1117 1118 for (i = 0; i < X86_VENDOR_NUM; i++) 1119 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1120 c->x86_vendor_id[0] = 0; 1121 cpu_devs[i]->c_identify(c); 1122 if (c->x86_vendor_id[0]) { 1123 get_cpu_vendor(c); 1124 break; 1125 } 1126 } 1127 #endif 1128 } 1129 1130 #define NO_SPECULATION BIT(0) 1131 #define NO_MELTDOWN BIT(1) 1132 #define NO_SSB BIT(2) 1133 #define NO_L1TF BIT(3) 1134 #define NO_MDS BIT(4) 1135 #define MSBDS_ONLY BIT(5) 1136 #define NO_SWAPGS BIT(6) 1137 #define NO_ITLB_MULTIHIT BIT(7) 1138 #define NO_SPECTRE_V2 BIT(8) 1139 #define NO_MMIO BIT(9) 1140 #define NO_EIBRS_PBRSB BIT(10) 1141 1142 #define VULNWL(vendor, family, model, whitelist) \ 1143 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1144 1145 #define VULNWL_INTEL(model, whitelist) \ 1146 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1147 1148 #define VULNWL_AMD(family, whitelist) \ 1149 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1150 1151 #define VULNWL_HYGON(family, whitelist) \ 1152 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1153 1154 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1155 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1156 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1157 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1158 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1159 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1160 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1161 1162 /* Intel Family 6 */ 1163 VULNWL_INTEL(TIGERLAKE, NO_MMIO), 1164 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), 1165 VULNWL_INTEL(ALDERLAKE, NO_MMIO), 1166 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), 1167 1168 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1169 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1170 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1171 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1172 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1173 1174 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1175 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1176 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1177 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1178 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1179 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1180 1181 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1182 1183 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1184 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1185 1186 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1187 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1188 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1189 1190 /* 1191 * Technically, swapgs isn't serializing on AMD (despite it previously 1192 * being documented as such in the APM). But according to AMD, %gs is 1193 * updated non-speculatively, and the issuing of %gs-relative memory 1194 * operands will be blocked until the %gs update completes, which is 1195 * good enough for our purposes. 1196 */ 1197 1198 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), 1199 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1200 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1201 1202 /* AMD Family 0xf - 0x12 */ 1203 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1204 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1205 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1206 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1207 1208 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1209 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1210 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1211 1212 /* Zhaoxin Family 7 */ 1213 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1214 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), 1215 {} 1216 }; 1217 1218 #define VULNBL(vendor, family, model, blacklist) \ 1219 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1220 1221 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ 1222 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ 1223 INTEL_FAM6_##model, steppings, \ 1224 X86_FEATURE_ANY, issues) 1225 1226 #define VULNBL_AMD(family, blacklist) \ 1227 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1228 1229 #define VULNBL_HYGON(family, blacklist) \ 1230 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1231 1232 #define SRBDS BIT(0) 1233 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1234 #define MMIO BIT(1) 1235 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1236 #define MMIO_SBDS BIT(2) 1237 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1238 #define RETBLEED BIT(3) 1239 1240 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1241 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1242 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), 1243 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), 1244 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), 1245 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), 1246 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), 1247 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1248 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), 1249 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), 1250 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1251 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED), 1252 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1253 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1254 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), 1255 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), 1256 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1257 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO), 1258 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO), 1259 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1260 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), 1261 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1262 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1263 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED), 1264 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1265 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO), 1266 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), 1267 1268 VULNBL_AMD(0x15, RETBLEED), 1269 VULNBL_AMD(0x16, RETBLEED), 1270 VULNBL_AMD(0x17, RETBLEED), 1271 VULNBL_HYGON(0x18, RETBLEED), 1272 {} 1273 }; 1274 1275 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1276 { 1277 const struct x86_cpu_id *m = x86_match_cpu(table); 1278 1279 return m && !!(m->driver_data & which); 1280 } 1281 1282 u64 x86_read_arch_cap_msr(void) 1283 { 1284 u64 ia32_cap = 0; 1285 1286 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1287 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1288 1289 return ia32_cap; 1290 } 1291 1292 static bool arch_cap_mmio_immune(u64 ia32_cap) 1293 { 1294 return (ia32_cap & ARCH_CAP_FBSDP_NO && 1295 ia32_cap & ARCH_CAP_PSDP_NO && 1296 ia32_cap & ARCH_CAP_SBDR_SSDP_NO); 1297 } 1298 1299 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1300 { 1301 u64 ia32_cap = x86_read_arch_cap_msr(); 1302 1303 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1304 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1305 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1306 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1307 1308 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1309 return; 1310 1311 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1312 1313 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1314 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1315 1316 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1317 !(ia32_cap & ARCH_CAP_SSB_NO) && 1318 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1319 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1320 1321 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1322 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1323 1324 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1325 !(ia32_cap & ARCH_CAP_MDS_NO)) { 1326 setup_force_cpu_bug(X86_BUG_MDS); 1327 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1328 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1329 } 1330 1331 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1332 setup_force_cpu_bug(X86_BUG_SWAPGS); 1333 1334 /* 1335 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1336 * - TSX is supported or 1337 * - TSX_CTRL is present 1338 * 1339 * TSX_CTRL check is needed for cases when TSX could be disabled before 1340 * the kernel boot e.g. kexec. 1341 * TSX_CTRL check alone is not sufficient for cases when the microcode 1342 * update is not present or running as guest that don't get TSX_CTRL. 1343 */ 1344 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1345 (cpu_has(c, X86_FEATURE_RTM) || 1346 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1347 setup_force_cpu_bug(X86_BUG_TAA); 1348 1349 /* 1350 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1351 * in the vulnerability blacklist. 1352 * 1353 * Some of the implications and mitigation of Shared Buffers Data 1354 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1355 * SRBDS. 1356 */ 1357 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1358 cpu_has(c, X86_FEATURE_RDSEED)) && 1359 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1360 setup_force_cpu_bug(X86_BUG_SRBDS); 1361 1362 /* 1363 * Processor MMIO Stale Data bug enumeration 1364 * 1365 * Affected CPU list is generally enough to enumerate the vulnerability, 1366 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1367 * not want the guest to enumerate the bug. 1368 * 1369 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1370 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1371 */ 1372 if (!arch_cap_mmio_immune(ia32_cap)) { 1373 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1374 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1375 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1376 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1377 } 1378 1379 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1380 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA)) 1381 setup_force_cpu_bug(X86_BUG_RETBLEED); 1382 } 1383 1384 if (cpu_has(c, X86_FEATURE_IBRS_ENHANCED) && 1385 !cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1386 !(ia32_cap & ARCH_CAP_PBRSB_NO)) 1387 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1388 1389 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1390 return; 1391 1392 /* Rogue Data Cache Load? No! */ 1393 if (ia32_cap & ARCH_CAP_RDCL_NO) 1394 return; 1395 1396 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1397 1398 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1399 return; 1400 1401 setup_force_cpu_bug(X86_BUG_L1TF); 1402 } 1403 1404 /* 1405 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1406 * unfortunately, that's not true in practice because of early VIA 1407 * chips and (more importantly) broken virtualizers that are not easy 1408 * to detect. In the latter case it doesn't even *fail* reliably, so 1409 * probing for it doesn't even work. Disable it completely on 32-bit 1410 * unless we can find a reliable way to detect all the broken cases. 1411 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1412 */ 1413 static void detect_nopl(void) 1414 { 1415 #ifdef CONFIG_X86_32 1416 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1417 #else 1418 setup_force_cpu_cap(X86_FEATURE_NOPL); 1419 #endif 1420 } 1421 1422 /* 1423 * We parse cpu parameters early because fpu__init_system() is executed 1424 * before parse_early_param(). 1425 */ 1426 static void __init cpu_parse_early_param(void) 1427 { 1428 char arg[128]; 1429 char *argptr = arg, *opt; 1430 int arglen, taint = 0; 1431 1432 #ifdef CONFIG_X86_32 1433 if (cmdline_find_option_bool(boot_command_line, "no387")) 1434 #ifdef CONFIG_MATH_EMULATION 1435 setup_clear_cpu_cap(X86_FEATURE_FPU); 1436 #else 1437 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1438 #endif 1439 1440 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1441 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1442 #endif 1443 1444 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1445 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1446 1447 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1448 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1449 1450 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1451 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1452 1453 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1454 if (arglen <= 0) 1455 return; 1456 1457 pr_info("Clearing CPUID bits:"); 1458 1459 while (argptr) { 1460 bool found __maybe_unused = false; 1461 unsigned int bit; 1462 1463 opt = strsep(&argptr, ","); 1464 1465 /* 1466 * Handle naked numbers first for feature flags which don't 1467 * have names. 1468 */ 1469 if (!kstrtouint(opt, 10, &bit)) { 1470 if (bit < NCAPINTS * 32) { 1471 1472 #ifdef CONFIG_X86_FEATURE_NAMES 1473 /* empty-string, i.e., ""-defined feature flags */ 1474 if (!x86_cap_flags[bit]) 1475 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1476 else 1477 #endif 1478 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1479 1480 setup_clear_cpu_cap(bit); 1481 taint++; 1482 } 1483 /* 1484 * The assumption is that there are no feature names with only 1485 * numbers in the name thus go to the next argument. 1486 */ 1487 continue; 1488 } 1489 1490 #ifdef CONFIG_X86_FEATURE_NAMES 1491 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1492 if (!x86_cap_flag(bit)) 1493 continue; 1494 1495 if (strcmp(x86_cap_flag(bit), opt)) 1496 continue; 1497 1498 pr_cont(" %s", opt); 1499 setup_clear_cpu_cap(bit); 1500 taint++; 1501 found = true; 1502 break; 1503 } 1504 1505 if (!found) 1506 pr_cont(" (unknown: %s)", opt); 1507 #endif 1508 } 1509 pr_cont("\n"); 1510 1511 if (taint) 1512 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1513 } 1514 1515 /* 1516 * Do minimum CPU detection early. 1517 * Fields really needed: vendor, cpuid_level, family, model, mask, 1518 * cache alignment. 1519 * The others are not touched to avoid unwanted side effects. 1520 * 1521 * WARNING: this function is only called on the boot CPU. Don't add code 1522 * here that is supposed to run on all CPUs. 1523 */ 1524 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1525 { 1526 #ifdef CONFIG_X86_64 1527 c->x86_clflush_size = 64; 1528 c->x86_phys_bits = 36; 1529 c->x86_virt_bits = 48; 1530 #else 1531 c->x86_clflush_size = 32; 1532 c->x86_phys_bits = 32; 1533 c->x86_virt_bits = 32; 1534 #endif 1535 c->x86_cache_alignment = c->x86_clflush_size; 1536 1537 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1538 c->extended_cpuid_level = 0; 1539 1540 if (!have_cpuid_p()) 1541 identify_cpu_without_cpuid(c); 1542 1543 /* cyrix could have cpuid enabled via c_identify()*/ 1544 if (have_cpuid_p()) { 1545 cpu_detect(c); 1546 get_cpu_vendor(c); 1547 get_cpu_cap(c); 1548 get_cpu_address_sizes(c); 1549 setup_force_cpu_cap(X86_FEATURE_CPUID); 1550 cpu_parse_early_param(); 1551 1552 if (this_cpu->c_early_init) 1553 this_cpu->c_early_init(c); 1554 1555 c->cpu_index = 0; 1556 filter_cpuid_features(c, false); 1557 1558 if (this_cpu->c_bsp_init) 1559 this_cpu->c_bsp_init(c); 1560 } else { 1561 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1562 } 1563 1564 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1565 1566 cpu_set_bug_bits(c); 1567 1568 sld_setup(c); 1569 1570 fpu__init_system(c); 1571 1572 init_sigframe_size(); 1573 1574 #ifdef CONFIG_X86_32 1575 /* 1576 * Regardless of whether PCID is enumerated, the SDM says 1577 * that it can't be enabled in 32-bit mode. 1578 */ 1579 setup_clear_cpu_cap(X86_FEATURE_PCID); 1580 #endif 1581 1582 /* 1583 * Later in the boot process pgtable_l5_enabled() relies on 1584 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1585 * enabled by this point we need to clear the feature bit to avoid 1586 * false-positives at the later stage. 1587 * 1588 * pgtable_l5_enabled() can be false here for several reasons: 1589 * - 5-level paging is disabled compile-time; 1590 * - it's 32-bit kernel; 1591 * - machine doesn't support 5-level paging; 1592 * - user specified 'no5lvl' in kernel command line. 1593 */ 1594 if (!pgtable_l5_enabled()) 1595 setup_clear_cpu_cap(X86_FEATURE_LA57); 1596 1597 detect_nopl(); 1598 } 1599 1600 void __init early_cpu_init(void) 1601 { 1602 const struct cpu_dev *const *cdev; 1603 int count = 0; 1604 1605 #ifdef CONFIG_PROCESSOR_SELECT 1606 pr_info("KERNEL supported cpus:\n"); 1607 #endif 1608 1609 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1610 const struct cpu_dev *cpudev = *cdev; 1611 1612 if (count >= X86_VENDOR_NUM) 1613 break; 1614 cpu_devs[count] = cpudev; 1615 count++; 1616 1617 #ifdef CONFIG_PROCESSOR_SELECT 1618 { 1619 unsigned int j; 1620 1621 for (j = 0; j < 2; j++) { 1622 if (!cpudev->c_ident[j]) 1623 continue; 1624 pr_info(" %s %s\n", cpudev->c_vendor, 1625 cpudev->c_ident[j]); 1626 } 1627 } 1628 #endif 1629 } 1630 early_identify_cpu(&boot_cpu_data); 1631 } 1632 1633 static bool detect_null_seg_behavior(void) 1634 { 1635 /* 1636 * Empirically, writing zero to a segment selector on AMD does 1637 * not clear the base, whereas writing zero to a segment 1638 * selector on Intel does clear the base. Intel's behavior 1639 * allows slightly faster context switches in the common case 1640 * where GS is unused by the prev and next threads. 1641 * 1642 * Since neither vendor documents this anywhere that I can see, 1643 * detect it directly instead of hard-coding the choice by 1644 * vendor. 1645 * 1646 * I've designated AMD's behavior as the "bug" because it's 1647 * counterintuitive and less friendly. 1648 */ 1649 1650 unsigned long old_base, tmp; 1651 rdmsrl(MSR_FS_BASE, old_base); 1652 wrmsrl(MSR_FS_BASE, 1); 1653 loadsegment(fs, 0); 1654 rdmsrl(MSR_FS_BASE, tmp); 1655 wrmsrl(MSR_FS_BASE, old_base); 1656 return tmp == 0; 1657 } 1658 1659 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1660 { 1661 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1662 if (!IS_ENABLED(CONFIG_X86_64)) 1663 return; 1664 1665 /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ 1666 if (c->extended_cpuid_level >= 0x80000021 && 1667 cpuid_eax(0x80000021) & BIT(6)) 1668 return; 1669 1670 /* 1671 * CPUID bit above wasn't set. If this kernel is still running 1672 * as a HV guest, then the HV has decided not to advertize 1673 * that CPUID bit for whatever reason. For example, one 1674 * member of the migration pool might be vulnerable. Which 1675 * means, the bug is present: set the BUG flag and return. 1676 */ 1677 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1678 set_cpu_bug(c, X86_BUG_NULL_SEG); 1679 return; 1680 } 1681 1682 /* 1683 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1684 * 0x18 is the respective family for Hygon. 1685 */ 1686 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1687 detect_null_seg_behavior()) 1688 return; 1689 1690 /* All the remaining ones are affected */ 1691 set_cpu_bug(c, X86_BUG_NULL_SEG); 1692 } 1693 1694 static void generic_identify(struct cpuinfo_x86 *c) 1695 { 1696 c->extended_cpuid_level = 0; 1697 1698 if (!have_cpuid_p()) 1699 identify_cpu_without_cpuid(c); 1700 1701 /* cyrix could have cpuid enabled via c_identify()*/ 1702 if (!have_cpuid_p()) 1703 return; 1704 1705 cpu_detect(c); 1706 1707 get_cpu_vendor(c); 1708 1709 get_cpu_cap(c); 1710 1711 get_cpu_address_sizes(c); 1712 1713 if (c->cpuid_level >= 0x00000001) { 1714 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1715 #ifdef CONFIG_X86_32 1716 # ifdef CONFIG_SMP 1717 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1718 # else 1719 c->apicid = c->initial_apicid; 1720 # endif 1721 #endif 1722 c->phys_proc_id = c->initial_apicid; 1723 } 1724 1725 get_model_name(c); /* Default name */ 1726 1727 /* 1728 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1729 * systems that run Linux at CPL > 0 may or may not have the 1730 * issue, but, even if they have the issue, there's absolutely 1731 * nothing we can do about it because we can't use the real IRET 1732 * instruction. 1733 * 1734 * NB: For the time being, only 32-bit kernels support 1735 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1736 * whether to apply espfix using paravirt hooks. If any 1737 * non-paravirt system ever shows up that does *not* have the 1738 * ESPFIX issue, we can change this. 1739 */ 1740 #ifdef CONFIG_X86_32 1741 set_cpu_bug(c, X86_BUG_ESPFIX); 1742 #endif 1743 } 1744 1745 /* 1746 * Validate that ACPI/mptables have the same information about the 1747 * effective APIC id and update the package map. 1748 */ 1749 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1750 { 1751 #ifdef CONFIG_SMP 1752 unsigned int apicid, cpu = smp_processor_id(); 1753 1754 apicid = apic->cpu_present_to_apicid(cpu); 1755 1756 if (apicid != c->apicid) { 1757 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1758 cpu, apicid, c->initial_apicid); 1759 } 1760 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1761 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1762 #else 1763 c->logical_proc_id = 0; 1764 #endif 1765 } 1766 1767 /* 1768 * This does the hard work of actually picking apart the CPU stuff... 1769 */ 1770 static void identify_cpu(struct cpuinfo_x86 *c) 1771 { 1772 int i; 1773 1774 c->loops_per_jiffy = loops_per_jiffy; 1775 c->x86_cache_size = 0; 1776 c->x86_vendor = X86_VENDOR_UNKNOWN; 1777 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1778 c->x86_vendor_id[0] = '\0'; /* Unset */ 1779 c->x86_model_id[0] = '\0'; /* Unset */ 1780 c->x86_max_cores = 1; 1781 c->x86_coreid_bits = 0; 1782 c->cu_id = 0xff; 1783 #ifdef CONFIG_X86_64 1784 c->x86_clflush_size = 64; 1785 c->x86_phys_bits = 36; 1786 c->x86_virt_bits = 48; 1787 #else 1788 c->cpuid_level = -1; /* CPUID not detected */ 1789 c->x86_clflush_size = 32; 1790 c->x86_phys_bits = 32; 1791 c->x86_virt_bits = 32; 1792 #endif 1793 c->x86_cache_alignment = c->x86_clflush_size; 1794 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1795 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1796 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1797 #endif 1798 1799 generic_identify(c); 1800 1801 if (this_cpu->c_identify) 1802 this_cpu->c_identify(c); 1803 1804 /* Clear/Set all flags overridden by options, after probe */ 1805 apply_forced_caps(c); 1806 1807 #ifdef CONFIG_X86_64 1808 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1809 #endif 1810 1811 /* 1812 * Vendor-specific initialization. In this section we 1813 * canonicalize the feature flags, meaning if there are 1814 * features a certain CPU supports which CPUID doesn't 1815 * tell us, CPUID claiming incorrect flags, or other bugs, 1816 * we handle them here. 1817 * 1818 * At the end of this section, c->x86_capability better 1819 * indicate the features this CPU genuinely supports! 1820 */ 1821 if (this_cpu->c_init) 1822 this_cpu->c_init(c); 1823 1824 /* Disable the PN if appropriate */ 1825 squash_the_stupid_serial_number(c); 1826 1827 /* Set up SMEP/SMAP/UMIP */ 1828 setup_smep(c); 1829 setup_smap(c); 1830 setup_umip(c); 1831 1832 /* Enable FSGSBASE instructions if available. */ 1833 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1834 cr4_set_bits(X86_CR4_FSGSBASE); 1835 elf_hwcap2 |= HWCAP2_FSGSBASE; 1836 } 1837 1838 /* 1839 * The vendor-specific functions might have changed features. 1840 * Now we do "generic changes." 1841 */ 1842 1843 /* Filter out anything that depends on CPUID levels we don't have */ 1844 filter_cpuid_features(c, true); 1845 1846 /* If the model name is still unset, do table lookup. */ 1847 if (!c->x86_model_id[0]) { 1848 const char *p; 1849 p = table_lookup_model(c); 1850 if (p) 1851 strcpy(c->x86_model_id, p); 1852 else 1853 /* Last resort... */ 1854 sprintf(c->x86_model_id, "%02x/%02x", 1855 c->x86, c->x86_model); 1856 } 1857 1858 #ifdef CONFIG_X86_64 1859 detect_ht(c); 1860 #endif 1861 1862 x86_init_rdrand(c); 1863 setup_pku(c); 1864 setup_cet(c); 1865 1866 /* 1867 * Clear/Set all flags overridden by options, need do it 1868 * before following smp all cpus cap AND. 1869 */ 1870 apply_forced_caps(c); 1871 1872 /* 1873 * On SMP, boot_cpu_data holds the common feature set between 1874 * all CPUs; so make sure that we indicate which features are 1875 * common between the CPUs. The first time this routine gets 1876 * executed, c == &boot_cpu_data. 1877 */ 1878 if (c != &boot_cpu_data) { 1879 /* AND the already accumulated flags with these */ 1880 for (i = 0; i < NCAPINTS; i++) 1881 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1882 1883 /* OR, i.e. replicate the bug flags */ 1884 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1885 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1886 } 1887 1888 ppin_init(c); 1889 1890 /* Init Machine Check Exception if available. */ 1891 mcheck_cpu_init(c); 1892 1893 select_idle_routine(c); 1894 1895 #ifdef CONFIG_NUMA 1896 numa_add_cpu(smp_processor_id()); 1897 #endif 1898 } 1899 1900 /* 1901 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1902 * on 32-bit kernels: 1903 */ 1904 #ifdef CONFIG_X86_32 1905 void enable_sep_cpu(void) 1906 { 1907 struct tss_struct *tss; 1908 int cpu; 1909 1910 if (!boot_cpu_has(X86_FEATURE_SEP)) 1911 return; 1912 1913 cpu = get_cpu(); 1914 tss = &per_cpu(cpu_tss_rw, cpu); 1915 1916 /* 1917 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1918 * see the big comment in struct x86_hw_tss's definition. 1919 */ 1920 1921 tss->x86_tss.ss1 = __KERNEL_CS; 1922 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1923 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1924 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1925 1926 put_cpu(); 1927 } 1928 #endif 1929 1930 void __init identify_boot_cpu(void) 1931 { 1932 identify_cpu(&boot_cpu_data); 1933 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1934 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1935 #ifdef CONFIG_X86_32 1936 sysenter_setup(); 1937 enable_sep_cpu(); 1938 #endif 1939 cpu_detect_tlb(&boot_cpu_data); 1940 setup_cr_pinning(); 1941 1942 tsx_init(); 1943 } 1944 1945 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1946 { 1947 BUG_ON(c == &boot_cpu_data); 1948 identify_cpu(c); 1949 #ifdef CONFIG_X86_32 1950 enable_sep_cpu(); 1951 #endif 1952 validate_apic_and_package_id(c); 1953 x86_spec_ctrl_setup_ap(); 1954 update_srbds_msr(); 1955 1956 tsx_ap_init(); 1957 } 1958 1959 void print_cpu_info(struct cpuinfo_x86 *c) 1960 { 1961 const char *vendor = NULL; 1962 1963 if (c->x86_vendor < X86_VENDOR_NUM) { 1964 vendor = this_cpu->c_vendor; 1965 } else { 1966 if (c->cpuid_level >= 0) 1967 vendor = c->x86_vendor_id; 1968 } 1969 1970 if (vendor && !strstr(c->x86_model_id, vendor)) 1971 pr_cont("%s ", vendor); 1972 1973 if (c->x86_model_id[0]) 1974 pr_cont("%s", c->x86_model_id); 1975 else 1976 pr_cont("%d86", c->x86); 1977 1978 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1979 1980 if (c->x86_stepping || c->cpuid_level >= 0) 1981 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1982 else 1983 pr_cont(")\n"); 1984 } 1985 1986 /* 1987 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 1988 * function prevents it from becoming an environment variable for init. 1989 */ 1990 static __init int setup_clearcpuid(char *arg) 1991 { 1992 return 1; 1993 } 1994 __setup("clearcpuid=", setup_clearcpuid); 1995 1996 #ifdef CONFIG_X86_64 1997 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1998 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1999 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2000 2001 /* 2002 * The following percpu variables are hot. Align current_task to 2003 * cacheline size such that they fall in the same cacheline. 2004 */ 2005 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 2006 &init_task; 2007 EXPORT_PER_CPU_SYMBOL(current_task); 2008 2009 DEFINE_PER_CPU(void *, hardirq_stack_ptr); 2010 DEFINE_PER_CPU(bool, hardirq_stack_inuse); 2011 2012 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 2013 EXPORT_PER_CPU_SYMBOL(__preempt_count); 2014 2015 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; 2016 2017 static void wrmsrl_cstar(unsigned long val) 2018 { 2019 /* 2020 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2021 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2022 * guest. Avoid the pointless write on all Intel CPUs. 2023 */ 2024 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2025 wrmsrl(MSR_CSTAR, val); 2026 } 2027 2028 /* May not be marked __init: used by software suspend */ 2029 void syscall_init(void) 2030 { 2031 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2032 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2033 2034 #ifdef CONFIG_IA32_EMULATION 2035 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2036 /* 2037 * This only works on Intel CPUs. 2038 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2039 * This does not cause SYSENTER to jump to the wrong location, because 2040 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2041 */ 2042 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2043 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2044 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2045 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2046 #else 2047 wrmsrl_cstar((unsigned long)ignore_sysret); 2048 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2049 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2050 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2051 #endif 2052 2053 /* 2054 * Flags to clear on syscall; clear as much as possible 2055 * to minimize user space-kernel interference. 2056 */ 2057 wrmsrl(MSR_SYSCALL_MASK, 2058 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2059 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2060 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2061 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2062 X86_EFLAGS_AC|X86_EFLAGS_ID); 2063 } 2064 2065 #else /* CONFIG_X86_64 */ 2066 2067 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 2068 EXPORT_PER_CPU_SYMBOL(current_task); 2069 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 2070 EXPORT_PER_CPU_SYMBOL(__preempt_count); 2071 2072 /* 2073 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 2074 * the top of the kernel stack. Use an extra percpu variable to track the 2075 * top of the kernel stack directly. 2076 */ 2077 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 2078 (unsigned long)&init_thread_union + THREAD_SIZE; 2079 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 2080 2081 #ifdef CONFIG_STACKPROTECTOR 2082 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2083 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2084 #endif 2085 2086 #endif /* CONFIG_X86_64 */ 2087 2088 /* 2089 * Clear all 6 debug registers: 2090 */ 2091 static void clear_all_debug_regs(void) 2092 { 2093 int i; 2094 2095 for (i = 0; i < 8; i++) { 2096 /* Ignore db4, db5 */ 2097 if ((i == 4) || (i == 5)) 2098 continue; 2099 2100 set_debugreg(0, i); 2101 } 2102 } 2103 2104 #ifdef CONFIG_KGDB 2105 /* 2106 * Restore debug regs if using kgdbwait and you have a kernel debugger 2107 * connection established. 2108 */ 2109 static void dbg_restore_debug_regs(void) 2110 { 2111 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2112 arch_kgdb_ops.correct_hw_break(); 2113 } 2114 #else /* ! CONFIG_KGDB */ 2115 #define dbg_restore_debug_regs() 2116 #endif /* ! CONFIG_KGDB */ 2117 2118 static void wait_for_master_cpu(int cpu) 2119 { 2120 #ifdef CONFIG_SMP 2121 /* 2122 * wait for ACK from master CPU before continuing 2123 * with AP initialization 2124 */ 2125 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 2126 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 2127 cpu_relax(); 2128 #endif 2129 } 2130 2131 #ifdef CONFIG_X86_64 2132 static inline void setup_getcpu(int cpu) 2133 { 2134 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2135 struct desc_struct d = { }; 2136 2137 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2138 wrmsr(MSR_TSC_AUX, cpudata, 0); 2139 2140 /* Store CPU and node number in limit. */ 2141 d.limit0 = cpudata; 2142 d.limit1 = cpudata >> 16; 2143 2144 d.type = 5; /* RO data, expand down, accessed */ 2145 d.dpl = 3; /* Visible to user code */ 2146 d.s = 1; /* Not a system segment */ 2147 d.p = 1; /* Present */ 2148 d.d = 1; /* 32-bit */ 2149 2150 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2151 } 2152 2153 static inline void ucode_cpu_init(int cpu) 2154 { 2155 if (cpu) 2156 load_ucode_ap(); 2157 } 2158 2159 static inline void tss_setup_ist(struct tss_struct *tss) 2160 { 2161 /* Set up the per-CPU TSS IST stacks */ 2162 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2163 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2164 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2165 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2166 /* Only mapped when SEV-ES is active */ 2167 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2168 } 2169 2170 #else /* CONFIG_X86_64 */ 2171 2172 static inline void setup_getcpu(int cpu) { } 2173 2174 static inline void ucode_cpu_init(int cpu) 2175 { 2176 show_ucode_info_early(); 2177 } 2178 2179 static inline void tss_setup_ist(struct tss_struct *tss) { } 2180 2181 #endif /* !CONFIG_X86_64 */ 2182 2183 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2184 { 2185 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2186 2187 #ifdef CONFIG_X86_IOPL_IOPERM 2188 tss->io_bitmap.prev_max = 0; 2189 tss->io_bitmap.prev_sequence = 0; 2190 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2191 /* 2192 * Invalidate the extra array entry past the end of the all 2193 * permission bitmap as required by the hardware. 2194 */ 2195 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2196 #endif 2197 } 2198 2199 /* 2200 * Setup everything needed to handle exceptions from the IDT, including the IST 2201 * exceptions which use paranoid_entry(). 2202 */ 2203 void cpu_init_exception_handling(void) 2204 { 2205 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2206 int cpu = raw_smp_processor_id(); 2207 2208 /* paranoid_entry() gets the CPU number from the GDT */ 2209 setup_getcpu(cpu); 2210 2211 /* IST vectors need TSS to be set up. */ 2212 tss_setup_ist(tss); 2213 tss_setup_io_bitmap(tss); 2214 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2215 2216 load_TR_desc(); 2217 2218 /* GHCB needs to be setup to handle #VC. */ 2219 setup_ghcb(); 2220 2221 /* Finally load the IDT */ 2222 load_current_idt(); 2223 } 2224 2225 /* 2226 * cpu_init() initializes state that is per-CPU. Some data is already 2227 * initialized (naturally) in the bootstrap process, such as the GDT. We 2228 * reload it nevertheless, this function acts as a 'CPU state barrier', 2229 * nothing should get across. 2230 */ 2231 void cpu_init(void) 2232 { 2233 struct task_struct *cur = current; 2234 int cpu = raw_smp_processor_id(); 2235 2236 wait_for_master_cpu(cpu); 2237 2238 ucode_cpu_init(cpu); 2239 2240 #ifdef CONFIG_NUMA 2241 if (this_cpu_read(numa_node) == 0 && 2242 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2243 set_numa_node(early_cpu_to_node(cpu)); 2244 #endif 2245 pr_debug("Initializing CPU#%d\n", cpu); 2246 2247 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2248 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2249 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2250 2251 /* 2252 * Initialize the per-CPU GDT with the boot GDT, 2253 * and set up the GDT descriptor: 2254 */ 2255 switch_to_new_gdt(cpu); 2256 2257 if (IS_ENABLED(CONFIG_X86_64)) { 2258 loadsegment(fs, 0); 2259 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2260 syscall_init(); 2261 2262 wrmsrl(MSR_FS_BASE, 0); 2263 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2264 barrier(); 2265 2266 x2apic_setup(); 2267 } 2268 2269 mmgrab(&init_mm); 2270 cur->active_mm = &init_mm; 2271 BUG_ON(cur->mm); 2272 initialize_tlbstate_and_flush(); 2273 enter_lazy_tlb(&init_mm, cur); 2274 2275 /* 2276 * sp0 points to the entry trampoline stack regardless of what task 2277 * is running. 2278 */ 2279 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2280 2281 load_mm_ldt(&init_mm); 2282 2283 clear_all_debug_regs(); 2284 dbg_restore_debug_regs(); 2285 2286 doublefault_init_cpu_tss(); 2287 2288 fpu__init_cpu(); 2289 2290 if (is_uv_system()) 2291 uv_cpu_init(); 2292 2293 load_fixmap_gdt(cpu); 2294 } 2295 2296 #ifdef CONFIG_SMP 2297 void cpu_init_secondary(void) 2298 { 2299 /* 2300 * Relies on the BP having set-up the IDT tables, which are loaded 2301 * on this CPU in cpu_init_exception_handling(). 2302 */ 2303 cpu_init_exception_handling(); 2304 cpu_init(); 2305 } 2306 #endif 2307 2308 #ifdef CONFIG_MICROCODE_LATE_LOADING 2309 /* 2310 * The microcode loader calls this upon late microcode load to recheck features, 2311 * only when microcode has been updated. Caller holds microcode_mutex and CPU 2312 * hotplug lock. 2313 */ 2314 void microcode_check(void) 2315 { 2316 struct cpuinfo_x86 info; 2317 2318 perf_check_microcode(); 2319 2320 /* Reload CPUID max function as it might've changed. */ 2321 info.cpuid_level = cpuid_eax(0); 2322 2323 /* 2324 * Copy all capability leafs to pick up the synthetic ones so that 2325 * memcmp() below doesn't fail on that. The ones coming from CPUID will 2326 * get overwritten in get_cpu_cap(). 2327 */ 2328 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 2329 2330 get_cpu_cap(&info); 2331 2332 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 2333 return; 2334 2335 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2336 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2337 } 2338 #endif 2339 2340 /* 2341 * Invoked from core CPU hotplug code after hotplug operations 2342 */ 2343 void arch_smt_update(void) 2344 { 2345 /* Handle the speculative execution misfeatures */ 2346 cpu_bugs_smt_update(); 2347 /* Check whether IPI broadcasting can be enabled */ 2348 apic_smt_update(); 2349 } 2350