1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/sched/smt.h> 18 #include <linux/init.h> 19 #include <linux/kprobes.h> 20 #include <linux/kgdb.h> 21 #include <linux/mem_encrypt.h> 22 #include <linux/smp.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/pgtable.h> 27 #include <linux/stackprotector.h> 28 #include <linux/utsname.h> 29 30 #include <asm/alternative.h> 31 #include <asm/cmdline.h> 32 #include <asm/perf_event.h> 33 #include <asm/mmu_context.h> 34 #include <asm/doublefault.h> 35 #include <asm/archrandom.h> 36 #include <asm/hypervisor.h> 37 #include <asm/processor.h> 38 #include <asm/tlbflush.h> 39 #include <asm/debugreg.h> 40 #include <asm/sections.h> 41 #include <asm/vsyscall.h> 42 #include <linux/topology.h> 43 #include <linux/cpumask.h> 44 #include <linux/atomic.h> 45 #include <asm/proto.h> 46 #include <asm/setup.h> 47 #include <asm/apic.h> 48 #include <asm/desc.h> 49 #include <asm/fpu/api.h> 50 #include <asm/mtrr.h> 51 #include <asm/hwcap2.h> 52 #include <linux/numa.h> 53 #include <asm/numa.h> 54 #include <asm/asm.h> 55 #include <asm/bugs.h> 56 #include <asm/cpu.h> 57 #include <asm/mce.h> 58 #include <asm/msr.h> 59 #include <asm/cacheinfo.h> 60 #include <asm/memtype.h> 61 #include <asm/microcode.h> 62 #include <asm/intel-family.h> 63 #include <asm/cpu_device_id.h> 64 #include <asm/fred.h> 65 #include <asm/uv/uv.h> 66 #include <asm/ia32.h> 67 #include <asm/set_memory.h> 68 #include <asm/traps.h> 69 #include <asm/sev.h> 70 #include <asm/tdx.h> 71 72 #include "cpu.h" 73 74 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 75 EXPORT_PER_CPU_SYMBOL(cpu_info); 76 77 u32 elf_hwcap2 __read_mostly; 78 79 /* Number of siblings per CPU package */ 80 unsigned int __max_threads_per_core __ro_after_init = 1; 81 EXPORT_SYMBOL(__max_threads_per_core); 82 83 unsigned int __max_dies_per_package __ro_after_init = 1; 84 EXPORT_SYMBOL(__max_dies_per_package); 85 86 unsigned int __max_logical_packages __ro_after_init = 1; 87 EXPORT_SYMBOL(__max_logical_packages); 88 89 unsigned int __num_cores_per_package __ro_after_init = 1; 90 EXPORT_SYMBOL(__num_cores_per_package); 91 92 unsigned int __num_threads_per_package __ro_after_init = 1; 93 EXPORT_SYMBOL(__num_threads_per_package); 94 95 static struct ppin_info { 96 int feature; 97 int msr_ppin_ctl; 98 int msr_ppin; 99 } ppin_info[] = { 100 [X86_VENDOR_INTEL] = { 101 .feature = X86_FEATURE_INTEL_PPIN, 102 .msr_ppin_ctl = MSR_PPIN_CTL, 103 .msr_ppin = MSR_PPIN 104 }, 105 [X86_VENDOR_AMD] = { 106 .feature = X86_FEATURE_AMD_PPIN, 107 .msr_ppin_ctl = MSR_AMD_PPIN_CTL, 108 .msr_ppin = MSR_AMD_PPIN 109 }, 110 }; 111 112 static const struct x86_cpu_id ppin_cpuids[] = { 113 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), 114 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), 115 116 /* Legacy models without CPUID enumeration */ 117 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), 118 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), 119 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), 120 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), 121 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), 122 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), 123 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), 124 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 125 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), 126 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), 127 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), 128 129 {} 130 }; 131 132 static void ppin_init(struct cpuinfo_x86 *c) 133 { 134 const struct x86_cpu_id *id; 135 unsigned long long val; 136 struct ppin_info *info; 137 138 id = x86_match_cpu(ppin_cpuids); 139 if (!id) 140 return; 141 142 /* 143 * Testing the presence of the MSR is not enough. Need to check 144 * that the PPIN_CTL allows reading of the PPIN. 145 */ 146 info = (struct ppin_info *)id->driver_data; 147 148 if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 149 goto clear_ppin; 150 151 if ((val & 3UL) == 1UL) { 152 /* PPIN locked in disabled mode */ 153 goto clear_ppin; 154 } 155 156 /* If PPIN is disabled, try to enable */ 157 if (!(val & 2UL)) { 158 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 159 rdmsrl_safe(info->msr_ppin_ctl, &val); 160 } 161 162 /* Is the enable bit set? */ 163 if (val & 2UL) { 164 c->ppin = __rdmsr(info->msr_ppin); 165 set_cpu_cap(c, info->feature); 166 return; 167 } 168 169 clear_ppin: 170 clear_cpu_cap(c, info->feature); 171 } 172 173 static void default_init(struct cpuinfo_x86 *c) 174 { 175 #ifdef CONFIG_X86_64 176 cpu_detect_cache_sizes(c); 177 #else 178 /* Not much we can do here... */ 179 /* Check if at least it has cpuid */ 180 if (c->cpuid_level == -1) { 181 /* No cpuid. It must be an ancient CPU */ 182 if (c->x86 == 4) 183 strcpy(c->x86_model_id, "486"); 184 else if (c->x86 == 3) 185 strcpy(c->x86_model_id, "386"); 186 } 187 #endif 188 } 189 190 static const struct cpu_dev default_cpu = { 191 .c_init = default_init, 192 .c_vendor = "Unknown", 193 .c_x86_vendor = X86_VENDOR_UNKNOWN, 194 }; 195 196 static const struct cpu_dev *this_cpu = &default_cpu; 197 198 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 199 #ifdef CONFIG_X86_64 200 /* 201 * We need valid kernel segments for data and code in long mode too 202 * IRET will check the segment types kkeil 2000/10/28 203 * Also sysret mandates a special GDT layout 204 * 205 * TLS descriptors are currently at a different place compared to i386. 206 * Hopefully nobody expects them at a fixed place (Wine?) 207 */ 208 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 209 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff), 210 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff), 211 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 212 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff), 213 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff), 214 #else 215 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff), 216 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 217 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff), 218 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff), 219 /* 220 * Segments used for calling PnP BIOS have byte granularity. 221 * They code segments and data segments have fixed 64k limits, 222 * the transfer segment sizes are set at run time. 223 */ 224 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 225 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 226 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff), 227 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 228 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0), 229 /* 230 * The APM segments have byte granularity and their bases 231 * are set at run time. All have 64k limits. 232 */ 233 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff), 234 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff), 235 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff), 236 237 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 238 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff), 239 #endif 240 } }; 241 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 242 243 #ifdef CONFIG_X86_64 244 static int __init x86_nopcid_setup(char *s) 245 { 246 /* nopcid doesn't accept parameters */ 247 if (s) 248 return -EINVAL; 249 250 /* do not emit a message if the feature is not present */ 251 if (!boot_cpu_has(X86_FEATURE_PCID)) 252 return 0; 253 254 setup_clear_cpu_cap(X86_FEATURE_PCID); 255 pr_info("nopcid: PCID feature disabled\n"); 256 return 0; 257 } 258 early_param("nopcid", x86_nopcid_setup); 259 #endif 260 261 static int __init x86_noinvpcid_setup(char *s) 262 { 263 /* noinvpcid doesn't accept parameters */ 264 if (s) 265 return -EINVAL; 266 267 /* do not emit a message if the feature is not present */ 268 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 269 return 0; 270 271 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 272 pr_info("noinvpcid: INVPCID feature disabled\n"); 273 return 0; 274 } 275 early_param("noinvpcid", x86_noinvpcid_setup); 276 277 #ifdef CONFIG_X86_32 278 static int cachesize_override = -1; 279 static int disable_x86_serial_nr = 1; 280 281 static int __init cachesize_setup(char *str) 282 { 283 get_option(&str, &cachesize_override); 284 return 1; 285 } 286 __setup("cachesize=", cachesize_setup); 287 288 /* Standard macro to see if a specific flag is changeable */ 289 static inline int flag_is_changeable_p(u32 flag) 290 { 291 u32 f1, f2; 292 293 /* 294 * Cyrix and IDT cpus allow disabling of CPUID 295 * so the code below may return different results 296 * when it is executed before and after enabling 297 * the CPUID. Add "volatile" to not allow gcc to 298 * optimize the subsequent calls to this function. 299 */ 300 asm volatile ("pushfl \n\t" 301 "pushfl \n\t" 302 "popl %0 \n\t" 303 "movl %0, %1 \n\t" 304 "xorl %2, %0 \n\t" 305 "pushl %0 \n\t" 306 "popfl \n\t" 307 "pushfl \n\t" 308 "popl %0 \n\t" 309 "popfl \n\t" 310 311 : "=&r" (f1), "=&r" (f2) 312 : "ir" (flag)); 313 314 return ((f1^f2) & flag) != 0; 315 } 316 317 /* Probe for the CPUID instruction */ 318 int have_cpuid_p(void) 319 { 320 return flag_is_changeable_p(X86_EFLAGS_ID); 321 } 322 323 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 324 { 325 unsigned long lo, hi; 326 327 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 328 return; 329 330 /* Disable processor serial number: */ 331 332 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 333 lo |= 0x200000; 334 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 335 336 pr_notice("CPU serial number disabled.\n"); 337 clear_cpu_cap(c, X86_FEATURE_PN); 338 339 /* Disabling the serial number may affect the cpuid level */ 340 c->cpuid_level = cpuid_eax(0); 341 } 342 343 static int __init x86_serial_nr_setup(char *s) 344 { 345 disable_x86_serial_nr = 0; 346 return 1; 347 } 348 __setup("serialnumber", x86_serial_nr_setup); 349 #else 350 static inline int flag_is_changeable_p(u32 flag) 351 { 352 return 1; 353 } 354 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 355 { 356 } 357 #endif 358 359 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 360 { 361 if (cpu_has(c, X86_FEATURE_SMEP)) 362 cr4_set_bits(X86_CR4_SMEP); 363 } 364 365 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 366 { 367 unsigned long eflags = native_save_fl(); 368 369 /* This should have been cleared long ago */ 370 BUG_ON(eflags & X86_EFLAGS_AC); 371 372 if (cpu_has(c, X86_FEATURE_SMAP)) 373 cr4_set_bits(X86_CR4_SMAP); 374 } 375 376 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 377 { 378 /* Check the boot processor, plus build option for UMIP. */ 379 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 380 goto out; 381 382 /* Check the current processor's cpuid bits. */ 383 if (!cpu_has(c, X86_FEATURE_UMIP)) 384 goto out; 385 386 cr4_set_bits(X86_CR4_UMIP); 387 388 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 389 390 return; 391 392 out: 393 /* 394 * Make sure UMIP is disabled in case it was enabled in a 395 * previous boot (e.g., via kexec). 396 */ 397 cr4_clear_bits(X86_CR4_UMIP); 398 } 399 400 /* These bits should not change their value after CPU init is finished. */ 401 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | 402 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; 403 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 404 static unsigned long cr4_pinned_bits __ro_after_init; 405 406 void native_write_cr0(unsigned long val) 407 { 408 unsigned long bits_missing = 0; 409 410 set_register: 411 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); 412 413 if (static_branch_likely(&cr_pinning)) { 414 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 415 bits_missing = X86_CR0_WP; 416 val |= bits_missing; 417 goto set_register; 418 } 419 /* Warn after we've set the missing bits. */ 420 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 421 } 422 } 423 EXPORT_SYMBOL(native_write_cr0); 424 425 void __no_profile native_write_cr4(unsigned long val) 426 { 427 unsigned long bits_changed = 0; 428 429 set_register: 430 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); 431 432 if (static_branch_likely(&cr_pinning)) { 433 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { 434 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; 435 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; 436 goto set_register; 437 } 438 /* Warn after we've corrected the changed bits. */ 439 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", 440 bits_changed); 441 } 442 } 443 #if IS_MODULE(CONFIG_LKDTM) 444 EXPORT_SYMBOL_GPL(native_write_cr4); 445 #endif 446 447 void cr4_update_irqsoff(unsigned long set, unsigned long clear) 448 { 449 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); 450 451 lockdep_assert_irqs_disabled(); 452 453 newval = (cr4 & ~clear) | set; 454 if (newval != cr4) { 455 this_cpu_write(cpu_tlbstate.cr4, newval); 456 __write_cr4(newval); 457 } 458 } 459 EXPORT_SYMBOL(cr4_update_irqsoff); 460 461 /* Read the CR4 shadow. */ 462 unsigned long cr4_read_shadow(void) 463 { 464 return this_cpu_read(cpu_tlbstate.cr4); 465 } 466 EXPORT_SYMBOL_GPL(cr4_read_shadow); 467 468 void cr4_init(void) 469 { 470 unsigned long cr4 = __read_cr4(); 471 472 if (boot_cpu_has(X86_FEATURE_PCID)) 473 cr4 |= X86_CR4_PCIDE; 474 if (static_branch_likely(&cr_pinning)) 475 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; 476 477 __write_cr4(cr4); 478 479 /* Initialize cr4 shadow for this CPU. */ 480 this_cpu_write(cpu_tlbstate.cr4, cr4); 481 } 482 483 /* 484 * Once CPU feature detection is finished (and boot params have been 485 * parsed), record any of the sensitive CR bits that are set, and 486 * enable CR pinning. 487 */ 488 static void __init setup_cr_pinning(void) 489 { 490 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; 491 static_key_enable(&cr_pinning.key); 492 } 493 494 static __init int x86_nofsgsbase_setup(char *arg) 495 { 496 /* Require an exact match without trailing characters. */ 497 if (strlen(arg)) 498 return 0; 499 500 /* Do not emit a message if the feature is not present. */ 501 if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) 502 return 1; 503 504 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); 505 pr_info("FSGSBASE disabled via kernel command line\n"); 506 return 1; 507 } 508 __setup("nofsgsbase", x86_nofsgsbase_setup); 509 510 /* 511 * Protection Keys are not available in 32-bit mode. 512 */ 513 static bool pku_disabled; 514 515 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 516 { 517 if (c == &boot_cpu_data) { 518 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) 519 return; 520 /* 521 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid 522 * bit to be set. Enforce it. 523 */ 524 setup_force_cpu_cap(X86_FEATURE_OSPKE); 525 526 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { 527 return; 528 } 529 530 cr4_set_bits(X86_CR4_PKE); 531 /* Load the default PKRU value */ 532 pkru_write_default(); 533 } 534 535 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 536 static __init int setup_disable_pku(char *arg) 537 { 538 /* 539 * Do not clear the X86_FEATURE_PKU bit. All of the 540 * runtime checks are against OSPKE so clearing the 541 * bit does nothing. 542 * 543 * This way, we will see "pku" in cpuinfo, but not 544 * "ospke", which is exactly what we want. It shows 545 * that the CPU has PKU, but the OS has not enabled it. 546 * This happens to be exactly how a system would look 547 * if we disabled the config option. 548 */ 549 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 550 pku_disabled = true; 551 return 1; 552 } 553 __setup("nopku", setup_disable_pku); 554 #endif 555 556 #ifdef CONFIG_X86_KERNEL_IBT 557 558 __noendbr u64 ibt_save(bool disable) 559 { 560 u64 msr = 0; 561 562 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 563 rdmsrl(MSR_IA32_S_CET, msr); 564 if (disable) 565 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 566 } 567 568 return msr; 569 } 570 571 __noendbr void ibt_restore(u64 save) 572 { 573 u64 msr; 574 575 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 576 rdmsrl(MSR_IA32_S_CET, msr); 577 msr &= ~CET_ENDBR_EN; 578 msr |= (save & CET_ENDBR_EN); 579 wrmsrl(MSR_IA32_S_CET, msr); 580 } 581 } 582 583 #endif 584 585 static __always_inline void setup_cet(struct cpuinfo_x86 *c) 586 { 587 bool user_shstk, kernel_ibt; 588 589 if (!IS_ENABLED(CONFIG_X86_CET)) 590 return; 591 592 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT); 593 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) && 594 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK); 595 596 if (!kernel_ibt && !user_shstk) 597 return; 598 599 if (user_shstk) 600 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 601 602 if (kernel_ibt) 603 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN); 604 else 605 wrmsrl(MSR_IA32_S_CET, 0); 606 607 cr4_set_bits(X86_CR4_CET); 608 609 if (kernel_ibt && ibt_selftest()) { 610 pr_err("IBT selftest: Failed!\n"); 611 wrmsrl(MSR_IA32_S_CET, 0); 612 setup_clear_cpu_cap(X86_FEATURE_IBT); 613 } 614 } 615 616 __noendbr void cet_disable(void) 617 { 618 if (!(cpu_feature_enabled(X86_FEATURE_IBT) || 619 cpu_feature_enabled(X86_FEATURE_SHSTK))) 620 return; 621 622 wrmsrl(MSR_IA32_S_CET, 0); 623 wrmsrl(MSR_IA32_U_CET, 0); 624 } 625 626 /* 627 * Some CPU features depend on higher CPUID levels, which may not always 628 * be available due to CPUID level capping or broken virtualization 629 * software. Add those features to this table to auto-disable them. 630 */ 631 struct cpuid_dependent_feature { 632 u32 feature; 633 u32 level; 634 }; 635 636 static const struct cpuid_dependent_feature 637 cpuid_dependent_features[] = { 638 { X86_FEATURE_MWAIT, 0x00000005 }, 639 { X86_FEATURE_DCA, 0x00000009 }, 640 { X86_FEATURE_XSAVE, 0x0000000d }, 641 { 0, 0 } 642 }; 643 644 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 645 { 646 const struct cpuid_dependent_feature *df; 647 648 for (df = cpuid_dependent_features; df->feature; df++) { 649 650 if (!cpu_has(c, df->feature)) 651 continue; 652 /* 653 * Note: cpuid_level is set to -1 if unavailable, but 654 * extended_extended_level is set to 0 if unavailable 655 * and the legitimate extended levels are all negative 656 * when signed; hence the weird messing around with 657 * signs here... 658 */ 659 if (!((s32)df->level < 0 ? 660 (u32)df->level > (u32)c->extended_cpuid_level : 661 (s32)df->level > (s32)c->cpuid_level)) 662 continue; 663 664 clear_cpu_cap(c, df->feature); 665 if (!warn) 666 continue; 667 668 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 669 x86_cap_flag(df->feature), df->level); 670 } 671 } 672 673 /* 674 * Naming convention should be: <Name> [(<Codename>)] 675 * This table only is used unless init_<vendor>() below doesn't set it; 676 * in particular, if CPUID levels 0x80000002..4 are supported, this 677 * isn't used 678 */ 679 680 /* Look up CPU names by table lookup. */ 681 static const char *table_lookup_model(struct cpuinfo_x86 *c) 682 { 683 #ifdef CONFIG_X86_32 684 const struct legacy_cpu_model_info *info; 685 686 if (c->x86_model >= 16) 687 return NULL; /* Range check */ 688 689 if (!this_cpu) 690 return NULL; 691 692 info = this_cpu->legacy_models; 693 694 while (info->family) { 695 if (info->family == c->x86) 696 return info->model_names[c->x86_model]; 697 info++; 698 } 699 #endif 700 return NULL; /* Not found */ 701 } 702 703 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 704 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 705 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 706 707 #ifdef CONFIG_X86_32 708 /* The 32-bit entry code needs to find cpu_entry_area. */ 709 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 710 #endif 711 712 /* Load the original GDT from the per-cpu structure */ 713 void load_direct_gdt(int cpu) 714 { 715 struct desc_ptr gdt_descr; 716 717 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 718 gdt_descr.size = GDT_SIZE - 1; 719 load_gdt(&gdt_descr); 720 } 721 EXPORT_SYMBOL_GPL(load_direct_gdt); 722 723 /* Load a fixmap remapping of the per-cpu GDT */ 724 void load_fixmap_gdt(int cpu) 725 { 726 struct desc_ptr gdt_descr; 727 728 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 729 gdt_descr.size = GDT_SIZE - 1; 730 load_gdt(&gdt_descr); 731 } 732 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 733 734 /** 735 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base 736 * @cpu: The CPU number for which this is invoked 737 * 738 * Invoked during early boot to switch from early GDT and early per CPU to 739 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base 740 * switch is implicit by loading the direct GDT. On 64bit this requires 741 * to update GSBASE. 742 */ 743 void __init switch_gdt_and_percpu_base(int cpu) 744 { 745 load_direct_gdt(cpu); 746 747 #ifdef CONFIG_X86_64 748 /* 749 * No need to load %gs. It is already correct. 750 * 751 * Writing %gs on 64bit would zero GSBASE which would make any per 752 * CPU operation up to the point of the wrmsrl() fault. 753 * 754 * Set GSBASE to the new offset. Until the wrmsrl() happens the 755 * early mapping is still valid. That means the GSBASE update will 756 * lose any prior per CPU data which was not copied over in 757 * setup_per_cpu_areas(). 758 * 759 * This works even with stackprotector enabled because the 760 * per CPU stack canary is 0 in both per CPU areas. 761 */ 762 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 763 #else 764 /* 765 * %fs is already set to __KERNEL_PERCPU, but after switching GDT 766 * it is required to load FS again so that the 'hidden' part is 767 * updated from the new GDT. Up to this point the early per CPU 768 * translation is active. Any content of the early per CPU data 769 * which was not copied over in setup_per_cpu_areas() is lost. 770 */ 771 loadsegment(fs, __KERNEL_PERCPU); 772 #endif 773 } 774 775 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 776 777 static void get_model_name(struct cpuinfo_x86 *c) 778 { 779 unsigned int *v; 780 char *p, *q, *s; 781 782 if (c->extended_cpuid_level < 0x80000004) 783 return; 784 785 v = (unsigned int *)c->x86_model_id; 786 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 787 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 788 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 789 c->x86_model_id[48] = 0; 790 791 /* Trim whitespace */ 792 p = q = s = &c->x86_model_id[0]; 793 794 while (*p == ' ') 795 p++; 796 797 while (*p) { 798 /* Note the last non-whitespace index */ 799 if (!isspace(*p)) 800 s = q; 801 802 *q++ = *p++; 803 } 804 805 *(s + 1) = '\0'; 806 } 807 808 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 809 { 810 unsigned int n, dummy, ebx, ecx, edx, l2size; 811 812 n = c->extended_cpuid_level; 813 814 if (n >= 0x80000005) { 815 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 816 c->x86_cache_size = (ecx>>24) + (edx>>24); 817 #ifdef CONFIG_X86_64 818 /* On K8 L1 TLB is inclusive, so don't count it */ 819 c->x86_tlbsize = 0; 820 #endif 821 } 822 823 if (n < 0x80000006) /* Some chips just has a large L1. */ 824 return; 825 826 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 827 l2size = ecx >> 16; 828 829 #ifdef CONFIG_X86_64 830 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 831 #else 832 /* do processor-specific cache resizing */ 833 if (this_cpu->legacy_cache_size) 834 l2size = this_cpu->legacy_cache_size(c, l2size); 835 836 /* Allow user to override all this if necessary. */ 837 if (cachesize_override != -1) 838 l2size = cachesize_override; 839 840 if (l2size == 0) 841 return; /* Again, no L2 cache is possible */ 842 #endif 843 844 c->x86_cache_size = l2size; 845 } 846 847 u16 __read_mostly tlb_lli_4k[NR_INFO]; 848 u16 __read_mostly tlb_lli_2m[NR_INFO]; 849 u16 __read_mostly tlb_lli_4m[NR_INFO]; 850 u16 __read_mostly tlb_lld_4k[NR_INFO]; 851 u16 __read_mostly tlb_lld_2m[NR_INFO]; 852 u16 __read_mostly tlb_lld_4m[NR_INFO]; 853 u16 __read_mostly tlb_lld_1g[NR_INFO]; 854 855 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 856 { 857 if (this_cpu->c_detect_tlb) 858 this_cpu->c_detect_tlb(c); 859 860 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 861 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 862 tlb_lli_4m[ENTRIES]); 863 864 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 865 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 866 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 867 } 868 869 static void get_cpu_vendor(struct cpuinfo_x86 *c) 870 { 871 char *v = c->x86_vendor_id; 872 int i; 873 874 for (i = 0; i < X86_VENDOR_NUM; i++) { 875 if (!cpu_devs[i]) 876 break; 877 878 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 879 (cpu_devs[i]->c_ident[1] && 880 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 881 882 this_cpu = cpu_devs[i]; 883 c->x86_vendor = this_cpu->c_x86_vendor; 884 return; 885 } 886 } 887 888 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 889 "CPU: Your system may be unstable.\n", v); 890 891 c->x86_vendor = X86_VENDOR_UNKNOWN; 892 this_cpu = &default_cpu; 893 } 894 895 void cpu_detect(struct cpuinfo_x86 *c) 896 { 897 /* Get vendor name */ 898 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 899 (unsigned int *)&c->x86_vendor_id[0], 900 (unsigned int *)&c->x86_vendor_id[8], 901 (unsigned int *)&c->x86_vendor_id[4]); 902 903 c->x86 = 4; 904 /* Intel-defined flags: level 0x00000001 */ 905 if (c->cpuid_level >= 0x00000001) { 906 u32 junk, tfms, cap0, misc; 907 908 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 909 c->x86 = x86_family(tfms); 910 c->x86_model = x86_model(tfms); 911 c->x86_stepping = x86_stepping(tfms); 912 913 if (cap0 & (1<<19)) { 914 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 915 c->x86_cache_alignment = c->x86_clflush_size; 916 } 917 } 918 } 919 920 static void apply_forced_caps(struct cpuinfo_x86 *c) 921 { 922 int i; 923 924 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 925 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 926 c->x86_capability[i] |= cpu_caps_set[i]; 927 } 928 } 929 930 static void init_speculation_control(struct cpuinfo_x86 *c) 931 { 932 /* 933 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 934 * and they also have a different bit for STIBP support. Also, 935 * a hypervisor might have set the individual AMD bits even on 936 * Intel CPUs, for finer-grained selection of what's available. 937 */ 938 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 939 set_cpu_cap(c, X86_FEATURE_IBRS); 940 set_cpu_cap(c, X86_FEATURE_IBPB); 941 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 942 } 943 944 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 945 set_cpu_cap(c, X86_FEATURE_STIBP); 946 947 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 948 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 949 set_cpu_cap(c, X86_FEATURE_SSBD); 950 951 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 952 set_cpu_cap(c, X86_FEATURE_IBRS); 953 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 954 } 955 956 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 957 set_cpu_cap(c, X86_FEATURE_IBPB); 958 959 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 960 set_cpu_cap(c, X86_FEATURE_STIBP); 961 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 962 } 963 964 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 965 set_cpu_cap(c, X86_FEATURE_SSBD); 966 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 967 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 968 } 969 } 970 971 void get_cpu_cap(struct cpuinfo_x86 *c) 972 { 973 u32 eax, ebx, ecx, edx; 974 975 /* Intel-defined flags: level 0x00000001 */ 976 if (c->cpuid_level >= 0x00000001) { 977 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 978 979 c->x86_capability[CPUID_1_ECX] = ecx; 980 c->x86_capability[CPUID_1_EDX] = edx; 981 } 982 983 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 984 if (c->cpuid_level >= 0x00000006) 985 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 986 987 /* Additional Intel-defined flags: level 0x00000007 */ 988 if (c->cpuid_level >= 0x00000007) { 989 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 990 c->x86_capability[CPUID_7_0_EBX] = ebx; 991 c->x86_capability[CPUID_7_ECX] = ecx; 992 c->x86_capability[CPUID_7_EDX] = edx; 993 994 /* Check valid sub-leaf index before accessing it */ 995 if (eax >= 1) { 996 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 997 c->x86_capability[CPUID_7_1_EAX] = eax; 998 } 999 } 1000 1001 /* Extended state features: level 0x0000000d */ 1002 if (c->cpuid_level >= 0x0000000d) { 1003 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 1004 1005 c->x86_capability[CPUID_D_1_EAX] = eax; 1006 } 1007 1008 /* AMD-defined flags: level 0x80000001 */ 1009 eax = cpuid_eax(0x80000000); 1010 c->extended_cpuid_level = eax; 1011 1012 if ((eax & 0xffff0000) == 0x80000000) { 1013 if (eax >= 0x80000001) { 1014 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 1015 1016 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 1017 c->x86_capability[CPUID_8000_0001_EDX] = edx; 1018 } 1019 } 1020 1021 if (c->extended_cpuid_level >= 0x80000007) { 1022 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 1023 1024 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 1025 c->x86_power = edx; 1026 } 1027 1028 if (c->extended_cpuid_level >= 0x80000008) { 1029 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1030 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 1031 } 1032 1033 if (c->extended_cpuid_level >= 0x8000000a) 1034 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 1035 1036 if (c->extended_cpuid_level >= 0x8000001f) 1037 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); 1038 1039 if (c->extended_cpuid_level >= 0x80000021) 1040 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); 1041 1042 init_scattered_cpuid_features(c); 1043 init_speculation_control(c); 1044 1045 /* 1046 * Clear/Set all flags overridden by options, after probe. 1047 * This needs to happen each time we re-probe, which may happen 1048 * several times during CPU initialization. 1049 */ 1050 apply_forced_caps(c); 1051 } 1052 1053 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 1054 { 1055 u32 eax, ebx, ecx, edx; 1056 1057 if (!cpu_has(c, X86_FEATURE_CPUID) || 1058 (c->extended_cpuid_level < 0x80000008)) { 1059 if (IS_ENABLED(CONFIG_X86_64)) { 1060 c->x86_clflush_size = 64; 1061 c->x86_phys_bits = 36; 1062 c->x86_virt_bits = 48; 1063 } else { 1064 c->x86_clflush_size = 32; 1065 c->x86_virt_bits = 32; 1066 c->x86_phys_bits = 32; 1067 1068 if (cpu_has(c, X86_FEATURE_PAE) || 1069 cpu_has(c, X86_FEATURE_PSE36)) 1070 c->x86_phys_bits = 36; 1071 } 1072 } else { 1073 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 1074 1075 c->x86_virt_bits = (eax >> 8) & 0xff; 1076 c->x86_phys_bits = eax & 0xff; 1077 } 1078 1079 c->x86_cache_bits = c->x86_phys_bits; 1080 c->x86_cache_alignment = c->x86_clflush_size; 1081 } 1082 1083 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 1084 { 1085 #ifdef CONFIG_X86_32 1086 int i; 1087 1088 /* 1089 * First of all, decide if this is a 486 or higher 1090 * It's a 486 if we can modify the AC flag 1091 */ 1092 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1093 c->x86 = 4; 1094 else 1095 c->x86 = 3; 1096 1097 for (i = 0; i < X86_VENDOR_NUM; i++) 1098 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1099 c->x86_vendor_id[0] = 0; 1100 cpu_devs[i]->c_identify(c); 1101 if (c->x86_vendor_id[0]) { 1102 get_cpu_vendor(c); 1103 break; 1104 } 1105 } 1106 #endif 1107 } 1108 1109 #define NO_SPECULATION BIT(0) 1110 #define NO_MELTDOWN BIT(1) 1111 #define NO_SSB BIT(2) 1112 #define NO_L1TF BIT(3) 1113 #define NO_MDS BIT(4) 1114 #define MSBDS_ONLY BIT(5) 1115 #define NO_SWAPGS BIT(6) 1116 #define NO_ITLB_MULTIHIT BIT(7) 1117 #define NO_SPECTRE_V2 BIT(8) 1118 #define NO_MMIO BIT(9) 1119 #define NO_EIBRS_PBRSB BIT(10) 1120 #define NO_BHI BIT(11) 1121 1122 #define VULNWL(vendor, family, model, whitelist) \ 1123 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) 1124 1125 #define VULNWL_INTEL(vfm, whitelist) \ 1126 X86_MATCH_VFM(vfm, whitelist) 1127 1128 #define VULNWL_AMD(family, whitelist) \ 1129 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1130 1131 #define VULNWL_HYGON(family, whitelist) \ 1132 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1133 1134 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1135 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1136 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1137 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1138 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1139 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), 1140 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), 1141 1142 /* Intel Family 6 */ 1143 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), 1144 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), 1145 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), 1146 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), 1147 1148 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1149 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1150 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1151 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1152 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1153 1154 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1155 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1156 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1157 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1158 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1159 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1160 1161 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), 1162 1163 VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1164 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1165 1166 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1167 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), 1168 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), 1169 1170 /* 1171 * Technically, swapgs isn't serializing on AMD (despite it previously 1172 * being documented as such in the APM). But according to AMD, %gs is 1173 * updated non-speculatively, and the issuing of %gs-relative memory 1174 * operands will be blocked until the %gs update completes, which is 1175 * good enough for our purposes. 1176 */ 1177 1178 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), 1179 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), 1180 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), 1181 1182 /* AMD Family 0xf - 0x12 */ 1183 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1184 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1185 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1186 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), 1187 1188 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1189 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1190 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI), 1191 1192 /* Zhaoxin Family 7 */ 1193 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1194 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI), 1195 {} 1196 }; 1197 1198 #define VULNBL(vendor, family, model, blacklist) \ 1199 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) 1200 1201 #define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ 1202 X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues) 1203 1204 #define VULNBL_AMD(family, blacklist) \ 1205 VULNBL(AMD, family, X86_MODEL_ANY, blacklist) 1206 1207 #define VULNBL_HYGON(family, blacklist) \ 1208 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) 1209 1210 #define SRBDS BIT(0) 1211 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ 1212 #define MMIO BIT(1) 1213 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ 1214 #define MMIO_SBDS BIT(2) 1215 /* CPU is affected by RETbleed, speculating where you would not expect it */ 1216 #define RETBLEED BIT(3) 1217 /* CPU is affected by SMT (cross-thread) return predictions */ 1218 #define SMT_RSB BIT(4) 1219 /* CPU is affected by SRSO */ 1220 #define SRSO BIT(5) 1221 /* CPU is affected by GDS */ 1222 #define GDS BIT(6) 1223 /* CPU is affected by Register File Data Sampling */ 1224 #define RFDS BIT(7) 1225 1226 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { 1227 VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), 1228 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS), 1229 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS), 1230 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS), 1231 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO), 1232 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO), 1233 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS), 1234 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO), 1235 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS), 1236 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1237 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1238 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1239 VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1240 VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), 1241 VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), 1242 VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1243 VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), 1244 VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), 1245 VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1246 VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), 1247 VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), 1248 VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS), 1249 VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS), 1250 VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), 1251 VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), 1252 VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS), 1253 VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS), 1254 VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS), 1255 VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), 1256 VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), 1257 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), 1258 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), 1259 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS), 1260 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), 1261 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS), 1262 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS), 1263 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS), 1264 1265 VULNBL_AMD(0x15, RETBLEED), 1266 VULNBL_AMD(0x16, RETBLEED), 1267 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), 1268 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), 1269 VULNBL_AMD(0x19, SRSO), 1270 {} 1271 }; 1272 1273 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) 1274 { 1275 const struct x86_cpu_id *m = x86_match_cpu(table); 1276 1277 return m && !!(m->driver_data & which); 1278 } 1279 1280 u64 x86_read_arch_cap_msr(void) 1281 { 1282 u64 x86_arch_cap_msr = 0; 1283 1284 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1285 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1286 1287 return x86_arch_cap_msr; 1288 } 1289 1290 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr) 1291 { 1292 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO && 1293 x86_arch_cap_msr & ARCH_CAP_PSDP_NO && 1294 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO); 1295 } 1296 1297 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr) 1298 { 1299 /* The "immunity" bit trumps everything else: */ 1300 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO) 1301 return false; 1302 1303 /* 1304 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to 1305 * indicate that mitigation is needed because guest is running on a 1306 * vulnerable hardware or may migrate to such hardware: 1307 */ 1308 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) 1309 return true; 1310 1311 /* Only consult the blacklist when there is no enumeration: */ 1312 return cpu_matches(cpu_vuln_blacklist, RFDS); 1313 } 1314 1315 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1316 { 1317 u64 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1318 1319 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1320 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && 1321 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO)) 1322 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1323 1324 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) 1325 return; 1326 1327 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1328 1329 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) 1330 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1331 1332 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && 1333 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) && 1334 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1335 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1336 1337 /* 1338 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature 1339 * flag and protect from vendor-specific bugs via the whitelist. 1340 * 1341 * Don't use AutoIBRS when SNP is enabled because it degrades host 1342 * userspace indirect branch performance. 1343 */ 1344 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) || 1345 (cpu_has(c, X86_FEATURE_AUTOIBRS) && 1346 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { 1347 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1348 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && 1349 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO)) 1350 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); 1351 } 1352 1353 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && 1354 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) { 1355 setup_force_cpu_bug(X86_BUG_MDS); 1356 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) 1357 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1358 } 1359 1360 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) 1361 setup_force_cpu_bug(X86_BUG_SWAPGS); 1362 1363 /* 1364 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1365 * - TSX is supported or 1366 * - TSX_CTRL is present 1367 * 1368 * TSX_CTRL check is needed for cases when TSX could be disabled before 1369 * the kernel boot e.g. kexec. 1370 * TSX_CTRL check alone is not sufficient for cases when the microcode 1371 * update is not present or running as guest that don't get TSX_CTRL. 1372 */ 1373 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) && 1374 (cpu_has(c, X86_FEATURE_RTM) || 1375 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR))) 1376 setup_force_cpu_bug(X86_BUG_TAA); 1377 1378 /* 1379 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed 1380 * in the vulnerability blacklist. 1381 * 1382 * Some of the implications and mitigation of Shared Buffers Data 1383 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as 1384 * SRBDS. 1385 */ 1386 if ((cpu_has(c, X86_FEATURE_RDRAND) || 1387 cpu_has(c, X86_FEATURE_RDSEED)) && 1388 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) 1389 setup_force_cpu_bug(X86_BUG_SRBDS); 1390 1391 /* 1392 * Processor MMIO Stale Data bug enumeration 1393 * 1394 * Affected CPU list is generally enough to enumerate the vulnerability, 1395 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may 1396 * not want the guest to enumerate the bug. 1397 * 1398 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, 1399 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. 1400 */ 1401 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) { 1402 if (cpu_matches(cpu_vuln_blacklist, MMIO)) 1403 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); 1404 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) 1405 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); 1406 } 1407 1408 if (!cpu_has(c, X86_FEATURE_BTC_NO)) { 1409 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA)) 1410 setup_force_cpu_bug(X86_BUG_RETBLEED); 1411 } 1412 1413 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB)) 1414 setup_force_cpu_bug(X86_BUG_SMT_RSB); 1415 1416 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) { 1417 if (cpu_matches(cpu_vuln_blacklist, SRSO)) 1418 setup_force_cpu_bug(X86_BUG_SRSO); 1419 } 1420 1421 /* 1422 * Check if CPU is vulnerable to GDS. If running in a virtual machine on 1423 * an affected processor, the VMM may have disabled the use of GATHER by 1424 * disabling AVX2. The only way to do this in HW is to clear XCR0[2], 1425 * which means that AVX will be disabled. 1426 */ 1427 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) && 1428 boot_cpu_has(X86_FEATURE_AVX)) 1429 setup_force_cpu_bug(X86_BUG_GDS); 1430 1431 if (vulnerable_to_rfds(x86_arch_cap_msr)) 1432 setup_force_cpu_bug(X86_BUG_RFDS); 1433 1434 /* When virtualized, eIBRS could be hidden, assume vulnerable */ 1435 if (!(x86_arch_cap_msr & ARCH_CAP_BHI_NO) && 1436 !cpu_matches(cpu_vuln_whitelist, NO_BHI) && 1437 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) || 1438 boot_cpu_has(X86_FEATURE_HYPERVISOR))) 1439 setup_force_cpu_bug(X86_BUG_BHI); 1440 1441 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) 1442 return; 1443 1444 /* Rogue Data Cache Load? No! */ 1445 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO) 1446 return; 1447 1448 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1449 1450 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) 1451 return; 1452 1453 setup_force_cpu_bug(X86_BUG_L1TF); 1454 } 1455 1456 /* 1457 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1458 * unfortunately, that's not true in practice because of early VIA 1459 * chips and (more importantly) broken virtualizers that are not easy 1460 * to detect. In the latter case it doesn't even *fail* reliably, so 1461 * probing for it doesn't even work. Disable it completely on 32-bit 1462 * unless we can find a reliable way to detect all the broken cases. 1463 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1464 */ 1465 static void detect_nopl(void) 1466 { 1467 #ifdef CONFIG_X86_32 1468 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1469 #else 1470 setup_force_cpu_cap(X86_FEATURE_NOPL); 1471 #endif 1472 } 1473 1474 /* 1475 * We parse cpu parameters early because fpu__init_system() is executed 1476 * before parse_early_param(). 1477 */ 1478 static void __init cpu_parse_early_param(void) 1479 { 1480 char arg[128]; 1481 char *argptr = arg, *opt; 1482 int arglen, taint = 0; 1483 1484 #ifdef CONFIG_X86_32 1485 if (cmdline_find_option_bool(boot_command_line, "no387")) 1486 #ifdef CONFIG_MATH_EMULATION 1487 setup_clear_cpu_cap(X86_FEATURE_FPU); 1488 #else 1489 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); 1490 #endif 1491 1492 if (cmdline_find_option_bool(boot_command_line, "nofxsr")) 1493 setup_clear_cpu_cap(X86_FEATURE_FXSR); 1494 #endif 1495 1496 if (cmdline_find_option_bool(boot_command_line, "noxsave")) 1497 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 1498 1499 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) 1500 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); 1501 1502 if (cmdline_find_option_bool(boot_command_line, "noxsaves")) 1503 setup_clear_cpu_cap(X86_FEATURE_XSAVES); 1504 1505 if (cmdline_find_option_bool(boot_command_line, "nousershstk")) 1506 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); 1507 1508 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); 1509 if (arglen <= 0) 1510 return; 1511 1512 pr_info("Clearing CPUID bits:"); 1513 1514 while (argptr) { 1515 bool found __maybe_unused = false; 1516 unsigned int bit; 1517 1518 opt = strsep(&argptr, ","); 1519 1520 /* 1521 * Handle naked numbers first for feature flags which don't 1522 * have names. 1523 */ 1524 if (!kstrtouint(opt, 10, &bit)) { 1525 if (bit < NCAPINTS * 32) { 1526 1527 /* empty-string, i.e., ""-defined feature flags */ 1528 if (!x86_cap_flags[bit]) 1529 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); 1530 else 1531 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); 1532 1533 setup_clear_cpu_cap(bit); 1534 taint++; 1535 } 1536 /* 1537 * The assumption is that there are no feature names with only 1538 * numbers in the name thus go to the next argument. 1539 */ 1540 continue; 1541 } 1542 1543 for (bit = 0; bit < 32 * NCAPINTS; bit++) { 1544 if (!x86_cap_flag(bit)) 1545 continue; 1546 1547 if (strcmp(x86_cap_flag(bit), opt)) 1548 continue; 1549 1550 pr_cont(" %s", opt); 1551 setup_clear_cpu_cap(bit); 1552 taint++; 1553 found = true; 1554 break; 1555 } 1556 1557 if (!found) 1558 pr_cont(" (unknown: %s)", opt); 1559 } 1560 pr_cont("\n"); 1561 1562 if (taint) 1563 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1564 } 1565 1566 /* 1567 * Do minimum CPU detection early. 1568 * Fields really needed: vendor, cpuid_level, family, model, mask, 1569 * cache alignment. 1570 * The others are not touched to avoid unwanted side effects. 1571 * 1572 * WARNING: this function is only called on the boot CPU. Don't add code 1573 * here that is supposed to run on all CPUs. 1574 */ 1575 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1576 { 1577 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1578 c->extended_cpuid_level = 0; 1579 1580 if (!have_cpuid_p()) 1581 identify_cpu_without_cpuid(c); 1582 1583 /* cyrix could have cpuid enabled via c_identify()*/ 1584 if (have_cpuid_p()) { 1585 cpu_detect(c); 1586 get_cpu_vendor(c); 1587 get_cpu_cap(c); 1588 setup_force_cpu_cap(X86_FEATURE_CPUID); 1589 get_cpu_address_sizes(c); 1590 cpu_parse_early_param(); 1591 1592 cpu_init_topology(c); 1593 1594 if (this_cpu->c_early_init) 1595 this_cpu->c_early_init(c); 1596 1597 c->cpu_index = 0; 1598 filter_cpuid_features(c, false); 1599 1600 if (this_cpu->c_bsp_init) 1601 this_cpu->c_bsp_init(c); 1602 } else { 1603 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1604 get_cpu_address_sizes(c); 1605 cpu_init_topology(c); 1606 } 1607 1608 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1609 1610 cpu_set_bug_bits(c); 1611 1612 sld_setup(c); 1613 1614 #ifdef CONFIG_X86_32 1615 /* 1616 * Regardless of whether PCID is enumerated, the SDM says 1617 * that it can't be enabled in 32-bit mode. 1618 */ 1619 setup_clear_cpu_cap(X86_FEATURE_PCID); 1620 #endif 1621 1622 /* 1623 * Later in the boot process pgtable_l5_enabled() relies on 1624 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1625 * enabled by this point we need to clear the feature bit to avoid 1626 * false-positives at the later stage. 1627 * 1628 * pgtable_l5_enabled() can be false here for several reasons: 1629 * - 5-level paging is disabled compile-time; 1630 * - it's 32-bit kernel; 1631 * - machine doesn't support 5-level paging; 1632 * - user specified 'no5lvl' in kernel command line. 1633 */ 1634 if (!pgtable_l5_enabled()) 1635 setup_clear_cpu_cap(X86_FEATURE_LA57); 1636 1637 detect_nopl(); 1638 } 1639 1640 void __init early_cpu_init(void) 1641 { 1642 const struct cpu_dev *const *cdev; 1643 int count = 0; 1644 1645 #ifdef CONFIG_PROCESSOR_SELECT 1646 pr_info("KERNEL supported cpus:\n"); 1647 #endif 1648 1649 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1650 const struct cpu_dev *cpudev = *cdev; 1651 1652 if (count >= X86_VENDOR_NUM) 1653 break; 1654 cpu_devs[count] = cpudev; 1655 count++; 1656 1657 #ifdef CONFIG_PROCESSOR_SELECT 1658 { 1659 unsigned int j; 1660 1661 for (j = 0; j < 2; j++) { 1662 if (!cpudev->c_ident[j]) 1663 continue; 1664 pr_info(" %s %s\n", cpudev->c_vendor, 1665 cpudev->c_ident[j]); 1666 } 1667 } 1668 #endif 1669 } 1670 early_identify_cpu(&boot_cpu_data); 1671 } 1672 1673 static bool detect_null_seg_behavior(void) 1674 { 1675 /* 1676 * Empirically, writing zero to a segment selector on AMD does 1677 * not clear the base, whereas writing zero to a segment 1678 * selector on Intel does clear the base. Intel's behavior 1679 * allows slightly faster context switches in the common case 1680 * where GS is unused by the prev and next threads. 1681 * 1682 * Since neither vendor documents this anywhere that I can see, 1683 * detect it directly instead of hard-coding the choice by 1684 * vendor. 1685 * 1686 * I've designated AMD's behavior as the "bug" because it's 1687 * counterintuitive and less friendly. 1688 */ 1689 1690 unsigned long old_base, tmp; 1691 rdmsrl(MSR_FS_BASE, old_base); 1692 wrmsrl(MSR_FS_BASE, 1); 1693 loadsegment(fs, 0); 1694 rdmsrl(MSR_FS_BASE, tmp); 1695 wrmsrl(MSR_FS_BASE, old_base); 1696 return tmp == 0; 1697 } 1698 1699 void check_null_seg_clears_base(struct cpuinfo_x86 *c) 1700 { 1701 /* BUG_NULL_SEG is only relevant with 64bit userspace */ 1702 if (!IS_ENABLED(CONFIG_X86_64)) 1703 return; 1704 1705 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) 1706 return; 1707 1708 /* 1709 * CPUID bit above wasn't set. If this kernel is still running 1710 * as a HV guest, then the HV has decided not to advertize 1711 * that CPUID bit for whatever reason. For example, one 1712 * member of the migration pool might be vulnerable. Which 1713 * means, the bug is present: set the BUG flag and return. 1714 */ 1715 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { 1716 set_cpu_bug(c, X86_BUG_NULL_SEG); 1717 return; 1718 } 1719 1720 /* 1721 * Zen2 CPUs also have this behaviour, but no CPUID bit. 1722 * 0x18 is the respective family for Hygon. 1723 */ 1724 if ((c->x86 == 0x17 || c->x86 == 0x18) && 1725 detect_null_seg_behavior()) 1726 return; 1727 1728 /* All the remaining ones are affected */ 1729 set_cpu_bug(c, X86_BUG_NULL_SEG); 1730 } 1731 1732 static void generic_identify(struct cpuinfo_x86 *c) 1733 { 1734 c->extended_cpuid_level = 0; 1735 1736 if (!have_cpuid_p()) 1737 identify_cpu_without_cpuid(c); 1738 1739 /* cyrix could have cpuid enabled via c_identify()*/ 1740 if (!have_cpuid_p()) 1741 return; 1742 1743 cpu_detect(c); 1744 1745 get_cpu_vendor(c); 1746 1747 get_cpu_cap(c); 1748 1749 get_cpu_address_sizes(c); 1750 1751 get_model_name(c); /* Default name */ 1752 1753 /* 1754 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1755 * systems that run Linux at CPL > 0 may or may not have the 1756 * issue, but, even if they have the issue, there's absolutely 1757 * nothing we can do about it because we can't use the real IRET 1758 * instruction. 1759 * 1760 * NB: For the time being, only 32-bit kernels support 1761 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1762 * whether to apply espfix using paravirt hooks. If any 1763 * non-paravirt system ever shows up that does *not* have the 1764 * ESPFIX issue, we can change this. 1765 */ 1766 #ifdef CONFIG_X86_32 1767 set_cpu_bug(c, X86_BUG_ESPFIX); 1768 #endif 1769 } 1770 1771 /* 1772 * This does the hard work of actually picking apart the CPU stuff... 1773 */ 1774 static void identify_cpu(struct cpuinfo_x86 *c) 1775 { 1776 int i; 1777 1778 c->loops_per_jiffy = loops_per_jiffy; 1779 c->x86_cache_size = 0; 1780 c->x86_vendor = X86_VENDOR_UNKNOWN; 1781 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1782 c->x86_vendor_id[0] = '\0'; /* Unset */ 1783 c->x86_model_id[0] = '\0'; /* Unset */ 1784 #ifdef CONFIG_X86_64 1785 c->x86_clflush_size = 64; 1786 c->x86_phys_bits = 36; 1787 c->x86_virt_bits = 48; 1788 #else 1789 c->cpuid_level = -1; /* CPUID not detected */ 1790 c->x86_clflush_size = 32; 1791 c->x86_phys_bits = 32; 1792 c->x86_virt_bits = 32; 1793 #endif 1794 c->x86_cache_alignment = c->x86_clflush_size; 1795 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1796 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 1797 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); 1798 #endif 1799 1800 generic_identify(c); 1801 1802 cpu_parse_topology(c); 1803 1804 if (this_cpu->c_identify) 1805 this_cpu->c_identify(c); 1806 1807 /* Clear/Set all flags overridden by options, after probe */ 1808 apply_forced_caps(c); 1809 1810 /* 1811 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and 1812 * Hygon will clear it in ->c_init() below. 1813 */ 1814 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); 1815 1816 /* 1817 * Vendor-specific initialization. In this section we 1818 * canonicalize the feature flags, meaning if there are 1819 * features a certain CPU supports which CPUID doesn't 1820 * tell us, CPUID claiming incorrect flags, or other bugs, 1821 * we handle them here. 1822 * 1823 * At the end of this section, c->x86_capability better 1824 * indicate the features this CPU genuinely supports! 1825 */ 1826 if (this_cpu->c_init) 1827 this_cpu->c_init(c); 1828 1829 /* Disable the PN if appropriate */ 1830 squash_the_stupid_serial_number(c); 1831 1832 /* Set up SMEP/SMAP/UMIP */ 1833 setup_smep(c); 1834 setup_smap(c); 1835 setup_umip(c); 1836 1837 /* Enable FSGSBASE instructions if available. */ 1838 if (cpu_has(c, X86_FEATURE_FSGSBASE)) { 1839 cr4_set_bits(X86_CR4_FSGSBASE); 1840 elf_hwcap2 |= HWCAP2_FSGSBASE; 1841 } 1842 1843 /* 1844 * The vendor-specific functions might have changed features. 1845 * Now we do "generic changes." 1846 */ 1847 1848 /* Filter out anything that depends on CPUID levels we don't have */ 1849 filter_cpuid_features(c, true); 1850 1851 /* If the model name is still unset, do table lookup. */ 1852 if (!c->x86_model_id[0]) { 1853 const char *p; 1854 p = table_lookup_model(c); 1855 if (p) 1856 strcpy(c->x86_model_id, p); 1857 else 1858 /* Last resort... */ 1859 sprintf(c->x86_model_id, "%02x/%02x", 1860 c->x86, c->x86_model); 1861 } 1862 1863 x86_init_rdrand(c); 1864 setup_pku(c); 1865 setup_cet(c); 1866 1867 /* 1868 * Clear/Set all flags overridden by options, need do it 1869 * before following smp all cpus cap AND. 1870 */ 1871 apply_forced_caps(c); 1872 1873 /* 1874 * On SMP, boot_cpu_data holds the common feature set between 1875 * all CPUs; so make sure that we indicate which features are 1876 * common between the CPUs. The first time this routine gets 1877 * executed, c == &boot_cpu_data. 1878 */ 1879 if (c != &boot_cpu_data) { 1880 /* AND the already accumulated flags with these */ 1881 for (i = 0; i < NCAPINTS; i++) 1882 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1883 1884 /* OR, i.e. replicate the bug flags */ 1885 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1886 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1887 } 1888 1889 ppin_init(c); 1890 1891 /* Init Machine Check Exception if available. */ 1892 mcheck_cpu_init(c); 1893 1894 #ifdef CONFIG_NUMA 1895 numa_add_cpu(smp_processor_id()); 1896 #endif 1897 } 1898 1899 /* 1900 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1901 * on 32-bit kernels: 1902 */ 1903 #ifdef CONFIG_X86_32 1904 void enable_sep_cpu(void) 1905 { 1906 struct tss_struct *tss; 1907 int cpu; 1908 1909 if (!boot_cpu_has(X86_FEATURE_SEP)) 1910 return; 1911 1912 cpu = get_cpu(); 1913 tss = &per_cpu(cpu_tss_rw, cpu); 1914 1915 /* 1916 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1917 * see the big comment in struct x86_hw_tss's definition. 1918 */ 1919 1920 tss->x86_tss.ss1 = __KERNEL_CS; 1921 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1922 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1923 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1924 1925 put_cpu(); 1926 } 1927 #endif 1928 1929 static __init void identify_boot_cpu(void) 1930 { 1931 identify_cpu(&boot_cpu_data); 1932 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1933 pr_info("CET detected: Indirect Branch Tracking enabled\n"); 1934 #ifdef CONFIG_X86_32 1935 enable_sep_cpu(); 1936 #endif 1937 cpu_detect_tlb(&boot_cpu_data); 1938 setup_cr_pinning(); 1939 1940 tsx_init(); 1941 tdx_init(); 1942 lkgs_init(); 1943 } 1944 1945 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1946 { 1947 BUG_ON(c == &boot_cpu_data); 1948 identify_cpu(c); 1949 #ifdef CONFIG_X86_32 1950 enable_sep_cpu(); 1951 #endif 1952 x86_spec_ctrl_setup_ap(); 1953 update_srbds_msr(); 1954 if (boot_cpu_has_bug(X86_BUG_GDS)) 1955 update_gds_msr(); 1956 1957 tsx_ap_init(); 1958 } 1959 1960 void print_cpu_info(struct cpuinfo_x86 *c) 1961 { 1962 const char *vendor = NULL; 1963 1964 if (c->x86_vendor < X86_VENDOR_NUM) { 1965 vendor = this_cpu->c_vendor; 1966 } else { 1967 if (c->cpuid_level >= 0) 1968 vendor = c->x86_vendor_id; 1969 } 1970 1971 if (vendor && !strstr(c->x86_model_id, vendor)) 1972 pr_cont("%s ", vendor); 1973 1974 if (c->x86_model_id[0]) 1975 pr_cont("%s", c->x86_model_id); 1976 else 1977 pr_cont("%d86", c->x86); 1978 1979 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1980 1981 if (c->x86_stepping || c->cpuid_level >= 0) 1982 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1983 else 1984 pr_cont(")\n"); 1985 } 1986 1987 /* 1988 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy 1989 * function prevents it from becoming an environment variable for init. 1990 */ 1991 static __init int setup_clearcpuid(char *arg) 1992 { 1993 return 1; 1994 } 1995 __setup("clearcpuid=", setup_clearcpuid); 1996 1997 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = { 1998 .current_task = &init_task, 1999 .preempt_count = INIT_PREEMPT_COUNT, 2000 .top_of_stack = TOP_OF_INIT_STACK, 2001 }; 2002 EXPORT_PER_CPU_SYMBOL(pcpu_hot); 2003 EXPORT_PER_CPU_SYMBOL(const_pcpu_hot); 2004 2005 #ifdef CONFIG_X86_64 2006 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 2007 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 2008 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 2009 2010 static void wrmsrl_cstar(unsigned long val) 2011 { 2012 /* 2013 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR 2014 * is so far ignored by the CPU, but raises a #VE trap in a TDX 2015 * guest. Avoid the pointless write on all Intel CPUs. 2016 */ 2017 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2018 wrmsrl(MSR_CSTAR, val); 2019 } 2020 2021 static inline void idt_syscall_init(void) 2022 { 2023 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2024 2025 if (ia32_enabled()) { 2026 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2027 /* 2028 * This only works on Intel CPUs. 2029 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2030 * This does not cause SYSENTER to jump to the wrong location, because 2031 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2032 */ 2033 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2034 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2035 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2036 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2037 } else { 2038 wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore); 2039 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2040 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2041 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2042 } 2043 2044 /* 2045 * Flags to clear on syscall; clear as much as possible 2046 * to minimize user space-kernel interference. 2047 */ 2048 wrmsrl(MSR_SYSCALL_MASK, 2049 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2050 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2051 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| 2052 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| 2053 X86_EFLAGS_AC|X86_EFLAGS_ID); 2054 } 2055 2056 /* May not be marked __init: used by software suspend */ 2057 void syscall_init(void) 2058 { 2059 /* The default user and kernel segments */ 2060 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 2061 2062 /* 2063 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and 2064 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED 2065 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit 2066 * instruction to return to ring 3 (both sysexit and sysret cause 2067 * #UD when FRED is enabled). 2068 */ 2069 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2070 idt_syscall_init(); 2071 } 2072 2073 #else /* CONFIG_X86_64 */ 2074 2075 #ifdef CONFIG_STACKPROTECTOR 2076 DEFINE_PER_CPU(unsigned long, __stack_chk_guard); 2077 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); 2078 #endif 2079 2080 #endif /* CONFIG_X86_64 */ 2081 2082 /* 2083 * Clear all 6 debug registers: 2084 */ 2085 static void clear_all_debug_regs(void) 2086 { 2087 int i; 2088 2089 for (i = 0; i < 8; i++) { 2090 /* Ignore db4, db5 */ 2091 if ((i == 4) || (i == 5)) 2092 continue; 2093 2094 set_debugreg(0, i); 2095 } 2096 } 2097 2098 #ifdef CONFIG_KGDB 2099 /* 2100 * Restore debug regs if using kgdbwait and you have a kernel debugger 2101 * connection established. 2102 */ 2103 static void dbg_restore_debug_regs(void) 2104 { 2105 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 2106 arch_kgdb_ops.correct_hw_break(); 2107 } 2108 #else /* ! CONFIG_KGDB */ 2109 #define dbg_restore_debug_regs() 2110 #endif /* ! CONFIG_KGDB */ 2111 2112 static inline void setup_getcpu(int cpu) 2113 { 2114 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 2115 struct desc_struct d = { }; 2116 2117 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2118 wrmsr(MSR_TSC_AUX, cpudata, 0); 2119 2120 /* Store CPU and node number in limit. */ 2121 d.limit0 = cpudata; 2122 d.limit1 = cpudata >> 16; 2123 2124 d.type = 5; /* RO data, expand down, accessed */ 2125 d.dpl = 3; /* Visible to user code */ 2126 d.s = 1; /* Not a system segment */ 2127 d.p = 1; /* Present */ 2128 d.d = 1; /* 32-bit */ 2129 2130 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 2131 } 2132 2133 #ifdef CONFIG_X86_64 2134 static inline void tss_setup_ist(struct tss_struct *tss) 2135 { 2136 /* Set up the per-CPU TSS IST stacks */ 2137 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 2138 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 2139 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 2140 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 2141 /* Only mapped when SEV-ES is active */ 2142 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); 2143 } 2144 #else /* CONFIG_X86_64 */ 2145 static inline void tss_setup_ist(struct tss_struct *tss) { } 2146 #endif /* !CONFIG_X86_64 */ 2147 2148 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 2149 { 2150 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 2151 2152 #ifdef CONFIG_X86_IOPL_IOPERM 2153 tss->io_bitmap.prev_max = 0; 2154 tss->io_bitmap.prev_sequence = 0; 2155 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 2156 /* 2157 * Invalidate the extra array entry past the end of the all 2158 * permission bitmap as required by the hardware. 2159 */ 2160 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 2161 #endif 2162 } 2163 2164 /* 2165 * Setup everything needed to handle exceptions from the IDT, including the IST 2166 * exceptions which use paranoid_entry(). 2167 */ 2168 void cpu_init_exception_handling(void) 2169 { 2170 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 2171 int cpu = raw_smp_processor_id(); 2172 2173 /* paranoid_entry() gets the CPU number from the GDT */ 2174 setup_getcpu(cpu); 2175 2176 /* For IDT mode, IST vectors need to be set in TSS. */ 2177 if (!cpu_feature_enabled(X86_FEATURE_FRED)) 2178 tss_setup_ist(tss); 2179 tss_setup_io_bitmap(tss); 2180 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 2181 2182 load_TR_desc(); 2183 2184 /* GHCB needs to be setup to handle #VC. */ 2185 setup_ghcb(); 2186 2187 if (cpu_feature_enabled(X86_FEATURE_FRED)) 2188 cpu_init_fred_exceptions(); 2189 else 2190 load_current_idt(); 2191 } 2192 2193 /* 2194 * cpu_init() initializes state that is per-CPU. Some data is already 2195 * initialized (naturally) in the bootstrap process, such as the GDT. We 2196 * reload it nevertheless, this function acts as a 'CPU state barrier', 2197 * nothing should get across. 2198 */ 2199 void cpu_init(void) 2200 { 2201 struct task_struct *cur = current; 2202 int cpu = raw_smp_processor_id(); 2203 2204 #ifdef CONFIG_NUMA 2205 if (this_cpu_read(numa_node) == 0 && 2206 early_cpu_to_node(cpu) != NUMA_NO_NODE) 2207 set_numa_node(early_cpu_to_node(cpu)); 2208 #endif 2209 pr_debug("Initializing CPU#%d\n", cpu); 2210 2211 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 2212 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 2213 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 2214 2215 if (IS_ENABLED(CONFIG_X86_64)) { 2216 loadsegment(fs, 0); 2217 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2218 syscall_init(); 2219 2220 wrmsrl(MSR_FS_BASE, 0); 2221 wrmsrl(MSR_KERNEL_GS_BASE, 0); 2222 barrier(); 2223 2224 x2apic_setup(); 2225 } 2226 2227 mmgrab(&init_mm); 2228 cur->active_mm = &init_mm; 2229 BUG_ON(cur->mm); 2230 initialize_tlbstate_and_flush(); 2231 enter_lazy_tlb(&init_mm, cur); 2232 2233 /* 2234 * sp0 points to the entry trampoline stack regardless of what task 2235 * is running. 2236 */ 2237 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 2238 2239 load_mm_ldt(&init_mm); 2240 2241 clear_all_debug_regs(); 2242 dbg_restore_debug_regs(); 2243 2244 doublefault_init_cpu_tss(); 2245 2246 if (is_uv_system()) 2247 uv_cpu_init(); 2248 2249 load_fixmap_gdt(cpu); 2250 } 2251 2252 #ifdef CONFIG_MICROCODE_LATE_LOADING 2253 /** 2254 * store_cpu_caps() - Store a snapshot of CPU capabilities 2255 * @curr_info: Pointer where to store it 2256 * 2257 * Returns: None 2258 */ 2259 void store_cpu_caps(struct cpuinfo_x86 *curr_info) 2260 { 2261 /* Reload CPUID max function as it might've changed. */ 2262 curr_info->cpuid_level = cpuid_eax(0); 2263 2264 /* Copy all capability leafs and pick up the synthetic ones. */ 2265 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, 2266 sizeof(curr_info->x86_capability)); 2267 2268 /* Get the hardware CPUID leafs */ 2269 get_cpu_cap(curr_info); 2270 } 2271 2272 /** 2273 * microcode_check() - Check if any CPU capabilities changed after an update. 2274 * @prev_info: CPU capabilities stored before an update. 2275 * 2276 * The microcode loader calls this upon late microcode load to recheck features, 2277 * only when microcode has been updated. Caller holds and CPU hotplug lock. 2278 * 2279 * Return: None 2280 */ 2281 void microcode_check(struct cpuinfo_x86 *prev_info) 2282 { 2283 struct cpuinfo_x86 curr_info; 2284 2285 perf_check_microcode(); 2286 2287 amd_check_microcode(); 2288 2289 store_cpu_caps(&curr_info); 2290 2291 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, 2292 sizeof(prev_info->x86_capability))) 2293 return; 2294 2295 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 2296 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 2297 } 2298 #endif 2299 2300 /* 2301 * Invoked from core CPU hotplug code after hotplug operations 2302 */ 2303 void arch_smt_update(void) 2304 { 2305 /* Handle the speculative execution misfeatures */ 2306 cpu_bugs_smt_update(); 2307 /* Check whether IPI broadcasting can be enabled */ 2308 apic_smt_update(); 2309 } 2310 2311 void __init arch_cpu_finalize_init(void) 2312 { 2313 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info); 2314 2315 identify_boot_cpu(); 2316 2317 select_idle_routine(); 2318 2319 /* 2320 * identify_boot_cpu() initialized SMT support information, let the 2321 * core code know. 2322 */ 2323 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core); 2324 2325 if (!IS_ENABLED(CONFIG_SMP)) { 2326 pr_info("CPU: "); 2327 print_cpu_info(&boot_cpu_data); 2328 } 2329 2330 cpu_select_mitigations(); 2331 2332 arch_smt_update(); 2333 2334 if (IS_ENABLED(CONFIG_X86_32)) { 2335 /* 2336 * Check whether this is a real i386 which is not longer 2337 * supported and fixup the utsname. 2338 */ 2339 if (boot_cpu_data.x86 < 4) 2340 panic("Kernel requires i486+ for 'invlpg' and other features"); 2341 2342 init_utsname()->machine[1] = 2343 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); 2344 } 2345 2346 /* 2347 * Must be before alternatives because it might set or clear 2348 * feature bits. 2349 */ 2350 fpu__init_system(); 2351 fpu__init_cpu(); 2352 2353 /* 2354 * Ensure that access to the per CPU representation has the initial 2355 * boot CPU configuration. 2356 */ 2357 *c = boot_cpu_data; 2358 c->initialized = true; 2359 2360 alternative_instructions(); 2361 2362 if (IS_ENABLED(CONFIG_X86_64)) { 2363 /* 2364 * Make sure the first 2MB area is not mapped by huge pages 2365 * There are typically fixed size MTRRs in there and overlapping 2366 * MTRRs into large pages causes slow downs. 2367 * 2368 * Right now we don't do that with gbpages because there seems 2369 * very little benefit for that case. 2370 */ 2371 if (!direct_gbpages) 2372 set_memory_4k((unsigned long)__va(0), 1); 2373 } else { 2374 fpu__init_check_bugs(); 2375 } 2376 2377 /* 2378 * This needs to be called before any devices perform DMA 2379 * operations that might use the SWIOTLB bounce buffers. It will 2380 * mark the bounce buffers as decrypted so that their usage will 2381 * not cause "plain-text" data to be decrypted when accessed. It 2382 * must be called after late_time_init() so that Hyper-V x86/x64 2383 * hypercalls work when the SWIOTLB bounce buffers are decrypted. 2384 */ 2385 mem_encrypt_init(); 2386 } 2387