1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/init.h> 18 #include <linux/kprobes.h> 19 #include <linux/kgdb.h> 20 #include <linux/smp.h> 21 #include <linux/io.h> 22 #include <linux/syscore_ops.h> 23 24 #include <asm/stackprotector.h> 25 #include <asm/perf_event.h> 26 #include <asm/mmu_context.h> 27 #include <asm/archrandom.h> 28 #include <asm/hypervisor.h> 29 #include <asm/processor.h> 30 #include <asm/tlbflush.h> 31 #include <asm/debugreg.h> 32 #include <asm/sections.h> 33 #include <asm/vsyscall.h> 34 #include <linux/topology.h> 35 #include <linux/cpumask.h> 36 #include <asm/pgtable.h> 37 #include <linux/atomic.h> 38 #include <asm/proto.h> 39 #include <asm/setup.h> 40 #include <asm/apic.h> 41 #include <asm/desc.h> 42 #include <asm/fpu/internal.h> 43 #include <asm/mtrr.h> 44 #include <asm/hwcap2.h> 45 #include <linux/numa.h> 46 #include <asm/asm.h> 47 #include <asm/bugs.h> 48 #include <asm/cpu.h> 49 #include <asm/mce.h> 50 #include <asm/msr.h> 51 #include <asm/pat.h> 52 #include <asm/microcode.h> 53 #include <asm/microcode_intel.h> 54 #include <asm/intel-family.h> 55 #include <asm/cpu_device_id.h> 56 57 #ifdef CONFIG_X86_LOCAL_APIC 58 #include <asm/uv/uv.h> 59 #endif 60 61 #include "cpu.h" 62 63 u32 elf_hwcap2 __read_mostly; 64 65 /* all of these masks are initialized in setup_cpu_local_masks() */ 66 cpumask_var_t cpu_initialized_mask; 67 cpumask_var_t cpu_callout_mask; 68 cpumask_var_t cpu_callin_mask; 69 70 /* representing cpus for which sibling maps can be computed */ 71 cpumask_var_t cpu_sibling_setup_mask; 72 73 /* Number of siblings per CPU package */ 74 int smp_num_siblings = 1; 75 EXPORT_SYMBOL(smp_num_siblings); 76 77 /* Last level cache ID of each logical CPU */ 78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 79 80 /* correctly size the local cpu masks */ 81 void __init setup_cpu_local_masks(void) 82 { 83 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 84 alloc_bootmem_cpumask_var(&cpu_callin_mask); 85 alloc_bootmem_cpumask_var(&cpu_callout_mask); 86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 87 } 88 89 static void default_init(struct cpuinfo_x86 *c) 90 { 91 #ifdef CONFIG_X86_64 92 cpu_detect_cache_sizes(c); 93 #else 94 /* Not much we can do here... */ 95 /* Check if at least it has cpuid */ 96 if (c->cpuid_level == -1) { 97 /* No cpuid. It must be an ancient CPU */ 98 if (c->x86 == 4) 99 strcpy(c->x86_model_id, "486"); 100 else if (c->x86 == 3) 101 strcpy(c->x86_model_id, "386"); 102 } 103 #endif 104 } 105 106 static const struct cpu_dev default_cpu = { 107 .c_init = default_init, 108 .c_vendor = "Unknown", 109 .c_x86_vendor = X86_VENDOR_UNKNOWN, 110 }; 111 112 static const struct cpu_dev *this_cpu = &default_cpu; 113 114 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 115 #ifdef CONFIG_X86_64 116 /* 117 * We need valid kernel segments for data and code in long mode too 118 * IRET will check the segment types kkeil 2000/10/28 119 * Also sysret mandates a special GDT layout 120 * 121 * TLS descriptors are currently at a different place compared to i386. 122 * Hopefully nobody expects them at a fixed place (Wine?) 123 */ 124 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 125 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 126 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 127 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 128 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 130 #else 131 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 132 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 133 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 134 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 135 /* 136 * Segments used for calling PnP BIOS have byte granularity. 137 * They code segments and data segments have fixed 64k limits, 138 * the transfer segment sizes are set at run time. 139 */ 140 /* 32-bit code */ 141 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 142 /* 16-bit code */ 143 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 144 /* 16-bit data */ 145 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 146 /* 16-bit data */ 147 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 148 /* 16-bit data */ 149 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 150 /* 151 * The APM segments have byte granularity and their bases 152 * are set at run time. All have 64k limits. 153 */ 154 /* 32-bit code */ 155 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 156 /* 16-bit code */ 157 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 158 /* data */ 159 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 160 161 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 162 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 163 GDT_STACK_CANARY_INIT 164 #endif 165 } }; 166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 167 168 static int __init x86_mpx_setup(char *s) 169 { 170 /* require an exact match without trailing characters */ 171 if (strlen(s)) 172 return 0; 173 174 /* do not emit a message if the feature is not present */ 175 if (!boot_cpu_has(X86_FEATURE_MPX)) 176 return 1; 177 178 setup_clear_cpu_cap(X86_FEATURE_MPX); 179 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 180 return 1; 181 } 182 __setup("nompx", x86_mpx_setup); 183 184 #ifdef CONFIG_X86_64 185 static int __init x86_nopcid_setup(char *s) 186 { 187 /* nopcid doesn't accept parameters */ 188 if (s) 189 return -EINVAL; 190 191 /* do not emit a message if the feature is not present */ 192 if (!boot_cpu_has(X86_FEATURE_PCID)) 193 return 0; 194 195 setup_clear_cpu_cap(X86_FEATURE_PCID); 196 pr_info("nopcid: PCID feature disabled\n"); 197 return 0; 198 } 199 early_param("nopcid", x86_nopcid_setup); 200 #endif 201 202 static int __init x86_noinvpcid_setup(char *s) 203 { 204 /* noinvpcid doesn't accept parameters */ 205 if (s) 206 return -EINVAL; 207 208 /* do not emit a message if the feature is not present */ 209 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 210 return 0; 211 212 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 213 pr_info("noinvpcid: INVPCID feature disabled\n"); 214 return 0; 215 } 216 early_param("noinvpcid", x86_noinvpcid_setup); 217 218 #ifdef CONFIG_X86_32 219 static int cachesize_override = -1; 220 static int disable_x86_serial_nr = 1; 221 222 static int __init cachesize_setup(char *str) 223 { 224 get_option(&str, &cachesize_override); 225 return 1; 226 } 227 __setup("cachesize=", cachesize_setup); 228 229 static int __init x86_sep_setup(char *s) 230 { 231 setup_clear_cpu_cap(X86_FEATURE_SEP); 232 return 1; 233 } 234 __setup("nosep", x86_sep_setup); 235 236 /* Standard macro to see if a specific flag is changeable */ 237 static inline int flag_is_changeable_p(u32 flag) 238 { 239 u32 f1, f2; 240 241 /* 242 * Cyrix and IDT cpus allow disabling of CPUID 243 * so the code below may return different results 244 * when it is executed before and after enabling 245 * the CPUID. Add "volatile" to not allow gcc to 246 * optimize the subsequent calls to this function. 247 */ 248 asm volatile ("pushfl \n\t" 249 "pushfl \n\t" 250 "popl %0 \n\t" 251 "movl %0, %1 \n\t" 252 "xorl %2, %0 \n\t" 253 "pushl %0 \n\t" 254 "popfl \n\t" 255 "pushfl \n\t" 256 "popl %0 \n\t" 257 "popfl \n\t" 258 259 : "=&r" (f1), "=&r" (f2) 260 : "ir" (flag)); 261 262 return ((f1^f2) & flag) != 0; 263 } 264 265 /* Probe for the CPUID instruction */ 266 int have_cpuid_p(void) 267 { 268 return flag_is_changeable_p(X86_EFLAGS_ID); 269 } 270 271 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 272 { 273 unsigned long lo, hi; 274 275 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 276 return; 277 278 /* Disable processor serial number: */ 279 280 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 281 lo |= 0x200000; 282 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 283 284 pr_notice("CPU serial number disabled.\n"); 285 clear_cpu_cap(c, X86_FEATURE_PN); 286 287 /* Disabling the serial number may affect the cpuid level */ 288 c->cpuid_level = cpuid_eax(0); 289 } 290 291 static int __init x86_serial_nr_setup(char *s) 292 { 293 disable_x86_serial_nr = 0; 294 return 1; 295 } 296 __setup("serialnumber", x86_serial_nr_setup); 297 #else 298 static inline int flag_is_changeable_p(u32 flag) 299 { 300 return 1; 301 } 302 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 303 { 304 } 305 #endif 306 307 static __init int setup_disable_smep(char *arg) 308 { 309 setup_clear_cpu_cap(X86_FEATURE_SMEP); 310 /* Check for things that depend on SMEP being enabled: */ 311 check_mpx_erratum(&boot_cpu_data); 312 return 1; 313 } 314 __setup("nosmep", setup_disable_smep); 315 316 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 317 { 318 if (cpu_has(c, X86_FEATURE_SMEP)) 319 cr4_set_bits(X86_CR4_SMEP); 320 } 321 322 static __init int setup_disable_smap(char *arg) 323 { 324 setup_clear_cpu_cap(X86_FEATURE_SMAP); 325 return 1; 326 } 327 __setup("nosmap", setup_disable_smap); 328 329 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 330 { 331 unsigned long eflags = native_save_fl(); 332 333 /* This should have been cleared long ago */ 334 BUG_ON(eflags & X86_EFLAGS_AC); 335 336 if (cpu_has(c, X86_FEATURE_SMAP)) { 337 #ifdef CONFIG_X86_SMAP 338 cr4_set_bits(X86_CR4_SMAP); 339 #else 340 cr4_clear_bits(X86_CR4_SMAP); 341 #endif 342 } 343 } 344 345 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 346 { 347 /* Check the boot processor, plus build option for UMIP. */ 348 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 349 goto out; 350 351 /* Check the current processor's cpuid bits. */ 352 if (!cpu_has(c, X86_FEATURE_UMIP)) 353 goto out; 354 355 cr4_set_bits(X86_CR4_UMIP); 356 357 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 358 359 return; 360 361 out: 362 /* 363 * Make sure UMIP is disabled in case it was enabled in a 364 * previous boot (e.g., via kexec). 365 */ 366 cr4_clear_bits(X86_CR4_UMIP); 367 } 368 369 /* 370 * Protection Keys are not available in 32-bit mode. 371 */ 372 static bool pku_disabled; 373 374 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 375 { 376 struct pkru_state *pk; 377 378 /* check the boot processor, plus compile options for PKU: */ 379 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 380 return; 381 /* checks the actual processor's cpuid bits: */ 382 if (!cpu_has(c, X86_FEATURE_PKU)) 383 return; 384 if (pku_disabled) 385 return; 386 387 cr4_set_bits(X86_CR4_PKE); 388 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 389 if (pk) 390 pk->pkru = init_pkru_value; 391 /* 392 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 393 * cpuid bit to be set. We need to ensure that we 394 * update that bit in this CPU's "cpu_info". 395 */ 396 get_cpu_cap(c); 397 } 398 399 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 400 static __init int setup_disable_pku(char *arg) 401 { 402 /* 403 * Do not clear the X86_FEATURE_PKU bit. All of the 404 * runtime checks are against OSPKE so clearing the 405 * bit does nothing. 406 * 407 * This way, we will see "pku" in cpuinfo, but not 408 * "ospke", which is exactly what we want. It shows 409 * that the CPU has PKU, but the OS has not enabled it. 410 * This happens to be exactly how a system would look 411 * if we disabled the config option. 412 */ 413 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 414 pku_disabled = true; 415 return 1; 416 } 417 __setup("nopku", setup_disable_pku); 418 #endif /* CONFIG_X86_64 */ 419 420 /* 421 * Some CPU features depend on higher CPUID levels, which may not always 422 * be available due to CPUID level capping or broken virtualization 423 * software. Add those features to this table to auto-disable them. 424 */ 425 struct cpuid_dependent_feature { 426 u32 feature; 427 u32 level; 428 }; 429 430 static const struct cpuid_dependent_feature 431 cpuid_dependent_features[] = { 432 { X86_FEATURE_MWAIT, 0x00000005 }, 433 { X86_FEATURE_DCA, 0x00000009 }, 434 { X86_FEATURE_XSAVE, 0x0000000d }, 435 { 0, 0 } 436 }; 437 438 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 439 { 440 const struct cpuid_dependent_feature *df; 441 442 for (df = cpuid_dependent_features; df->feature; df++) { 443 444 if (!cpu_has(c, df->feature)) 445 continue; 446 /* 447 * Note: cpuid_level is set to -1 if unavailable, but 448 * extended_extended_level is set to 0 if unavailable 449 * and the legitimate extended levels are all negative 450 * when signed; hence the weird messing around with 451 * signs here... 452 */ 453 if (!((s32)df->level < 0 ? 454 (u32)df->level > (u32)c->extended_cpuid_level : 455 (s32)df->level > (s32)c->cpuid_level)) 456 continue; 457 458 clear_cpu_cap(c, df->feature); 459 if (!warn) 460 continue; 461 462 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 463 x86_cap_flag(df->feature), df->level); 464 } 465 } 466 467 /* 468 * Naming convention should be: <Name> [(<Codename>)] 469 * This table only is used unless init_<vendor>() below doesn't set it; 470 * in particular, if CPUID levels 0x80000002..4 are supported, this 471 * isn't used 472 */ 473 474 /* Look up CPU names by table lookup. */ 475 static const char *table_lookup_model(struct cpuinfo_x86 *c) 476 { 477 #ifdef CONFIG_X86_32 478 const struct legacy_cpu_model_info *info; 479 480 if (c->x86_model >= 16) 481 return NULL; /* Range check */ 482 483 if (!this_cpu) 484 return NULL; 485 486 info = this_cpu->legacy_models; 487 488 while (info->family) { 489 if (info->family == c->x86) 490 return info->model_names[c->x86_model]; 491 info++; 492 } 493 #endif 494 return NULL; /* Not found */ 495 } 496 497 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 498 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 499 500 void load_percpu_segment(int cpu) 501 { 502 #ifdef CONFIG_X86_32 503 loadsegment(fs, __KERNEL_PERCPU); 504 #else 505 __loadsegment_simple(gs, 0); 506 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 507 #endif 508 load_stack_canary_segment(); 509 } 510 511 #ifdef CONFIG_X86_32 512 /* The 32-bit entry code needs to find cpu_entry_area. */ 513 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 514 #endif 515 516 /* Load the original GDT from the per-cpu structure */ 517 void load_direct_gdt(int cpu) 518 { 519 struct desc_ptr gdt_descr; 520 521 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 522 gdt_descr.size = GDT_SIZE - 1; 523 load_gdt(&gdt_descr); 524 } 525 EXPORT_SYMBOL_GPL(load_direct_gdt); 526 527 /* Load a fixmap remapping of the per-cpu GDT */ 528 void load_fixmap_gdt(int cpu) 529 { 530 struct desc_ptr gdt_descr; 531 532 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 533 gdt_descr.size = GDT_SIZE - 1; 534 load_gdt(&gdt_descr); 535 } 536 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 537 538 /* 539 * Current gdt points %fs at the "master" per-cpu area: after this, 540 * it's on the real one. 541 */ 542 void switch_to_new_gdt(int cpu) 543 { 544 /* Load the original GDT */ 545 load_direct_gdt(cpu); 546 /* Reload the per-cpu base */ 547 load_percpu_segment(cpu); 548 } 549 550 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 551 552 static void get_model_name(struct cpuinfo_x86 *c) 553 { 554 unsigned int *v; 555 char *p, *q, *s; 556 557 if (c->extended_cpuid_level < 0x80000004) 558 return; 559 560 v = (unsigned int *)c->x86_model_id; 561 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 562 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 563 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 564 c->x86_model_id[48] = 0; 565 566 /* Trim whitespace */ 567 p = q = s = &c->x86_model_id[0]; 568 569 while (*p == ' ') 570 p++; 571 572 while (*p) { 573 /* Note the last non-whitespace index */ 574 if (!isspace(*p)) 575 s = q; 576 577 *q++ = *p++; 578 } 579 580 *(s + 1) = '\0'; 581 } 582 583 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 584 { 585 unsigned int eax, ebx, ecx, edx; 586 587 c->x86_max_cores = 1; 588 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 589 return; 590 591 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 592 if (eax & 0x1f) 593 c->x86_max_cores = (eax >> 26) + 1; 594 } 595 596 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 597 { 598 unsigned int n, dummy, ebx, ecx, edx, l2size; 599 600 n = c->extended_cpuid_level; 601 602 if (n >= 0x80000005) { 603 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 604 c->x86_cache_size = (ecx>>24) + (edx>>24); 605 #ifdef CONFIG_X86_64 606 /* On K8 L1 TLB is inclusive, so don't count it */ 607 c->x86_tlbsize = 0; 608 #endif 609 } 610 611 if (n < 0x80000006) /* Some chips just has a large L1. */ 612 return; 613 614 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 615 l2size = ecx >> 16; 616 617 #ifdef CONFIG_X86_64 618 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 619 #else 620 /* do processor-specific cache resizing */ 621 if (this_cpu->legacy_cache_size) 622 l2size = this_cpu->legacy_cache_size(c, l2size); 623 624 /* Allow user to override all this if necessary. */ 625 if (cachesize_override != -1) 626 l2size = cachesize_override; 627 628 if (l2size == 0) 629 return; /* Again, no L2 cache is possible */ 630 #endif 631 632 c->x86_cache_size = l2size; 633 } 634 635 u16 __read_mostly tlb_lli_4k[NR_INFO]; 636 u16 __read_mostly tlb_lli_2m[NR_INFO]; 637 u16 __read_mostly tlb_lli_4m[NR_INFO]; 638 u16 __read_mostly tlb_lld_4k[NR_INFO]; 639 u16 __read_mostly tlb_lld_2m[NR_INFO]; 640 u16 __read_mostly tlb_lld_4m[NR_INFO]; 641 u16 __read_mostly tlb_lld_1g[NR_INFO]; 642 643 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 644 { 645 if (this_cpu->c_detect_tlb) 646 this_cpu->c_detect_tlb(c); 647 648 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 649 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 650 tlb_lli_4m[ENTRIES]); 651 652 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 653 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 654 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 655 } 656 657 int detect_ht_early(struct cpuinfo_x86 *c) 658 { 659 #ifdef CONFIG_SMP 660 u32 eax, ebx, ecx, edx; 661 662 if (!cpu_has(c, X86_FEATURE_HT)) 663 return -1; 664 665 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 666 return -1; 667 668 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 669 return -1; 670 671 cpuid(1, &eax, &ebx, &ecx, &edx); 672 673 smp_num_siblings = (ebx & 0xff0000) >> 16; 674 if (smp_num_siblings == 1) 675 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 676 #endif 677 return 0; 678 } 679 680 void detect_ht(struct cpuinfo_x86 *c) 681 { 682 #ifdef CONFIG_SMP 683 int index_msb, core_bits; 684 685 if (detect_ht_early(c) < 0) 686 return; 687 688 index_msb = get_count_order(smp_num_siblings); 689 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 690 691 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 692 693 index_msb = get_count_order(smp_num_siblings); 694 695 core_bits = get_count_order(c->x86_max_cores); 696 697 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 698 ((1 << core_bits) - 1); 699 #endif 700 } 701 702 static void get_cpu_vendor(struct cpuinfo_x86 *c) 703 { 704 char *v = c->x86_vendor_id; 705 int i; 706 707 for (i = 0; i < X86_VENDOR_NUM; i++) { 708 if (!cpu_devs[i]) 709 break; 710 711 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 712 (cpu_devs[i]->c_ident[1] && 713 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 714 715 this_cpu = cpu_devs[i]; 716 c->x86_vendor = this_cpu->c_x86_vendor; 717 return; 718 } 719 } 720 721 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 722 "CPU: Your system may be unstable.\n", v); 723 724 c->x86_vendor = X86_VENDOR_UNKNOWN; 725 this_cpu = &default_cpu; 726 } 727 728 void cpu_detect(struct cpuinfo_x86 *c) 729 { 730 /* Get vendor name */ 731 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 732 (unsigned int *)&c->x86_vendor_id[0], 733 (unsigned int *)&c->x86_vendor_id[8], 734 (unsigned int *)&c->x86_vendor_id[4]); 735 736 c->x86 = 4; 737 /* Intel-defined flags: level 0x00000001 */ 738 if (c->cpuid_level >= 0x00000001) { 739 u32 junk, tfms, cap0, misc; 740 741 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 742 c->x86 = x86_family(tfms); 743 c->x86_model = x86_model(tfms); 744 c->x86_stepping = x86_stepping(tfms); 745 746 if (cap0 & (1<<19)) { 747 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 748 c->x86_cache_alignment = c->x86_clflush_size; 749 } 750 } 751 } 752 753 static void apply_forced_caps(struct cpuinfo_x86 *c) 754 { 755 int i; 756 757 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 758 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 759 c->x86_capability[i] |= cpu_caps_set[i]; 760 } 761 } 762 763 static void init_speculation_control(struct cpuinfo_x86 *c) 764 { 765 /* 766 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 767 * and they also have a different bit for STIBP support. Also, 768 * a hypervisor might have set the individual AMD bits even on 769 * Intel CPUs, for finer-grained selection of what's available. 770 */ 771 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 772 set_cpu_cap(c, X86_FEATURE_IBRS); 773 set_cpu_cap(c, X86_FEATURE_IBPB); 774 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 775 } 776 777 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 778 set_cpu_cap(c, X86_FEATURE_STIBP); 779 780 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 781 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 782 set_cpu_cap(c, X86_FEATURE_SSBD); 783 784 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 785 set_cpu_cap(c, X86_FEATURE_IBRS); 786 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 787 } 788 789 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 790 set_cpu_cap(c, X86_FEATURE_IBPB); 791 792 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 793 set_cpu_cap(c, X86_FEATURE_STIBP); 794 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 795 } 796 797 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 798 set_cpu_cap(c, X86_FEATURE_SSBD); 799 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 800 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 801 } 802 } 803 804 static void init_cqm(struct cpuinfo_x86 *c) 805 { 806 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 807 c->x86_cache_max_rmid = -1; 808 c->x86_cache_occ_scale = -1; 809 return; 810 } 811 812 /* will be overridden if occupancy monitoring exists */ 813 c->x86_cache_max_rmid = cpuid_ebx(0xf); 814 815 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 816 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 817 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 818 u32 eax, ebx, ecx, edx; 819 820 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 821 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 822 823 c->x86_cache_max_rmid = ecx; 824 c->x86_cache_occ_scale = ebx; 825 } 826 } 827 828 void get_cpu_cap(struct cpuinfo_x86 *c) 829 { 830 u32 eax, ebx, ecx, edx; 831 832 /* Intel-defined flags: level 0x00000001 */ 833 if (c->cpuid_level >= 0x00000001) { 834 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 835 836 c->x86_capability[CPUID_1_ECX] = ecx; 837 c->x86_capability[CPUID_1_EDX] = edx; 838 } 839 840 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 841 if (c->cpuid_level >= 0x00000006) 842 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 843 844 /* Additional Intel-defined flags: level 0x00000007 */ 845 if (c->cpuid_level >= 0x00000007) { 846 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 847 c->x86_capability[CPUID_7_0_EBX] = ebx; 848 c->x86_capability[CPUID_7_ECX] = ecx; 849 c->x86_capability[CPUID_7_EDX] = edx; 850 851 /* Check valid sub-leaf index before accessing it */ 852 if (eax >= 1) { 853 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 854 c->x86_capability[CPUID_7_1_EAX] = eax; 855 } 856 } 857 858 /* Extended state features: level 0x0000000d */ 859 if (c->cpuid_level >= 0x0000000d) { 860 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 861 862 c->x86_capability[CPUID_D_1_EAX] = eax; 863 } 864 865 /* AMD-defined flags: level 0x80000001 */ 866 eax = cpuid_eax(0x80000000); 867 c->extended_cpuid_level = eax; 868 869 if ((eax & 0xffff0000) == 0x80000000) { 870 if (eax >= 0x80000001) { 871 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 872 873 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 874 c->x86_capability[CPUID_8000_0001_EDX] = edx; 875 } 876 } 877 878 if (c->extended_cpuid_level >= 0x80000007) { 879 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 880 881 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 882 c->x86_power = edx; 883 } 884 885 if (c->extended_cpuid_level >= 0x80000008) { 886 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 887 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 888 } 889 890 if (c->extended_cpuid_level >= 0x8000000a) 891 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 892 893 init_scattered_cpuid_features(c); 894 init_speculation_control(c); 895 init_cqm(c); 896 897 /* 898 * Clear/Set all flags overridden by options, after probe. 899 * This needs to happen each time we re-probe, which may happen 900 * several times during CPU initialization. 901 */ 902 apply_forced_caps(c); 903 } 904 905 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 906 { 907 u32 eax, ebx, ecx, edx; 908 909 if (c->extended_cpuid_level >= 0x80000008) { 910 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 911 912 c->x86_virt_bits = (eax >> 8) & 0xff; 913 c->x86_phys_bits = eax & 0xff; 914 } 915 #ifdef CONFIG_X86_32 916 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 917 c->x86_phys_bits = 36; 918 #endif 919 c->x86_cache_bits = c->x86_phys_bits; 920 } 921 922 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 923 { 924 #ifdef CONFIG_X86_32 925 int i; 926 927 /* 928 * First of all, decide if this is a 486 or higher 929 * It's a 486 if we can modify the AC flag 930 */ 931 if (flag_is_changeable_p(X86_EFLAGS_AC)) 932 c->x86 = 4; 933 else 934 c->x86 = 3; 935 936 for (i = 0; i < X86_VENDOR_NUM; i++) 937 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 938 c->x86_vendor_id[0] = 0; 939 cpu_devs[i]->c_identify(c); 940 if (c->x86_vendor_id[0]) { 941 get_cpu_vendor(c); 942 break; 943 } 944 } 945 #endif 946 } 947 948 #define NO_SPECULATION BIT(0) 949 #define NO_MELTDOWN BIT(1) 950 #define NO_SSB BIT(2) 951 #define NO_L1TF BIT(3) 952 #define NO_MDS BIT(4) 953 #define MSBDS_ONLY BIT(5) 954 955 #define VULNWL(_vendor, _family, _model, _whitelist) \ 956 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } 957 958 #define VULNWL_INTEL(model, whitelist) \ 959 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 960 961 #define VULNWL_AMD(family, whitelist) \ 962 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 963 964 #define VULNWL_HYGON(family, whitelist) \ 965 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 966 967 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 968 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 969 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 970 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 971 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 972 973 /* Intel Family 6 */ 974 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION), 975 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION), 976 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION), 977 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), 978 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), 979 980 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), 981 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY), 982 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY), 983 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), 984 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY), 985 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY), 986 987 VULNWL_INTEL(CORE_YONAH, NO_SSB), 988 989 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY), 990 991 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF), 992 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF), 993 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF), 994 995 /* AMD Family 0xf - 0x12 */ 996 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 997 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 998 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 999 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), 1000 1001 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1002 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), 1003 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), 1004 {} 1005 }; 1006 1007 static bool __init cpu_matches(unsigned long which) 1008 { 1009 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 1010 1011 return m && !!(m->driver_data & which); 1012 } 1013 1014 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1015 { 1016 u64 ia32_cap = 0; 1017 1018 if (cpu_matches(NO_SPECULATION)) 1019 return; 1020 1021 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1022 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1023 1024 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) 1025 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1026 1027 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 1028 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1029 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1030 1031 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1032 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1033 1034 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1035 setup_force_cpu_bug(X86_BUG_MDS); 1036 if (cpu_matches(MSBDS_ONLY)) 1037 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1038 } 1039 1040 if (cpu_matches(NO_MELTDOWN)) 1041 return; 1042 1043 /* Rogue Data Cache Load? No! */ 1044 if (ia32_cap & ARCH_CAP_RDCL_NO) 1045 return; 1046 1047 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1048 1049 if (cpu_matches(NO_L1TF)) 1050 return; 1051 1052 setup_force_cpu_bug(X86_BUG_L1TF); 1053 } 1054 1055 /* 1056 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1057 * unfortunately, that's not true in practice because of early VIA 1058 * chips and (more importantly) broken virtualizers that are not easy 1059 * to detect. In the latter case it doesn't even *fail* reliably, so 1060 * probing for it doesn't even work. Disable it completely on 32-bit 1061 * unless we can find a reliable way to detect all the broken cases. 1062 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1063 */ 1064 static void detect_nopl(void) 1065 { 1066 #ifdef CONFIG_X86_32 1067 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1068 #else 1069 setup_force_cpu_cap(X86_FEATURE_NOPL); 1070 #endif 1071 } 1072 1073 /* 1074 * Do minimum CPU detection early. 1075 * Fields really needed: vendor, cpuid_level, family, model, mask, 1076 * cache alignment. 1077 * The others are not touched to avoid unwanted side effects. 1078 * 1079 * WARNING: this function is only called on the boot CPU. Don't add code 1080 * here that is supposed to run on all CPUs. 1081 */ 1082 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1083 { 1084 #ifdef CONFIG_X86_64 1085 c->x86_clflush_size = 64; 1086 c->x86_phys_bits = 36; 1087 c->x86_virt_bits = 48; 1088 #else 1089 c->x86_clflush_size = 32; 1090 c->x86_phys_bits = 32; 1091 c->x86_virt_bits = 32; 1092 #endif 1093 c->x86_cache_alignment = c->x86_clflush_size; 1094 1095 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1096 c->extended_cpuid_level = 0; 1097 1098 if (!have_cpuid_p()) 1099 identify_cpu_without_cpuid(c); 1100 1101 /* cyrix could have cpuid enabled via c_identify()*/ 1102 if (have_cpuid_p()) { 1103 cpu_detect(c); 1104 get_cpu_vendor(c); 1105 get_cpu_cap(c); 1106 get_cpu_address_sizes(c); 1107 setup_force_cpu_cap(X86_FEATURE_CPUID); 1108 1109 if (this_cpu->c_early_init) 1110 this_cpu->c_early_init(c); 1111 1112 c->cpu_index = 0; 1113 filter_cpuid_features(c, false); 1114 1115 if (this_cpu->c_bsp_init) 1116 this_cpu->c_bsp_init(c); 1117 } else { 1118 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1119 } 1120 1121 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1122 1123 cpu_set_bug_bits(c); 1124 1125 fpu__init_system(c); 1126 1127 #ifdef CONFIG_X86_32 1128 /* 1129 * Regardless of whether PCID is enumerated, the SDM says 1130 * that it can't be enabled in 32-bit mode. 1131 */ 1132 setup_clear_cpu_cap(X86_FEATURE_PCID); 1133 #endif 1134 1135 /* 1136 * Later in the boot process pgtable_l5_enabled() relies on 1137 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1138 * enabled by this point we need to clear the feature bit to avoid 1139 * false-positives at the later stage. 1140 * 1141 * pgtable_l5_enabled() can be false here for several reasons: 1142 * - 5-level paging is disabled compile-time; 1143 * - it's 32-bit kernel; 1144 * - machine doesn't support 5-level paging; 1145 * - user specified 'no5lvl' in kernel command line. 1146 */ 1147 if (!pgtable_l5_enabled()) 1148 setup_clear_cpu_cap(X86_FEATURE_LA57); 1149 1150 detect_nopl(); 1151 } 1152 1153 void __init early_cpu_init(void) 1154 { 1155 const struct cpu_dev *const *cdev; 1156 int count = 0; 1157 1158 #ifdef CONFIG_PROCESSOR_SELECT 1159 pr_info("KERNEL supported cpus:\n"); 1160 #endif 1161 1162 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1163 const struct cpu_dev *cpudev = *cdev; 1164 1165 if (count >= X86_VENDOR_NUM) 1166 break; 1167 cpu_devs[count] = cpudev; 1168 count++; 1169 1170 #ifdef CONFIG_PROCESSOR_SELECT 1171 { 1172 unsigned int j; 1173 1174 for (j = 0; j < 2; j++) { 1175 if (!cpudev->c_ident[j]) 1176 continue; 1177 pr_info(" %s %s\n", cpudev->c_vendor, 1178 cpudev->c_ident[j]); 1179 } 1180 } 1181 #endif 1182 } 1183 early_identify_cpu(&boot_cpu_data); 1184 } 1185 1186 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1187 { 1188 #ifdef CONFIG_X86_64 1189 /* 1190 * Empirically, writing zero to a segment selector on AMD does 1191 * not clear the base, whereas writing zero to a segment 1192 * selector on Intel does clear the base. Intel's behavior 1193 * allows slightly faster context switches in the common case 1194 * where GS is unused by the prev and next threads. 1195 * 1196 * Since neither vendor documents this anywhere that I can see, 1197 * detect it directly instead of hardcoding the choice by 1198 * vendor. 1199 * 1200 * I've designated AMD's behavior as the "bug" because it's 1201 * counterintuitive and less friendly. 1202 */ 1203 1204 unsigned long old_base, tmp; 1205 rdmsrl(MSR_FS_BASE, old_base); 1206 wrmsrl(MSR_FS_BASE, 1); 1207 loadsegment(fs, 0); 1208 rdmsrl(MSR_FS_BASE, tmp); 1209 if (tmp != 0) 1210 set_cpu_bug(c, X86_BUG_NULL_SEG); 1211 wrmsrl(MSR_FS_BASE, old_base); 1212 #endif 1213 } 1214 1215 static void generic_identify(struct cpuinfo_x86 *c) 1216 { 1217 c->extended_cpuid_level = 0; 1218 1219 if (!have_cpuid_p()) 1220 identify_cpu_without_cpuid(c); 1221 1222 /* cyrix could have cpuid enabled via c_identify()*/ 1223 if (!have_cpuid_p()) 1224 return; 1225 1226 cpu_detect(c); 1227 1228 get_cpu_vendor(c); 1229 1230 get_cpu_cap(c); 1231 1232 get_cpu_address_sizes(c); 1233 1234 if (c->cpuid_level >= 0x00000001) { 1235 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1236 #ifdef CONFIG_X86_32 1237 # ifdef CONFIG_SMP 1238 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1239 # else 1240 c->apicid = c->initial_apicid; 1241 # endif 1242 #endif 1243 c->phys_proc_id = c->initial_apicid; 1244 } 1245 1246 get_model_name(c); /* Default name */ 1247 1248 detect_null_seg_behavior(c); 1249 1250 /* 1251 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1252 * systems that run Linux at CPL > 0 may or may not have the 1253 * issue, but, even if they have the issue, there's absolutely 1254 * nothing we can do about it because we can't use the real IRET 1255 * instruction. 1256 * 1257 * NB: For the time being, only 32-bit kernels support 1258 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1259 * whether to apply espfix using paravirt hooks. If any 1260 * non-paravirt system ever shows up that does *not* have the 1261 * ESPFIX issue, we can change this. 1262 */ 1263 #ifdef CONFIG_X86_32 1264 # ifdef CONFIG_PARAVIRT_XXL 1265 do { 1266 extern void native_iret(void); 1267 if (pv_ops.cpu.iret == native_iret) 1268 set_cpu_bug(c, X86_BUG_ESPFIX); 1269 } while (0); 1270 # else 1271 set_cpu_bug(c, X86_BUG_ESPFIX); 1272 # endif 1273 #endif 1274 } 1275 1276 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1277 { 1278 /* 1279 * The heavy lifting of max_rmid and cache_occ_scale are handled 1280 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1281 * in case CQM bits really aren't there in this CPU. 1282 */ 1283 if (c != &boot_cpu_data) { 1284 boot_cpu_data.x86_cache_max_rmid = 1285 min(boot_cpu_data.x86_cache_max_rmid, 1286 c->x86_cache_max_rmid); 1287 } 1288 } 1289 1290 /* 1291 * Validate that ACPI/mptables have the same information about the 1292 * effective APIC id and update the package map. 1293 */ 1294 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1295 { 1296 #ifdef CONFIG_SMP 1297 unsigned int apicid, cpu = smp_processor_id(); 1298 1299 apicid = apic->cpu_present_to_apicid(cpu); 1300 1301 if (apicid != c->apicid) { 1302 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1303 cpu, apicid, c->initial_apicid); 1304 } 1305 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1306 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1307 #else 1308 c->logical_proc_id = 0; 1309 #endif 1310 } 1311 1312 /* 1313 * This does the hard work of actually picking apart the CPU stuff... 1314 */ 1315 static void identify_cpu(struct cpuinfo_x86 *c) 1316 { 1317 int i; 1318 1319 c->loops_per_jiffy = loops_per_jiffy; 1320 c->x86_cache_size = 0; 1321 c->x86_vendor = X86_VENDOR_UNKNOWN; 1322 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1323 c->x86_vendor_id[0] = '\0'; /* Unset */ 1324 c->x86_model_id[0] = '\0'; /* Unset */ 1325 c->x86_max_cores = 1; 1326 c->x86_coreid_bits = 0; 1327 c->cu_id = 0xff; 1328 #ifdef CONFIG_X86_64 1329 c->x86_clflush_size = 64; 1330 c->x86_phys_bits = 36; 1331 c->x86_virt_bits = 48; 1332 #else 1333 c->cpuid_level = -1; /* CPUID not detected */ 1334 c->x86_clflush_size = 32; 1335 c->x86_phys_bits = 32; 1336 c->x86_virt_bits = 32; 1337 #endif 1338 c->x86_cache_alignment = c->x86_clflush_size; 1339 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1340 1341 generic_identify(c); 1342 1343 if (this_cpu->c_identify) 1344 this_cpu->c_identify(c); 1345 1346 /* Clear/Set all flags overridden by options, after probe */ 1347 apply_forced_caps(c); 1348 1349 #ifdef CONFIG_X86_64 1350 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1351 #endif 1352 1353 /* 1354 * Vendor-specific initialization. In this section we 1355 * canonicalize the feature flags, meaning if there are 1356 * features a certain CPU supports which CPUID doesn't 1357 * tell us, CPUID claiming incorrect flags, or other bugs, 1358 * we handle them here. 1359 * 1360 * At the end of this section, c->x86_capability better 1361 * indicate the features this CPU genuinely supports! 1362 */ 1363 if (this_cpu->c_init) 1364 this_cpu->c_init(c); 1365 1366 /* Disable the PN if appropriate */ 1367 squash_the_stupid_serial_number(c); 1368 1369 /* Set up SMEP/SMAP/UMIP */ 1370 setup_smep(c); 1371 setup_smap(c); 1372 setup_umip(c); 1373 1374 /* 1375 * The vendor-specific functions might have changed features. 1376 * Now we do "generic changes." 1377 */ 1378 1379 /* Filter out anything that depends on CPUID levels we don't have */ 1380 filter_cpuid_features(c, true); 1381 1382 /* If the model name is still unset, do table lookup. */ 1383 if (!c->x86_model_id[0]) { 1384 const char *p; 1385 p = table_lookup_model(c); 1386 if (p) 1387 strcpy(c->x86_model_id, p); 1388 else 1389 /* Last resort... */ 1390 sprintf(c->x86_model_id, "%02x/%02x", 1391 c->x86, c->x86_model); 1392 } 1393 1394 #ifdef CONFIG_X86_64 1395 detect_ht(c); 1396 #endif 1397 1398 x86_init_rdrand(c); 1399 x86_init_cache_qos(c); 1400 setup_pku(c); 1401 1402 /* 1403 * Clear/Set all flags overridden by options, need do it 1404 * before following smp all cpus cap AND. 1405 */ 1406 apply_forced_caps(c); 1407 1408 /* 1409 * On SMP, boot_cpu_data holds the common feature set between 1410 * all CPUs; so make sure that we indicate which features are 1411 * common between the CPUs. The first time this routine gets 1412 * executed, c == &boot_cpu_data. 1413 */ 1414 if (c != &boot_cpu_data) { 1415 /* AND the already accumulated flags with these */ 1416 for (i = 0; i < NCAPINTS; i++) 1417 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1418 1419 /* OR, i.e. replicate the bug flags */ 1420 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1421 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1422 } 1423 1424 /* Init Machine Check Exception if available. */ 1425 mcheck_cpu_init(c); 1426 1427 select_idle_routine(c); 1428 1429 #ifdef CONFIG_NUMA 1430 numa_add_cpu(smp_processor_id()); 1431 #endif 1432 } 1433 1434 /* 1435 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1436 * on 32-bit kernels: 1437 */ 1438 #ifdef CONFIG_X86_32 1439 void enable_sep_cpu(void) 1440 { 1441 struct tss_struct *tss; 1442 int cpu; 1443 1444 if (!boot_cpu_has(X86_FEATURE_SEP)) 1445 return; 1446 1447 cpu = get_cpu(); 1448 tss = &per_cpu(cpu_tss_rw, cpu); 1449 1450 /* 1451 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1452 * see the big comment in struct x86_hw_tss's definition. 1453 */ 1454 1455 tss->x86_tss.ss1 = __KERNEL_CS; 1456 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1457 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1458 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1459 1460 put_cpu(); 1461 } 1462 #endif 1463 1464 void __init identify_boot_cpu(void) 1465 { 1466 identify_cpu(&boot_cpu_data); 1467 #ifdef CONFIG_X86_32 1468 sysenter_setup(); 1469 enable_sep_cpu(); 1470 #endif 1471 cpu_detect_tlb(&boot_cpu_data); 1472 } 1473 1474 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1475 { 1476 BUG_ON(c == &boot_cpu_data); 1477 identify_cpu(c); 1478 #ifdef CONFIG_X86_32 1479 enable_sep_cpu(); 1480 #endif 1481 mtrr_ap_init(); 1482 validate_apic_and_package_id(c); 1483 x86_spec_ctrl_setup_ap(); 1484 } 1485 1486 static __init int setup_noclflush(char *arg) 1487 { 1488 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1489 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1490 return 1; 1491 } 1492 __setup("noclflush", setup_noclflush); 1493 1494 void print_cpu_info(struct cpuinfo_x86 *c) 1495 { 1496 const char *vendor = NULL; 1497 1498 if (c->x86_vendor < X86_VENDOR_NUM) { 1499 vendor = this_cpu->c_vendor; 1500 } else { 1501 if (c->cpuid_level >= 0) 1502 vendor = c->x86_vendor_id; 1503 } 1504 1505 if (vendor && !strstr(c->x86_model_id, vendor)) 1506 pr_cont("%s ", vendor); 1507 1508 if (c->x86_model_id[0]) 1509 pr_cont("%s", c->x86_model_id); 1510 else 1511 pr_cont("%d86", c->x86); 1512 1513 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1514 1515 if (c->x86_stepping || c->cpuid_level >= 0) 1516 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1517 else 1518 pr_cont(")\n"); 1519 } 1520 1521 /* 1522 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1523 * But we need to keep a dummy __setup around otherwise it would 1524 * show up as an environment variable for init. 1525 */ 1526 static __init int setup_clearcpuid(char *arg) 1527 { 1528 return 1; 1529 } 1530 __setup("clearcpuid=", setup_clearcpuid); 1531 1532 #ifdef CONFIG_X86_64 1533 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1534 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1535 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1536 1537 /* 1538 * The following percpu variables are hot. Align current_task to 1539 * cacheline size such that they fall in the same cacheline. 1540 */ 1541 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1542 &init_task; 1543 EXPORT_PER_CPU_SYMBOL(current_task); 1544 1545 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1546 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1547 1548 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1549 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1550 1551 /* May not be marked __init: used by software suspend */ 1552 void syscall_init(void) 1553 { 1554 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1555 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1556 1557 #ifdef CONFIG_IA32_EMULATION 1558 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1559 /* 1560 * This only works on Intel CPUs. 1561 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1562 * This does not cause SYSENTER to jump to the wrong location, because 1563 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1564 */ 1565 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1566 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1567 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1568 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1569 #else 1570 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1571 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1572 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1573 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1574 #endif 1575 1576 /* Flags to clear on syscall */ 1577 wrmsrl(MSR_SYSCALL_MASK, 1578 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1579 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1580 } 1581 1582 DEFINE_PER_CPU(int, debug_stack_usage); 1583 DEFINE_PER_CPU(u32, debug_idt_ctr); 1584 1585 void debug_stack_set_zero(void) 1586 { 1587 this_cpu_inc(debug_idt_ctr); 1588 load_current_idt(); 1589 } 1590 NOKPROBE_SYMBOL(debug_stack_set_zero); 1591 1592 void debug_stack_reset(void) 1593 { 1594 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1595 return; 1596 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1597 load_current_idt(); 1598 } 1599 NOKPROBE_SYMBOL(debug_stack_reset); 1600 1601 #else /* CONFIG_X86_64 */ 1602 1603 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1604 EXPORT_PER_CPU_SYMBOL(current_task); 1605 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1606 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1607 1608 /* 1609 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1610 * the top of the kernel stack. Use an extra percpu variable to track the 1611 * top of the kernel stack directly. 1612 */ 1613 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1614 (unsigned long)&init_thread_union + THREAD_SIZE; 1615 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1616 1617 #ifdef CONFIG_STACKPROTECTOR 1618 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1619 #endif 1620 1621 #endif /* CONFIG_X86_64 */ 1622 1623 /* 1624 * Clear all 6 debug registers: 1625 */ 1626 static void clear_all_debug_regs(void) 1627 { 1628 int i; 1629 1630 for (i = 0; i < 8; i++) { 1631 /* Ignore db4, db5 */ 1632 if ((i == 4) || (i == 5)) 1633 continue; 1634 1635 set_debugreg(0, i); 1636 } 1637 } 1638 1639 #ifdef CONFIG_KGDB 1640 /* 1641 * Restore debug regs if using kgdbwait and you have a kernel debugger 1642 * connection established. 1643 */ 1644 static void dbg_restore_debug_regs(void) 1645 { 1646 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1647 arch_kgdb_ops.correct_hw_break(); 1648 } 1649 #else /* ! CONFIG_KGDB */ 1650 #define dbg_restore_debug_regs() 1651 #endif /* ! CONFIG_KGDB */ 1652 1653 static void wait_for_master_cpu(int cpu) 1654 { 1655 #ifdef CONFIG_SMP 1656 /* 1657 * wait for ACK from master CPU before continuing 1658 * with AP initialization 1659 */ 1660 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1661 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1662 cpu_relax(); 1663 #endif 1664 } 1665 1666 #ifdef CONFIG_X86_64 1667 static void setup_getcpu(int cpu) 1668 { 1669 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1670 struct desc_struct d = { }; 1671 1672 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1673 write_rdtscp_aux(cpudata); 1674 1675 /* Store CPU and node number in limit. */ 1676 d.limit0 = cpudata; 1677 d.limit1 = cpudata >> 16; 1678 1679 d.type = 5; /* RO data, expand down, accessed */ 1680 d.dpl = 3; /* Visible to user code */ 1681 d.s = 1; /* Not a system segment */ 1682 d.p = 1; /* Present */ 1683 d.d = 1; /* 32-bit */ 1684 1685 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1686 } 1687 #endif 1688 1689 /* 1690 * cpu_init() initializes state that is per-CPU. Some data is already 1691 * initialized (naturally) in the bootstrap process, such as the GDT 1692 * and IDT. We reload them nevertheless, this function acts as a 1693 * 'CPU state barrier', nothing should get across. 1694 */ 1695 #ifdef CONFIG_X86_64 1696 1697 void cpu_init(void) 1698 { 1699 int cpu = raw_smp_processor_id(); 1700 struct task_struct *me; 1701 struct tss_struct *t; 1702 int i; 1703 1704 wait_for_master_cpu(cpu); 1705 1706 /* 1707 * Initialize the CR4 shadow before doing anything that could 1708 * try to read it. 1709 */ 1710 cr4_init_shadow(); 1711 1712 if (cpu) 1713 load_ucode_ap(); 1714 1715 t = &per_cpu(cpu_tss_rw, cpu); 1716 1717 #ifdef CONFIG_NUMA 1718 if (this_cpu_read(numa_node) == 0 && 1719 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1720 set_numa_node(early_cpu_to_node(cpu)); 1721 #endif 1722 setup_getcpu(cpu); 1723 1724 me = current; 1725 1726 pr_debug("Initializing CPU#%d\n", cpu); 1727 1728 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1729 1730 /* 1731 * Initialize the per-CPU GDT with the boot GDT, 1732 * and set up the GDT descriptor: 1733 */ 1734 1735 switch_to_new_gdt(cpu); 1736 loadsegment(fs, 0); 1737 1738 load_current_idt(); 1739 1740 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1741 syscall_init(); 1742 1743 wrmsrl(MSR_FS_BASE, 0); 1744 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1745 barrier(); 1746 1747 x86_configure_nx(); 1748 x2apic_setup(); 1749 1750 /* 1751 * set up and load the per-CPU TSS 1752 */ 1753 if (!t->x86_tss.ist[0]) { 1754 t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1755 t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1756 t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1757 t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1758 } 1759 1760 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1761 1762 /* 1763 * <= is required because the CPU will access up to 1764 * 8 bits beyond the end of the IO permission bitmap. 1765 */ 1766 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1767 t->io_bitmap[i] = ~0UL; 1768 1769 mmgrab(&init_mm); 1770 me->active_mm = &init_mm; 1771 BUG_ON(me->mm); 1772 initialize_tlbstate_and_flush(); 1773 enter_lazy_tlb(&init_mm, me); 1774 1775 /* 1776 * Initialize the TSS. sp0 points to the entry trampoline stack 1777 * regardless of what task is running. 1778 */ 1779 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1780 load_TR_desc(); 1781 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1782 1783 load_mm_ldt(&init_mm); 1784 1785 clear_all_debug_regs(); 1786 dbg_restore_debug_regs(); 1787 1788 fpu__init_cpu(); 1789 1790 if (is_uv_system()) 1791 uv_cpu_init(); 1792 1793 load_fixmap_gdt(cpu); 1794 } 1795 1796 #else 1797 1798 void cpu_init(void) 1799 { 1800 int cpu = smp_processor_id(); 1801 struct task_struct *curr = current; 1802 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1803 1804 wait_for_master_cpu(cpu); 1805 1806 /* 1807 * Initialize the CR4 shadow before doing anything that could 1808 * try to read it. 1809 */ 1810 cr4_init_shadow(); 1811 1812 show_ucode_info_early(); 1813 1814 pr_info("Initializing CPU#%d\n", cpu); 1815 1816 if (cpu_feature_enabled(X86_FEATURE_VME) || 1817 boot_cpu_has(X86_FEATURE_TSC) || 1818 boot_cpu_has(X86_FEATURE_DE)) 1819 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1820 1821 load_current_idt(); 1822 switch_to_new_gdt(cpu); 1823 1824 /* 1825 * Set up and load the per-CPU TSS and LDT 1826 */ 1827 mmgrab(&init_mm); 1828 curr->active_mm = &init_mm; 1829 BUG_ON(curr->mm); 1830 initialize_tlbstate_and_flush(); 1831 enter_lazy_tlb(&init_mm, curr); 1832 1833 /* 1834 * Initialize the TSS. sp0 points to the entry trampoline stack 1835 * regardless of what task is running. 1836 */ 1837 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1838 load_TR_desc(); 1839 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1840 1841 load_mm_ldt(&init_mm); 1842 1843 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1844 1845 #ifdef CONFIG_DOUBLEFAULT 1846 /* Set up doublefault TSS pointer in the GDT */ 1847 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1848 #endif 1849 1850 clear_all_debug_regs(); 1851 dbg_restore_debug_regs(); 1852 1853 fpu__init_cpu(); 1854 1855 load_fixmap_gdt(cpu); 1856 } 1857 #endif 1858 1859 /* 1860 * The microcode loader calls this upon late microcode load to recheck features, 1861 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1862 * hotplug lock. 1863 */ 1864 void microcode_check(void) 1865 { 1866 struct cpuinfo_x86 info; 1867 1868 perf_check_microcode(); 1869 1870 /* Reload CPUID max function as it might've changed. */ 1871 info.cpuid_level = cpuid_eax(0); 1872 1873 /* 1874 * Copy all capability leafs to pick up the synthetic ones so that 1875 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1876 * get overwritten in get_cpu_cap(). 1877 */ 1878 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1879 1880 get_cpu_cap(&info); 1881 1882 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1883 return; 1884 1885 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1886 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1887 } 1888