1 // SPDX-License-Identifier: GPL-2.0-only 2 /* cpu_feature_enabled() cannot be used this early */ 3 #define USE_EARLY_PGTABLE_L5 4 5 #include <linux/memblock.h> 6 #include <linux/linkage.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/percpu.h> 11 #include <linux/string.h> 12 #include <linux/ctype.h> 13 #include <linux/delay.h> 14 #include <linux/sched/mm.h> 15 #include <linux/sched/clock.h> 16 #include <linux/sched/task.h> 17 #include <linux/init.h> 18 #include <linux/kprobes.h> 19 #include <linux/kgdb.h> 20 #include <linux/smp.h> 21 #include <linux/io.h> 22 #include <linux/syscore_ops.h> 23 24 #include <asm/stackprotector.h> 25 #include <asm/perf_event.h> 26 #include <asm/mmu_context.h> 27 #include <asm/archrandom.h> 28 #include <asm/hypervisor.h> 29 #include <asm/processor.h> 30 #include <asm/tlbflush.h> 31 #include <asm/debugreg.h> 32 #include <asm/sections.h> 33 #include <asm/vsyscall.h> 34 #include <linux/topology.h> 35 #include <linux/cpumask.h> 36 #include <asm/pgtable.h> 37 #include <linux/atomic.h> 38 #include <asm/proto.h> 39 #include <asm/setup.h> 40 #include <asm/apic.h> 41 #include <asm/desc.h> 42 #include <asm/fpu/internal.h> 43 #include <asm/mtrr.h> 44 #include <asm/hwcap2.h> 45 #include <linux/numa.h> 46 #include <asm/asm.h> 47 #include <asm/bugs.h> 48 #include <asm/cpu.h> 49 #include <asm/mce.h> 50 #include <asm/msr.h> 51 #include <asm/pat.h> 52 #include <asm/microcode.h> 53 #include <asm/microcode_intel.h> 54 #include <asm/intel-family.h> 55 #include <asm/cpu_device_id.h> 56 #include <asm/uv/uv.h> 57 58 #include "cpu.h" 59 60 u32 elf_hwcap2 __read_mostly; 61 62 /* all of these masks are initialized in setup_cpu_local_masks() */ 63 cpumask_var_t cpu_initialized_mask; 64 cpumask_var_t cpu_callout_mask; 65 cpumask_var_t cpu_callin_mask; 66 67 /* representing cpus for which sibling maps can be computed */ 68 cpumask_var_t cpu_sibling_setup_mask; 69 70 /* Number of siblings per CPU package */ 71 int smp_num_siblings = 1; 72 EXPORT_SYMBOL(smp_num_siblings); 73 74 /* Last level cache ID of each logical CPU */ 75 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 76 77 /* correctly size the local cpu masks */ 78 void __init setup_cpu_local_masks(void) 79 { 80 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 81 alloc_bootmem_cpumask_var(&cpu_callin_mask); 82 alloc_bootmem_cpumask_var(&cpu_callout_mask); 83 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 84 } 85 86 static void default_init(struct cpuinfo_x86 *c) 87 { 88 #ifdef CONFIG_X86_64 89 cpu_detect_cache_sizes(c); 90 #else 91 /* Not much we can do here... */ 92 /* Check if at least it has cpuid */ 93 if (c->cpuid_level == -1) { 94 /* No cpuid. It must be an ancient CPU */ 95 if (c->x86 == 4) 96 strcpy(c->x86_model_id, "486"); 97 else if (c->x86 == 3) 98 strcpy(c->x86_model_id, "386"); 99 } 100 #endif 101 } 102 103 static const struct cpu_dev default_cpu = { 104 .c_init = default_init, 105 .c_vendor = "Unknown", 106 .c_x86_vendor = X86_VENDOR_UNKNOWN, 107 }; 108 109 static const struct cpu_dev *this_cpu = &default_cpu; 110 111 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 112 #ifdef CONFIG_X86_64 113 /* 114 * We need valid kernel segments for data and code in long mode too 115 * IRET will check the segment types kkeil 2000/10/28 116 * Also sysret mandates a special GDT layout 117 * 118 * TLS descriptors are currently at a different place compared to i386. 119 * Hopefully nobody expects them at a fixed place (Wine?) 120 */ 121 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 122 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 123 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 124 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 125 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 126 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 127 #else 128 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 129 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 130 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 131 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 132 /* 133 * Segments used for calling PnP BIOS have byte granularity. 134 * They code segments and data segments have fixed 64k limits, 135 * the transfer segment sizes are set at run time. 136 */ 137 /* 32-bit code */ 138 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 139 /* 16-bit code */ 140 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 141 /* 16-bit data */ 142 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 143 /* 16-bit data */ 144 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 145 /* 16-bit data */ 146 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 147 /* 148 * The APM segments have byte granularity and their bases 149 * are set at run time. All have 64k limits. 150 */ 151 /* 32-bit code */ 152 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 153 /* 16-bit code */ 154 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 155 /* data */ 156 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 157 158 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 159 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 160 GDT_STACK_CANARY_INIT 161 #endif 162 } }; 163 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 164 165 static int __init x86_mpx_setup(char *s) 166 { 167 /* require an exact match without trailing characters */ 168 if (strlen(s)) 169 return 0; 170 171 /* do not emit a message if the feature is not present */ 172 if (!boot_cpu_has(X86_FEATURE_MPX)) 173 return 1; 174 175 setup_clear_cpu_cap(X86_FEATURE_MPX); 176 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 177 return 1; 178 } 179 __setup("nompx", x86_mpx_setup); 180 181 #ifdef CONFIG_X86_64 182 static int __init x86_nopcid_setup(char *s) 183 { 184 /* nopcid doesn't accept parameters */ 185 if (s) 186 return -EINVAL; 187 188 /* do not emit a message if the feature is not present */ 189 if (!boot_cpu_has(X86_FEATURE_PCID)) 190 return 0; 191 192 setup_clear_cpu_cap(X86_FEATURE_PCID); 193 pr_info("nopcid: PCID feature disabled\n"); 194 return 0; 195 } 196 early_param("nopcid", x86_nopcid_setup); 197 #endif 198 199 static int __init x86_noinvpcid_setup(char *s) 200 { 201 /* noinvpcid doesn't accept parameters */ 202 if (s) 203 return -EINVAL; 204 205 /* do not emit a message if the feature is not present */ 206 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 207 return 0; 208 209 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 210 pr_info("noinvpcid: INVPCID feature disabled\n"); 211 return 0; 212 } 213 early_param("noinvpcid", x86_noinvpcid_setup); 214 215 #ifdef CONFIG_X86_32 216 static int cachesize_override = -1; 217 static int disable_x86_serial_nr = 1; 218 219 static int __init cachesize_setup(char *str) 220 { 221 get_option(&str, &cachesize_override); 222 return 1; 223 } 224 __setup("cachesize=", cachesize_setup); 225 226 static int __init x86_sep_setup(char *s) 227 { 228 setup_clear_cpu_cap(X86_FEATURE_SEP); 229 return 1; 230 } 231 __setup("nosep", x86_sep_setup); 232 233 /* Standard macro to see if a specific flag is changeable */ 234 static inline int flag_is_changeable_p(u32 flag) 235 { 236 u32 f1, f2; 237 238 /* 239 * Cyrix and IDT cpus allow disabling of CPUID 240 * so the code below may return different results 241 * when it is executed before and after enabling 242 * the CPUID. Add "volatile" to not allow gcc to 243 * optimize the subsequent calls to this function. 244 */ 245 asm volatile ("pushfl \n\t" 246 "pushfl \n\t" 247 "popl %0 \n\t" 248 "movl %0, %1 \n\t" 249 "xorl %2, %0 \n\t" 250 "pushl %0 \n\t" 251 "popfl \n\t" 252 "pushfl \n\t" 253 "popl %0 \n\t" 254 "popfl \n\t" 255 256 : "=&r" (f1), "=&r" (f2) 257 : "ir" (flag)); 258 259 return ((f1^f2) & flag) != 0; 260 } 261 262 /* Probe for the CPUID instruction */ 263 int have_cpuid_p(void) 264 { 265 return flag_is_changeable_p(X86_EFLAGS_ID); 266 } 267 268 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 269 { 270 unsigned long lo, hi; 271 272 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 273 return; 274 275 /* Disable processor serial number: */ 276 277 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 278 lo |= 0x200000; 279 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 280 281 pr_notice("CPU serial number disabled.\n"); 282 clear_cpu_cap(c, X86_FEATURE_PN); 283 284 /* Disabling the serial number may affect the cpuid level */ 285 c->cpuid_level = cpuid_eax(0); 286 } 287 288 static int __init x86_serial_nr_setup(char *s) 289 { 290 disable_x86_serial_nr = 0; 291 return 1; 292 } 293 __setup("serialnumber", x86_serial_nr_setup); 294 #else 295 static inline int flag_is_changeable_p(u32 flag) 296 { 297 return 1; 298 } 299 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 300 { 301 } 302 #endif 303 304 static __init int setup_disable_smep(char *arg) 305 { 306 setup_clear_cpu_cap(X86_FEATURE_SMEP); 307 /* Check for things that depend on SMEP being enabled: */ 308 check_mpx_erratum(&boot_cpu_data); 309 return 1; 310 } 311 __setup("nosmep", setup_disable_smep); 312 313 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 314 { 315 if (cpu_has(c, X86_FEATURE_SMEP)) 316 cr4_set_bits(X86_CR4_SMEP); 317 } 318 319 static __init int setup_disable_smap(char *arg) 320 { 321 setup_clear_cpu_cap(X86_FEATURE_SMAP); 322 return 1; 323 } 324 __setup("nosmap", setup_disable_smap); 325 326 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 327 { 328 unsigned long eflags = native_save_fl(); 329 330 /* This should have been cleared long ago */ 331 BUG_ON(eflags & X86_EFLAGS_AC); 332 333 if (cpu_has(c, X86_FEATURE_SMAP)) { 334 #ifdef CONFIG_X86_SMAP 335 cr4_set_bits(X86_CR4_SMAP); 336 #else 337 cr4_clear_bits(X86_CR4_SMAP); 338 #endif 339 } 340 } 341 342 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 343 { 344 /* Check the boot processor, plus build option for UMIP. */ 345 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 346 goto out; 347 348 /* Check the current processor's cpuid bits. */ 349 if (!cpu_has(c, X86_FEATURE_UMIP)) 350 goto out; 351 352 cr4_set_bits(X86_CR4_UMIP); 353 354 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); 355 356 return; 357 358 out: 359 /* 360 * Make sure UMIP is disabled in case it was enabled in a 361 * previous boot (e.g., via kexec). 362 */ 363 cr4_clear_bits(X86_CR4_UMIP); 364 } 365 366 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); 367 static unsigned long cr4_pinned_bits __ro_after_init; 368 369 void native_write_cr0(unsigned long val) 370 { 371 unsigned long bits_missing = 0; 372 373 set_register: 374 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); 375 376 if (static_branch_likely(&cr_pinning)) { 377 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { 378 bits_missing = X86_CR0_WP; 379 val |= bits_missing; 380 goto set_register; 381 } 382 /* Warn after we've set the missing bits. */ 383 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); 384 } 385 } 386 EXPORT_SYMBOL(native_write_cr0); 387 388 void native_write_cr4(unsigned long val) 389 { 390 unsigned long bits_missing = 0; 391 392 set_register: 393 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits)); 394 395 if (static_branch_likely(&cr_pinning)) { 396 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) { 397 bits_missing = ~val & cr4_pinned_bits; 398 val |= bits_missing; 399 goto set_register; 400 } 401 /* Warn after we've set the missing bits. */ 402 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n", 403 bits_missing); 404 } 405 } 406 EXPORT_SYMBOL(native_write_cr4); 407 408 void cr4_init(void) 409 { 410 unsigned long cr4 = __read_cr4(); 411 412 if (boot_cpu_has(X86_FEATURE_PCID)) 413 cr4 |= X86_CR4_PCIDE; 414 if (static_branch_likely(&cr_pinning)) 415 cr4 |= cr4_pinned_bits; 416 417 __write_cr4(cr4); 418 419 /* Initialize cr4 shadow for this CPU. */ 420 this_cpu_write(cpu_tlbstate.cr4, cr4); 421 } 422 423 /* 424 * Once CPU feature detection is finished (and boot params have been 425 * parsed), record any of the sensitive CR bits that are set, and 426 * enable CR pinning. 427 */ 428 static void __init setup_cr_pinning(void) 429 { 430 unsigned long mask; 431 432 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); 433 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; 434 static_key_enable(&cr_pinning.key); 435 } 436 437 /* 438 * Protection Keys are not available in 32-bit mode. 439 */ 440 static bool pku_disabled; 441 442 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 443 { 444 struct pkru_state *pk; 445 446 /* check the boot processor, plus compile options for PKU: */ 447 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 448 return; 449 /* checks the actual processor's cpuid bits: */ 450 if (!cpu_has(c, X86_FEATURE_PKU)) 451 return; 452 if (pku_disabled) 453 return; 454 455 cr4_set_bits(X86_CR4_PKE); 456 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU); 457 if (pk) 458 pk->pkru = init_pkru_value; 459 /* 460 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 461 * cpuid bit to be set. We need to ensure that we 462 * update that bit in this CPU's "cpu_info". 463 */ 464 get_cpu_cap(c); 465 } 466 467 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 468 static __init int setup_disable_pku(char *arg) 469 { 470 /* 471 * Do not clear the X86_FEATURE_PKU bit. All of the 472 * runtime checks are against OSPKE so clearing the 473 * bit does nothing. 474 * 475 * This way, we will see "pku" in cpuinfo, but not 476 * "ospke", which is exactly what we want. It shows 477 * that the CPU has PKU, but the OS has not enabled it. 478 * This happens to be exactly how a system would look 479 * if we disabled the config option. 480 */ 481 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 482 pku_disabled = true; 483 return 1; 484 } 485 __setup("nopku", setup_disable_pku); 486 #endif /* CONFIG_X86_64 */ 487 488 /* 489 * Some CPU features depend on higher CPUID levels, which may not always 490 * be available due to CPUID level capping or broken virtualization 491 * software. Add those features to this table to auto-disable them. 492 */ 493 struct cpuid_dependent_feature { 494 u32 feature; 495 u32 level; 496 }; 497 498 static const struct cpuid_dependent_feature 499 cpuid_dependent_features[] = { 500 { X86_FEATURE_MWAIT, 0x00000005 }, 501 { X86_FEATURE_DCA, 0x00000009 }, 502 { X86_FEATURE_XSAVE, 0x0000000d }, 503 { 0, 0 } 504 }; 505 506 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 507 { 508 const struct cpuid_dependent_feature *df; 509 510 for (df = cpuid_dependent_features; df->feature; df++) { 511 512 if (!cpu_has(c, df->feature)) 513 continue; 514 /* 515 * Note: cpuid_level is set to -1 if unavailable, but 516 * extended_extended_level is set to 0 if unavailable 517 * and the legitimate extended levels are all negative 518 * when signed; hence the weird messing around with 519 * signs here... 520 */ 521 if (!((s32)df->level < 0 ? 522 (u32)df->level > (u32)c->extended_cpuid_level : 523 (s32)df->level > (s32)c->cpuid_level)) 524 continue; 525 526 clear_cpu_cap(c, df->feature); 527 if (!warn) 528 continue; 529 530 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 531 x86_cap_flag(df->feature), df->level); 532 } 533 } 534 535 /* 536 * Naming convention should be: <Name> [(<Codename>)] 537 * This table only is used unless init_<vendor>() below doesn't set it; 538 * in particular, if CPUID levels 0x80000002..4 are supported, this 539 * isn't used 540 */ 541 542 /* Look up CPU names by table lookup. */ 543 static const char *table_lookup_model(struct cpuinfo_x86 *c) 544 { 545 #ifdef CONFIG_X86_32 546 const struct legacy_cpu_model_info *info; 547 548 if (c->x86_model >= 16) 549 return NULL; /* Range check */ 550 551 if (!this_cpu) 552 return NULL; 553 554 info = this_cpu->legacy_models; 555 556 while (info->family) { 557 if (info->family == c->x86) 558 return info->model_names[c->x86_model]; 559 info++; 560 } 561 #endif 562 return NULL; /* Not found */ 563 } 564 565 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ 566 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 567 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); 568 569 void load_percpu_segment(int cpu) 570 { 571 #ifdef CONFIG_X86_32 572 loadsegment(fs, __KERNEL_PERCPU); 573 #else 574 __loadsegment_simple(gs, 0); 575 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 576 #endif 577 load_stack_canary_segment(); 578 } 579 580 #ifdef CONFIG_X86_32 581 /* The 32-bit entry code needs to find cpu_entry_area. */ 582 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 583 #endif 584 585 /* Load the original GDT from the per-cpu structure */ 586 void load_direct_gdt(int cpu) 587 { 588 struct desc_ptr gdt_descr; 589 590 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 591 gdt_descr.size = GDT_SIZE - 1; 592 load_gdt(&gdt_descr); 593 } 594 EXPORT_SYMBOL_GPL(load_direct_gdt); 595 596 /* Load a fixmap remapping of the per-cpu GDT */ 597 void load_fixmap_gdt(int cpu) 598 { 599 struct desc_ptr gdt_descr; 600 601 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 602 gdt_descr.size = GDT_SIZE - 1; 603 load_gdt(&gdt_descr); 604 } 605 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 606 607 /* 608 * Current gdt points %fs at the "master" per-cpu area: after this, 609 * it's on the real one. 610 */ 611 void switch_to_new_gdt(int cpu) 612 { 613 /* Load the original GDT */ 614 load_direct_gdt(cpu); 615 /* Reload the per-cpu base */ 616 load_percpu_segment(cpu); 617 } 618 619 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 620 621 static void get_model_name(struct cpuinfo_x86 *c) 622 { 623 unsigned int *v; 624 char *p, *q, *s; 625 626 if (c->extended_cpuid_level < 0x80000004) 627 return; 628 629 v = (unsigned int *)c->x86_model_id; 630 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 631 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 632 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 633 c->x86_model_id[48] = 0; 634 635 /* Trim whitespace */ 636 p = q = s = &c->x86_model_id[0]; 637 638 while (*p == ' ') 639 p++; 640 641 while (*p) { 642 /* Note the last non-whitespace index */ 643 if (!isspace(*p)) 644 s = q; 645 646 *q++ = *p++; 647 } 648 649 *(s + 1) = '\0'; 650 } 651 652 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 653 { 654 unsigned int eax, ebx, ecx, edx; 655 656 c->x86_max_cores = 1; 657 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 658 return; 659 660 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 661 if (eax & 0x1f) 662 c->x86_max_cores = (eax >> 26) + 1; 663 } 664 665 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 666 { 667 unsigned int n, dummy, ebx, ecx, edx, l2size; 668 669 n = c->extended_cpuid_level; 670 671 if (n >= 0x80000005) { 672 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 673 c->x86_cache_size = (ecx>>24) + (edx>>24); 674 #ifdef CONFIG_X86_64 675 /* On K8 L1 TLB is inclusive, so don't count it */ 676 c->x86_tlbsize = 0; 677 #endif 678 } 679 680 if (n < 0x80000006) /* Some chips just has a large L1. */ 681 return; 682 683 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 684 l2size = ecx >> 16; 685 686 #ifdef CONFIG_X86_64 687 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 688 #else 689 /* do processor-specific cache resizing */ 690 if (this_cpu->legacy_cache_size) 691 l2size = this_cpu->legacy_cache_size(c, l2size); 692 693 /* Allow user to override all this if necessary. */ 694 if (cachesize_override != -1) 695 l2size = cachesize_override; 696 697 if (l2size == 0) 698 return; /* Again, no L2 cache is possible */ 699 #endif 700 701 c->x86_cache_size = l2size; 702 } 703 704 u16 __read_mostly tlb_lli_4k[NR_INFO]; 705 u16 __read_mostly tlb_lli_2m[NR_INFO]; 706 u16 __read_mostly tlb_lli_4m[NR_INFO]; 707 u16 __read_mostly tlb_lld_4k[NR_INFO]; 708 u16 __read_mostly tlb_lld_2m[NR_INFO]; 709 u16 __read_mostly tlb_lld_4m[NR_INFO]; 710 u16 __read_mostly tlb_lld_1g[NR_INFO]; 711 712 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 713 { 714 if (this_cpu->c_detect_tlb) 715 this_cpu->c_detect_tlb(c); 716 717 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 718 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 719 tlb_lli_4m[ENTRIES]); 720 721 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 722 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 723 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 724 } 725 726 int detect_ht_early(struct cpuinfo_x86 *c) 727 { 728 #ifdef CONFIG_SMP 729 u32 eax, ebx, ecx, edx; 730 731 if (!cpu_has(c, X86_FEATURE_HT)) 732 return -1; 733 734 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 735 return -1; 736 737 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 738 return -1; 739 740 cpuid(1, &eax, &ebx, &ecx, &edx); 741 742 smp_num_siblings = (ebx & 0xff0000) >> 16; 743 if (smp_num_siblings == 1) 744 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 745 #endif 746 return 0; 747 } 748 749 void detect_ht(struct cpuinfo_x86 *c) 750 { 751 #ifdef CONFIG_SMP 752 int index_msb, core_bits; 753 754 if (detect_ht_early(c) < 0) 755 return; 756 757 index_msb = get_count_order(smp_num_siblings); 758 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 759 760 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 761 762 index_msb = get_count_order(smp_num_siblings); 763 764 core_bits = get_count_order(c->x86_max_cores); 765 766 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 767 ((1 << core_bits) - 1); 768 #endif 769 } 770 771 static void get_cpu_vendor(struct cpuinfo_x86 *c) 772 { 773 char *v = c->x86_vendor_id; 774 int i; 775 776 for (i = 0; i < X86_VENDOR_NUM; i++) { 777 if (!cpu_devs[i]) 778 break; 779 780 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 781 (cpu_devs[i]->c_ident[1] && 782 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 783 784 this_cpu = cpu_devs[i]; 785 c->x86_vendor = this_cpu->c_x86_vendor; 786 return; 787 } 788 } 789 790 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 791 "CPU: Your system may be unstable.\n", v); 792 793 c->x86_vendor = X86_VENDOR_UNKNOWN; 794 this_cpu = &default_cpu; 795 } 796 797 void cpu_detect(struct cpuinfo_x86 *c) 798 { 799 /* Get vendor name */ 800 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 801 (unsigned int *)&c->x86_vendor_id[0], 802 (unsigned int *)&c->x86_vendor_id[8], 803 (unsigned int *)&c->x86_vendor_id[4]); 804 805 c->x86 = 4; 806 /* Intel-defined flags: level 0x00000001 */ 807 if (c->cpuid_level >= 0x00000001) { 808 u32 junk, tfms, cap0, misc; 809 810 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 811 c->x86 = x86_family(tfms); 812 c->x86_model = x86_model(tfms); 813 c->x86_stepping = x86_stepping(tfms); 814 815 if (cap0 & (1<<19)) { 816 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 817 c->x86_cache_alignment = c->x86_clflush_size; 818 } 819 } 820 } 821 822 static void apply_forced_caps(struct cpuinfo_x86 *c) 823 { 824 int i; 825 826 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 827 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 828 c->x86_capability[i] |= cpu_caps_set[i]; 829 } 830 } 831 832 static void init_speculation_control(struct cpuinfo_x86 *c) 833 { 834 /* 835 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 836 * and they also have a different bit for STIBP support. Also, 837 * a hypervisor might have set the individual AMD bits even on 838 * Intel CPUs, for finer-grained selection of what's available. 839 */ 840 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 841 set_cpu_cap(c, X86_FEATURE_IBRS); 842 set_cpu_cap(c, X86_FEATURE_IBPB); 843 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 844 } 845 846 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 847 set_cpu_cap(c, X86_FEATURE_STIBP); 848 849 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 850 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 851 set_cpu_cap(c, X86_FEATURE_SSBD); 852 853 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 854 set_cpu_cap(c, X86_FEATURE_IBRS); 855 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 856 } 857 858 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 859 set_cpu_cap(c, X86_FEATURE_IBPB); 860 861 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 862 set_cpu_cap(c, X86_FEATURE_STIBP); 863 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 864 } 865 866 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { 867 set_cpu_cap(c, X86_FEATURE_SSBD); 868 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 869 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); 870 } 871 } 872 873 static void init_cqm(struct cpuinfo_x86 *c) 874 { 875 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 876 c->x86_cache_max_rmid = -1; 877 c->x86_cache_occ_scale = -1; 878 return; 879 } 880 881 /* will be overridden if occupancy monitoring exists */ 882 c->x86_cache_max_rmid = cpuid_ebx(0xf); 883 884 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 885 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 886 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 887 u32 eax, ebx, ecx, edx; 888 889 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 890 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 891 892 c->x86_cache_max_rmid = ecx; 893 c->x86_cache_occ_scale = ebx; 894 } 895 } 896 897 void get_cpu_cap(struct cpuinfo_x86 *c) 898 { 899 u32 eax, ebx, ecx, edx; 900 901 /* Intel-defined flags: level 0x00000001 */ 902 if (c->cpuid_level >= 0x00000001) { 903 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 904 905 c->x86_capability[CPUID_1_ECX] = ecx; 906 c->x86_capability[CPUID_1_EDX] = edx; 907 } 908 909 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 910 if (c->cpuid_level >= 0x00000006) 911 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 912 913 /* Additional Intel-defined flags: level 0x00000007 */ 914 if (c->cpuid_level >= 0x00000007) { 915 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 916 c->x86_capability[CPUID_7_0_EBX] = ebx; 917 c->x86_capability[CPUID_7_ECX] = ecx; 918 c->x86_capability[CPUID_7_EDX] = edx; 919 920 /* Check valid sub-leaf index before accessing it */ 921 if (eax >= 1) { 922 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); 923 c->x86_capability[CPUID_7_1_EAX] = eax; 924 } 925 } 926 927 /* Extended state features: level 0x0000000d */ 928 if (c->cpuid_level >= 0x0000000d) { 929 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 930 931 c->x86_capability[CPUID_D_1_EAX] = eax; 932 } 933 934 /* AMD-defined flags: level 0x80000001 */ 935 eax = cpuid_eax(0x80000000); 936 c->extended_cpuid_level = eax; 937 938 if ((eax & 0xffff0000) == 0x80000000) { 939 if (eax >= 0x80000001) { 940 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 941 942 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 943 c->x86_capability[CPUID_8000_0001_EDX] = edx; 944 } 945 } 946 947 if (c->extended_cpuid_level >= 0x80000007) { 948 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 949 950 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 951 c->x86_power = edx; 952 } 953 954 if (c->extended_cpuid_level >= 0x80000008) { 955 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 956 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 957 } 958 959 if (c->extended_cpuid_level >= 0x8000000a) 960 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 961 962 init_scattered_cpuid_features(c); 963 init_speculation_control(c); 964 init_cqm(c); 965 966 /* 967 * Clear/Set all flags overridden by options, after probe. 968 * This needs to happen each time we re-probe, which may happen 969 * several times during CPU initialization. 970 */ 971 apply_forced_caps(c); 972 } 973 974 void get_cpu_address_sizes(struct cpuinfo_x86 *c) 975 { 976 u32 eax, ebx, ecx, edx; 977 978 if (c->extended_cpuid_level >= 0x80000008) { 979 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 980 981 c->x86_virt_bits = (eax >> 8) & 0xff; 982 c->x86_phys_bits = eax & 0xff; 983 } 984 #ifdef CONFIG_X86_32 985 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 986 c->x86_phys_bits = 36; 987 #endif 988 c->x86_cache_bits = c->x86_phys_bits; 989 } 990 991 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 992 { 993 #ifdef CONFIG_X86_32 994 int i; 995 996 /* 997 * First of all, decide if this is a 486 or higher 998 * It's a 486 if we can modify the AC flag 999 */ 1000 if (flag_is_changeable_p(X86_EFLAGS_AC)) 1001 c->x86 = 4; 1002 else 1003 c->x86 = 3; 1004 1005 for (i = 0; i < X86_VENDOR_NUM; i++) 1006 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 1007 c->x86_vendor_id[0] = 0; 1008 cpu_devs[i]->c_identify(c); 1009 if (c->x86_vendor_id[0]) { 1010 get_cpu_vendor(c); 1011 break; 1012 } 1013 } 1014 #endif 1015 } 1016 1017 #define NO_SPECULATION BIT(0) 1018 #define NO_MELTDOWN BIT(1) 1019 #define NO_SSB BIT(2) 1020 #define NO_L1TF BIT(3) 1021 #define NO_MDS BIT(4) 1022 #define MSBDS_ONLY BIT(5) 1023 #define NO_SWAPGS BIT(6) 1024 #define NO_ITLB_MULTIHIT BIT(7) 1025 1026 #define VULNWL(_vendor, _family, _model, _whitelist) \ 1027 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } 1028 1029 #define VULNWL_INTEL(model, whitelist) \ 1030 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) 1031 1032 #define VULNWL_AMD(family, whitelist) \ 1033 VULNWL(AMD, family, X86_MODEL_ANY, whitelist) 1034 1035 #define VULNWL_HYGON(family, whitelist) \ 1036 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) 1037 1038 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 1039 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), 1040 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), 1041 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), 1042 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), 1043 1044 /* Intel Family 6 */ 1045 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1046 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), 1047 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1048 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), 1049 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), 1050 1051 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1052 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1053 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1054 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1055 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1056 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1057 1058 VULNWL_INTEL(CORE_YONAH, NO_SSB), 1059 1060 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), 1061 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1062 1063 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1064 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1065 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), 1066 1067 /* 1068 * Technically, swapgs isn't serializing on AMD (despite it previously 1069 * being documented as such in the APM). But according to AMD, %gs is 1070 * updated non-speculatively, and the issuing of %gs-relative memory 1071 * operands will be blocked until the %gs update completes, which is 1072 * good enough for our purposes. 1073 */ 1074 1075 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), 1076 1077 /* AMD Family 0xf - 0x12 */ 1078 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1079 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1080 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1081 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1082 1083 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ 1084 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1085 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), 1086 {} 1087 }; 1088 1089 static bool __init cpu_matches(unsigned long which) 1090 { 1091 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); 1092 1093 return m && !!(m->driver_data & which); 1094 } 1095 1096 u64 x86_read_arch_cap_msr(void) 1097 { 1098 u64 ia32_cap = 0; 1099 1100 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1101 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 1102 1103 return ia32_cap; 1104 } 1105 1106 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 1107 { 1108 u64 ia32_cap = x86_read_arch_cap_msr(); 1109 1110 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ 1111 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) 1112 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); 1113 1114 if (cpu_matches(NO_SPECULATION)) 1115 return; 1116 1117 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 1118 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 1119 1120 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && 1121 !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) 1122 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 1123 1124 if (ia32_cap & ARCH_CAP_IBRS_ALL) 1125 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); 1126 1127 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { 1128 setup_force_cpu_bug(X86_BUG_MDS); 1129 if (cpu_matches(MSBDS_ONLY)) 1130 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); 1131 } 1132 1133 if (!cpu_matches(NO_SWAPGS)) 1134 setup_force_cpu_bug(X86_BUG_SWAPGS); 1135 1136 /* 1137 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: 1138 * - TSX is supported or 1139 * - TSX_CTRL is present 1140 * 1141 * TSX_CTRL check is needed for cases when TSX could be disabled before 1142 * the kernel boot e.g. kexec. 1143 * TSX_CTRL check alone is not sufficient for cases when the microcode 1144 * update is not present or running as guest that don't get TSX_CTRL. 1145 */ 1146 if (!(ia32_cap & ARCH_CAP_TAA_NO) && 1147 (cpu_has(c, X86_FEATURE_RTM) || 1148 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) 1149 setup_force_cpu_bug(X86_BUG_TAA); 1150 1151 if (cpu_matches(NO_MELTDOWN)) 1152 return; 1153 1154 /* Rogue Data Cache Load? No! */ 1155 if (ia32_cap & ARCH_CAP_RDCL_NO) 1156 return; 1157 1158 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1159 1160 if (cpu_matches(NO_L1TF)) 1161 return; 1162 1163 setup_force_cpu_bug(X86_BUG_L1TF); 1164 } 1165 1166 /* 1167 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1168 * unfortunately, that's not true in practice because of early VIA 1169 * chips and (more importantly) broken virtualizers that are not easy 1170 * to detect. In the latter case it doesn't even *fail* reliably, so 1171 * probing for it doesn't even work. Disable it completely on 32-bit 1172 * unless we can find a reliable way to detect all the broken cases. 1173 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1174 */ 1175 static void detect_nopl(void) 1176 { 1177 #ifdef CONFIG_X86_32 1178 setup_clear_cpu_cap(X86_FEATURE_NOPL); 1179 #else 1180 setup_force_cpu_cap(X86_FEATURE_NOPL); 1181 #endif 1182 } 1183 1184 /* 1185 * Do minimum CPU detection early. 1186 * Fields really needed: vendor, cpuid_level, family, model, mask, 1187 * cache alignment. 1188 * The others are not touched to avoid unwanted side effects. 1189 * 1190 * WARNING: this function is only called on the boot CPU. Don't add code 1191 * here that is supposed to run on all CPUs. 1192 */ 1193 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1194 { 1195 #ifdef CONFIG_X86_64 1196 c->x86_clflush_size = 64; 1197 c->x86_phys_bits = 36; 1198 c->x86_virt_bits = 48; 1199 #else 1200 c->x86_clflush_size = 32; 1201 c->x86_phys_bits = 32; 1202 c->x86_virt_bits = 32; 1203 #endif 1204 c->x86_cache_alignment = c->x86_clflush_size; 1205 1206 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1207 c->extended_cpuid_level = 0; 1208 1209 if (!have_cpuid_p()) 1210 identify_cpu_without_cpuid(c); 1211 1212 /* cyrix could have cpuid enabled via c_identify()*/ 1213 if (have_cpuid_p()) { 1214 cpu_detect(c); 1215 get_cpu_vendor(c); 1216 get_cpu_cap(c); 1217 get_cpu_address_sizes(c); 1218 setup_force_cpu_cap(X86_FEATURE_CPUID); 1219 1220 if (this_cpu->c_early_init) 1221 this_cpu->c_early_init(c); 1222 1223 c->cpu_index = 0; 1224 filter_cpuid_features(c, false); 1225 1226 if (this_cpu->c_bsp_init) 1227 this_cpu->c_bsp_init(c); 1228 } else { 1229 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1230 } 1231 1232 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1233 1234 cpu_set_bug_bits(c); 1235 1236 fpu__init_system(c); 1237 1238 #ifdef CONFIG_X86_32 1239 /* 1240 * Regardless of whether PCID is enumerated, the SDM says 1241 * that it can't be enabled in 32-bit mode. 1242 */ 1243 setup_clear_cpu_cap(X86_FEATURE_PCID); 1244 #endif 1245 1246 /* 1247 * Later in the boot process pgtable_l5_enabled() relies on 1248 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1249 * enabled by this point we need to clear the feature bit to avoid 1250 * false-positives at the later stage. 1251 * 1252 * pgtable_l5_enabled() can be false here for several reasons: 1253 * - 5-level paging is disabled compile-time; 1254 * - it's 32-bit kernel; 1255 * - machine doesn't support 5-level paging; 1256 * - user specified 'no5lvl' in kernel command line. 1257 */ 1258 if (!pgtable_l5_enabled()) 1259 setup_clear_cpu_cap(X86_FEATURE_LA57); 1260 1261 detect_nopl(); 1262 } 1263 1264 void __init early_cpu_init(void) 1265 { 1266 const struct cpu_dev *const *cdev; 1267 int count = 0; 1268 1269 #ifdef CONFIG_PROCESSOR_SELECT 1270 pr_info("KERNEL supported cpus:\n"); 1271 #endif 1272 1273 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1274 const struct cpu_dev *cpudev = *cdev; 1275 1276 if (count >= X86_VENDOR_NUM) 1277 break; 1278 cpu_devs[count] = cpudev; 1279 count++; 1280 1281 #ifdef CONFIG_PROCESSOR_SELECT 1282 { 1283 unsigned int j; 1284 1285 for (j = 0; j < 2; j++) { 1286 if (!cpudev->c_ident[j]) 1287 continue; 1288 pr_info(" %s %s\n", cpudev->c_vendor, 1289 cpudev->c_ident[j]); 1290 } 1291 } 1292 #endif 1293 } 1294 early_identify_cpu(&boot_cpu_data); 1295 } 1296 1297 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1298 { 1299 #ifdef CONFIG_X86_64 1300 /* 1301 * Empirically, writing zero to a segment selector on AMD does 1302 * not clear the base, whereas writing zero to a segment 1303 * selector on Intel does clear the base. Intel's behavior 1304 * allows slightly faster context switches in the common case 1305 * where GS is unused by the prev and next threads. 1306 * 1307 * Since neither vendor documents this anywhere that I can see, 1308 * detect it directly instead of hardcoding the choice by 1309 * vendor. 1310 * 1311 * I've designated AMD's behavior as the "bug" because it's 1312 * counterintuitive and less friendly. 1313 */ 1314 1315 unsigned long old_base, tmp; 1316 rdmsrl(MSR_FS_BASE, old_base); 1317 wrmsrl(MSR_FS_BASE, 1); 1318 loadsegment(fs, 0); 1319 rdmsrl(MSR_FS_BASE, tmp); 1320 if (tmp != 0) 1321 set_cpu_bug(c, X86_BUG_NULL_SEG); 1322 wrmsrl(MSR_FS_BASE, old_base); 1323 #endif 1324 } 1325 1326 static void generic_identify(struct cpuinfo_x86 *c) 1327 { 1328 c->extended_cpuid_level = 0; 1329 1330 if (!have_cpuid_p()) 1331 identify_cpu_without_cpuid(c); 1332 1333 /* cyrix could have cpuid enabled via c_identify()*/ 1334 if (!have_cpuid_p()) 1335 return; 1336 1337 cpu_detect(c); 1338 1339 get_cpu_vendor(c); 1340 1341 get_cpu_cap(c); 1342 1343 get_cpu_address_sizes(c); 1344 1345 if (c->cpuid_level >= 0x00000001) { 1346 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1347 #ifdef CONFIG_X86_32 1348 # ifdef CONFIG_SMP 1349 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1350 # else 1351 c->apicid = c->initial_apicid; 1352 # endif 1353 #endif 1354 c->phys_proc_id = c->initial_apicid; 1355 } 1356 1357 get_model_name(c); /* Default name */ 1358 1359 detect_null_seg_behavior(c); 1360 1361 /* 1362 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1363 * systems that run Linux at CPL > 0 may or may not have the 1364 * issue, but, even if they have the issue, there's absolutely 1365 * nothing we can do about it because we can't use the real IRET 1366 * instruction. 1367 * 1368 * NB: For the time being, only 32-bit kernels support 1369 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1370 * whether to apply espfix using paravirt hooks. If any 1371 * non-paravirt system ever shows up that does *not* have the 1372 * ESPFIX issue, we can change this. 1373 */ 1374 #ifdef CONFIG_X86_32 1375 # ifdef CONFIG_PARAVIRT_XXL 1376 do { 1377 extern void native_iret(void); 1378 if (pv_ops.cpu.iret == native_iret) 1379 set_cpu_bug(c, X86_BUG_ESPFIX); 1380 } while (0); 1381 # else 1382 set_cpu_bug(c, X86_BUG_ESPFIX); 1383 # endif 1384 #endif 1385 } 1386 1387 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1388 { 1389 /* 1390 * The heavy lifting of max_rmid and cache_occ_scale are handled 1391 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1392 * in case CQM bits really aren't there in this CPU. 1393 */ 1394 if (c != &boot_cpu_data) { 1395 boot_cpu_data.x86_cache_max_rmid = 1396 min(boot_cpu_data.x86_cache_max_rmid, 1397 c->x86_cache_max_rmid); 1398 } 1399 } 1400 1401 /* 1402 * Validate that ACPI/mptables have the same information about the 1403 * effective APIC id and update the package map. 1404 */ 1405 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1406 { 1407 #ifdef CONFIG_SMP 1408 unsigned int apicid, cpu = smp_processor_id(); 1409 1410 apicid = apic->cpu_present_to_apicid(cpu); 1411 1412 if (apicid != c->apicid) { 1413 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1414 cpu, apicid, c->initial_apicid); 1415 } 1416 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1417 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); 1418 #else 1419 c->logical_proc_id = 0; 1420 #endif 1421 } 1422 1423 /* 1424 * This does the hard work of actually picking apart the CPU stuff... 1425 */ 1426 static void identify_cpu(struct cpuinfo_x86 *c) 1427 { 1428 int i; 1429 1430 c->loops_per_jiffy = loops_per_jiffy; 1431 c->x86_cache_size = 0; 1432 c->x86_vendor = X86_VENDOR_UNKNOWN; 1433 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1434 c->x86_vendor_id[0] = '\0'; /* Unset */ 1435 c->x86_model_id[0] = '\0'; /* Unset */ 1436 c->x86_max_cores = 1; 1437 c->x86_coreid_bits = 0; 1438 c->cu_id = 0xff; 1439 #ifdef CONFIG_X86_64 1440 c->x86_clflush_size = 64; 1441 c->x86_phys_bits = 36; 1442 c->x86_virt_bits = 48; 1443 #else 1444 c->cpuid_level = -1; /* CPUID not detected */ 1445 c->x86_clflush_size = 32; 1446 c->x86_phys_bits = 32; 1447 c->x86_virt_bits = 32; 1448 #endif 1449 c->x86_cache_alignment = c->x86_clflush_size; 1450 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); 1451 1452 generic_identify(c); 1453 1454 if (this_cpu->c_identify) 1455 this_cpu->c_identify(c); 1456 1457 /* Clear/Set all flags overridden by options, after probe */ 1458 apply_forced_caps(c); 1459 1460 #ifdef CONFIG_X86_64 1461 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1462 #endif 1463 1464 /* 1465 * Vendor-specific initialization. In this section we 1466 * canonicalize the feature flags, meaning if there are 1467 * features a certain CPU supports which CPUID doesn't 1468 * tell us, CPUID claiming incorrect flags, or other bugs, 1469 * we handle them here. 1470 * 1471 * At the end of this section, c->x86_capability better 1472 * indicate the features this CPU genuinely supports! 1473 */ 1474 if (this_cpu->c_init) 1475 this_cpu->c_init(c); 1476 1477 /* Disable the PN if appropriate */ 1478 squash_the_stupid_serial_number(c); 1479 1480 /* Set up SMEP/SMAP/UMIP */ 1481 setup_smep(c); 1482 setup_smap(c); 1483 setup_umip(c); 1484 1485 /* 1486 * The vendor-specific functions might have changed features. 1487 * Now we do "generic changes." 1488 */ 1489 1490 /* Filter out anything that depends on CPUID levels we don't have */ 1491 filter_cpuid_features(c, true); 1492 1493 /* If the model name is still unset, do table lookup. */ 1494 if (!c->x86_model_id[0]) { 1495 const char *p; 1496 p = table_lookup_model(c); 1497 if (p) 1498 strcpy(c->x86_model_id, p); 1499 else 1500 /* Last resort... */ 1501 sprintf(c->x86_model_id, "%02x/%02x", 1502 c->x86, c->x86_model); 1503 } 1504 1505 #ifdef CONFIG_X86_64 1506 detect_ht(c); 1507 #endif 1508 1509 x86_init_rdrand(c); 1510 x86_init_cache_qos(c); 1511 setup_pku(c); 1512 1513 /* 1514 * Clear/Set all flags overridden by options, need do it 1515 * before following smp all cpus cap AND. 1516 */ 1517 apply_forced_caps(c); 1518 1519 /* 1520 * On SMP, boot_cpu_data holds the common feature set between 1521 * all CPUs; so make sure that we indicate which features are 1522 * common between the CPUs. The first time this routine gets 1523 * executed, c == &boot_cpu_data. 1524 */ 1525 if (c != &boot_cpu_data) { 1526 /* AND the already accumulated flags with these */ 1527 for (i = 0; i < NCAPINTS; i++) 1528 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1529 1530 /* OR, i.e. replicate the bug flags */ 1531 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1532 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1533 } 1534 1535 /* Init Machine Check Exception if available. */ 1536 mcheck_cpu_init(c); 1537 1538 select_idle_routine(c); 1539 1540 #ifdef CONFIG_NUMA 1541 numa_add_cpu(smp_processor_id()); 1542 #endif 1543 } 1544 1545 /* 1546 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1547 * on 32-bit kernels: 1548 */ 1549 #ifdef CONFIG_X86_32 1550 void enable_sep_cpu(void) 1551 { 1552 struct tss_struct *tss; 1553 int cpu; 1554 1555 if (!boot_cpu_has(X86_FEATURE_SEP)) 1556 return; 1557 1558 cpu = get_cpu(); 1559 tss = &per_cpu(cpu_tss_rw, cpu); 1560 1561 /* 1562 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1563 * see the big comment in struct x86_hw_tss's definition. 1564 */ 1565 1566 tss->x86_tss.ss1 = __KERNEL_CS; 1567 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1568 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1569 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1570 1571 put_cpu(); 1572 } 1573 #endif 1574 1575 void __init identify_boot_cpu(void) 1576 { 1577 identify_cpu(&boot_cpu_data); 1578 #ifdef CONFIG_X86_32 1579 sysenter_setup(); 1580 enable_sep_cpu(); 1581 #endif 1582 cpu_detect_tlb(&boot_cpu_data); 1583 setup_cr_pinning(); 1584 1585 tsx_init(); 1586 } 1587 1588 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1589 { 1590 BUG_ON(c == &boot_cpu_data); 1591 identify_cpu(c); 1592 #ifdef CONFIG_X86_32 1593 enable_sep_cpu(); 1594 #endif 1595 mtrr_ap_init(); 1596 validate_apic_and_package_id(c); 1597 x86_spec_ctrl_setup_ap(); 1598 } 1599 1600 static __init int setup_noclflush(char *arg) 1601 { 1602 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1603 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1604 return 1; 1605 } 1606 __setup("noclflush", setup_noclflush); 1607 1608 void print_cpu_info(struct cpuinfo_x86 *c) 1609 { 1610 const char *vendor = NULL; 1611 1612 if (c->x86_vendor < X86_VENDOR_NUM) { 1613 vendor = this_cpu->c_vendor; 1614 } else { 1615 if (c->cpuid_level >= 0) 1616 vendor = c->x86_vendor_id; 1617 } 1618 1619 if (vendor && !strstr(c->x86_model_id, vendor)) 1620 pr_cont("%s ", vendor); 1621 1622 if (c->x86_model_id[0]) 1623 pr_cont("%s", c->x86_model_id); 1624 else 1625 pr_cont("%d86", c->x86); 1626 1627 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1628 1629 if (c->x86_stepping || c->cpuid_level >= 0) 1630 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1631 else 1632 pr_cont(")\n"); 1633 } 1634 1635 /* 1636 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1637 * But we need to keep a dummy __setup around otherwise it would 1638 * show up as an environment variable for init. 1639 */ 1640 static __init int setup_clearcpuid(char *arg) 1641 { 1642 return 1; 1643 } 1644 __setup("clearcpuid=", setup_clearcpuid); 1645 1646 #ifdef CONFIG_X86_64 1647 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, 1648 fixed_percpu_data) __aligned(PAGE_SIZE) __visible; 1649 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); 1650 1651 /* 1652 * The following percpu variables are hot. Align current_task to 1653 * cacheline size such that they fall in the same cacheline. 1654 */ 1655 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1656 &init_task; 1657 EXPORT_PER_CPU_SYMBOL(current_task); 1658 1659 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 1660 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1661 1662 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1663 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1664 1665 /* May not be marked __init: used by software suspend */ 1666 void syscall_init(void) 1667 { 1668 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1669 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1670 1671 #ifdef CONFIG_IA32_EMULATION 1672 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1673 /* 1674 * This only works on Intel CPUs. 1675 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1676 * This does not cause SYSENTER to jump to the wrong location, because 1677 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1678 */ 1679 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1680 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1681 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 1682 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1683 #else 1684 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1685 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1686 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1687 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1688 #endif 1689 1690 /* Flags to clear on syscall */ 1691 wrmsrl(MSR_SYSCALL_MASK, 1692 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1693 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1694 } 1695 1696 DEFINE_PER_CPU(int, debug_stack_usage); 1697 DEFINE_PER_CPU(u32, debug_idt_ctr); 1698 1699 void debug_stack_set_zero(void) 1700 { 1701 this_cpu_inc(debug_idt_ctr); 1702 load_current_idt(); 1703 } 1704 NOKPROBE_SYMBOL(debug_stack_set_zero); 1705 1706 void debug_stack_reset(void) 1707 { 1708 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1709 return; 1710 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1711 load_current_idt(); 1712 } 1713 NOKPROBE_SYMBOL(debug_stack_reset); 1714 1715 #else /* CONFIG_X86_64 */ 1716 1717 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1718 EXPORT_PER_CPU_SYMBOL(current_task); 1719 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1720 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1721 1722 /* 1723 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1724 * the top of the kernel stack. Use an extra percpu variable to track the 1725 * top of the kernel stack directly. 1726 */ 1727 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1728 (unsigned long)&init_thread_union + THREAD_SIZE; 1729 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1730 1731 #ifdef CONFIG_STACKPROTECTOR 1732 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1733 #endif 1734 1735 #endif /* CONFIG_X86_64 */ 1736 1737 /* 1738 * Clear all 6 debug registers: 1739 */ 1740 static void clear_all_debug_regs(void) 1741 { 1742 int i; 1743 1744 for (i = 0; i < 8; i++) { 1745 /* Ignore db4, db5 */ 1746 if ((i == 4) || (i == 5)) 1747 continue; 1748 1749 set_debugreg(0, i); 1750 } 1751 } 1752 1753 #ifdef CONFIG_KGDB 1754 /* 1755 * Restore debug regs if using kgdbwait and you have a kernel debugger 1756 * connection established. 1757 */ 1758 static void dbg_restore_debug_regs(void) 1759 { 1760 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1761 arch_kgdb_ops.correct_hw_break(); 1762 } 1763 #else /* ! CONFIG_KGDB */ 1764 #define dbg_restore_debug_regs() 1765 #endif /* ! CONFIG_KGDB */ 1766 1767 static void wait_for_master_cpu(int cpu) 1768 { 1769 #ifdef CONFIG_SMP 1770 /* 1771 * wait for ACK from master CPU before continuing 1772 * with AP initialization 1773 */ 1774 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1775 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1776 cpu_relax(); 1777 #endif 1778 } 1779 1780 #ifdef CONFIG_X86_64 1781 static inline void setup_getcpu(int cpu) 1782 { 1783 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); 1784 struct desc_struct d = { }; 1785 1786 if (boot_cpu_has(X86_FEATURE_RDTSCP)) 1787 write_rdtscp_aux(cpudata); 1788 1789 /* Store CPU and node number in limit. */ 1790 d.limit0 = cpudata; 1791 d.limit1 = cpudata >> 16; 1792 1793 d.type = 5; /* RO data, expand down, accessed */ 1794 d.dpl = 3; /* Visible to user code */ 1795 d.s = 1; /* Not a system segment */ 1796 d.p = 1; /* Present */ 1797 d.d = 1; /* 32-bit */ 1798 1799 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); 1800 } 1801 1802 static inline void ucode_cpu_init(int cpu) 1803 { 1804 if (cpu) 1805 load_ucode_ap(); 1806 } 1807 1808 static inline void tss_setup_ist(struct tss_struct *tss) 1809 { 1810 /* Set up the per-CPU TSS IST stacks */ 1811 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); 1812 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); 1813 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); 1814 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); 1815 } 1816 1817 static inline void gdt_setup_doublefault_tss(int cpu) { } 1818 1819 #else /* CONFIG_X86_64 */ 1820 1821 static inline void setup_getcpu(int cpu) { } 1822 1823 static inline void ucode_cpu_init(int cpu) 1824 { 1825 show_ucode_info_early(); 1826 } 1827 1828 static inline void tss_setup_ist(struct tss_struct *tss) { } 1829 1830 static inline void gdt_setup_doublefault_tss(int cpu) 1831 { 1832 #ifdef CONFIG_DOUBLEFAULT 1833 /* Set up the doublefault TSS pointer in the GDT */ 1834 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1835 #endif 1836 } 1837 #endif /* !CONFIG_X86_64 */ 1838 1839 static inline void tss_setup_io_bitmap(struct tss_struct *tss) 1840 { 1841 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; 1842 1843 #ifdef CONFIG_X86_IOPL_IOPERM 1844 tss->io_bitmap.prev_max = 0; 1845 tss->io_bitmap.prev_sequence = 0; 1846 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); 1847 /* 1848 * Invalidate the extra array entry past the end of the all 1849 * permission bitmap as required by the hardware. 1850 */ 1851 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; 1852 #endif 1853 } 1854 1855 /* 1856 * cpu_init() initializes state that is per-CPU. Some data is already 1857 * initialized (naturally) in the bootstrap process, such as the GDT 1858 * and IDT. We reload them nevertheless, this function acts as a 1859 * 'CPU state barrier', nothing should get across. 1860 */ 1861 void cpu_init(void) 1862 { 1863 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 1864 struct task_struct *cur = current; 1865 int cpu = raw_smp_processor_id(); 1866 1867 wait_for_master_cpu(cpu); 1868 1869 ucode_cpu_init(cpu); 1870 1871 #ifdef CONFIG_NUMA 1872 if (this_cpu_read(numa_node) == 0 && 1873 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1874 set_numa_node(early_cpu_to_node(cpu)); 1875 #endif 1876 setup_getcpu(cpu); 1877 1878 pr_debug("Initializing CPU#%d\n", cpu); 1879 1880 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || 1881 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) 1882 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1883 1884 /* 1885 * Initialize the per-CPU GDT with the boot GDT, 1886 * and set up the GDT descriptor: 1887 */ 1888 switch_to_new_gdt(cpu); 1889 load_current_idt(); 1890 1891 if (IS_ENABLED(CONFIG_X86_64)) { 1892 loadsegment(fs, 0); 1893 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1894 syscall_init(); 1895 1896 wrmsrl(MSR_FS_BASE, 0); 1897 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1898 barrier(); 1899 1900 x2apic_setup(); 1901 } 1902 1903 mmgrab(&init_mm); 1904 cur->active_mm = &init_mm; 1905 BUG_ON(cur->mm); 1906 initialize_tlbstate_and_flush(); 1907 enter_lazy_tlb(&init_mm, cur); 1908 1909 /* Initialize the TSS. */ 1910 tss_setup_ist(tss); 1911 tss_setup_io_bitmap(tss); 1912 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1913 1914 load_TR_desc(); 1915 /* 1916 * sp0 points to the entry trampoline stack regardless of what task 1917 * is running. 1918 */ 1919 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1920 1921 load_mm_ldt(&init_mm); 1922 1923 clear_all_debug_regs(); 1924 dbg_restore_debug_regs(); 1925 1926 gdt_setup_doublefault_tss(cpu); 1927 1928 fpu__init_cpu(); 1929 1930 if (is_uv_system()) 1931 uv_cpu_init(); 1932 1933 load_fixmap_gdt(cpu); 1934 } 1935 1936 /* 1937 * The microcode loader calls this upon late microcode load to recheck features, 1938 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1939 * hotplug lock. 1940 */ 1941 void microcode_check(void) 1942 { 1943 struct cpuinfo_x86 info; 1944 1945 perf_check_microcode(); 1946 1947 /* Reload CPUID max function as it might've changed. */ 1948 info.cpuid_level = cpuid_eax(0); 1949 1950 /* 1951 * Copy all capability leafs to pick up the synthetic ones so that 1952 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1953 * get overwritten in get_cpu_cap(). 1954 */ 1955 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1956 1957 get_cpu_cap(&info); 1958 1959 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1960 return; 1961 1962 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1963 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1964 } 1965 1966 /* 1967 * Invoked from core CPU hotplug code after hotplug operations 1968 */ 1969 void arch_smt_update(void) 1970 { 1971 /* Handle the speculative execution misfeatures */ 1972 cpu_bugs_smt_update(); 1973 /* Check whether IPI broadcasting can be enabled */ 1974 apic_smt_update(); 1975 } 1976