1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 #include <asm/intel-family.h> 51 #include <asm/cpu_device_id.h> 52 53 #ifdef CONFIG_X86_LOCAL_APIC 54 #include <asm/uv/uv.h> 55 #endif 56 57 #include "cpu.h" 58 59 u32 elf_hwcap2 __read_mostly; 60 61 /* all of these masks are initialized in setup_cpu_local_masks() */ 62 cpumask_var_t cpu_initialized_mask; 63 cpumask_var_t cpu_callout_mask; 64 cpumask_var_t cpu_callin_mask; 65 66 /* representing cpus for which sibling maps can be computed */ 67 cpumask_var_t cpu_sibling_setup_mask; 68 69 /* correctly size the local cpu masks */ 70 void __init setup_cpu_local_masks(void) 71 { 72 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 73 alloc_bootmem_cpumask_var(&cpu_callin_mask); 74 alloc_bootmem_cpumask_var(&cpu_callout_mask); 75 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 76 } 77 78 static void default_init(struct cpuinfo_x86 *c) 79 { 80 #ifdef CONFIG_X86_64 81 cpu_detect_cache_sizes(c); 82 #else 83 /* Not much we can do here... */ 84 /* Check if at least it has cpuid */ 85 if (c->cpuid_level == -1) { 86 /* No cpuid. It must be an ancient CPU */ 87 if (c->x86 == 4) 88 strcpy(c->x86_model_id, "486"); 89 else if (c->x86 == 3) 90 strcpy(c->x86_model_id, "386"); 91 } 92 #endif 93 } 94 95 static const struct cpu_dev default_cpu = { 96 .c_init = default_init, 97 .c_vendor = "Unknown", 98 .c_x86_vendor = X86_VENDOR_UNKNOWN, 99 }; 100 101 static const struct cpu_dev *this_cpu = &default_cpu; 102 103 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 104 #ifdef CONFIG_X86_64 105 /* 106 * We need valid kernel segments for data and code in long mode too 107 * IRET will check the segment types kkeil 2000/10/28 108 * Also sysret mandates a special GDT layout 109 * 110 * TLS descriptors are currently at a different place compared to i386. 111 * Hopefully nobody expects them at a fixed place (Wine?) 112 */ 113 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 114 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 115 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 117 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 118 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 119 #else 120 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 121 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 122 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 123 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 124 /* 125 * Segments used for calling PnP BIOS have byte granularity. 126 * They code segments and data segments have fixed 64k limits, 127 * the transfer segment sizes are set at run time. 128 */ 129 /* 32-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 131 /* 16-bit code */ 132 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 16-bit data */ 138 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 139 /* 140 * The APM segments have byte granularity and their bases 141 * are set at run time. All have 64k limits. 142 */ 143 /* 32-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 145 /* 16-bit code */ 146 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 147 /* data */ 148 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 149 150 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 151 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 152 GDT_STACK_CANARY_INIT 153 #endif 154 } }; 155 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 156 157 static int __init x86_mpx_setup(char *s) 158 { 159 /* require an exact match without trailing characters */ 160 if (strlen(s)) 161 return 0; 162 163 /* do not emit a message if the feature is not present */ 164 if (!boot_cpu_has(X86_FEATURE_MPX)) 165 return 1; 166 167 setup_clear_cpu_cap(X86_FEATURE_MPX); 168 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 169 return 1; 170 } 171 __setup("nompx", x86_mpx_setup); 172 173 #ifdef CONFIG_X86_64 174 static int __init x86_nopcid_setup(char *s) 175 { 176 /* nopcid doesn't accept parameters */ 177 if (s) 178 return -EINVAL; 179 180 /* do not emit a message if the feature is not present */ 181 if (!boot_cpu_has(X86_FEATURE_PCID)) 182 return 0; 183 184 setup_clear_cpu_cap(X86_FEATURE_PCID); 185 pr_info("nopcid: PCID feature disabled\n"); 186 return 0; 187 } 188 early_param("nopcid", x86_nopcid_setup); 189 #endif 190 191 static int __init x86_noinvpcid_setup(char *s) 192 { 193 /* noinvpcid doesn't accept parameters */ 194 if (s) 195 return -EINVAL; 196 197 /* do not emit a message if the feature is not present */ 198 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 199 return 0; 200 201 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 202 pr_info("noinvpcid: INVPCID feature disabled\n"); 203 return 0; 204 } 205 early_param("noinvpcid", x86_noinvpcid_setup); 206 207 #ifdef CONFIG_X86_32 208 static int cachesize_override = -1; 209 static int disable_x86_serial_nr = 1; 210 211 static int __init cachesize_setup(char *str) 212 { 213 get_option(&str, &cachesize_override); 214 return 1; 215 } 216 __setup("cachesize=", cachesize_setup); 217 218 static int __init x86_sep_setup(char *s) 219 { 220 setup_clear_cpu_cap(X86_FEATURE_SEP); 221 return 1; 222 } 223 __setup("nosep", x86_sep_setup); 224 225 /* Standard macro to see if a specific flag is changeable */ 226 static inline int flag_is_changeable_p(u32 flag) 227 { 228 u32 f1, f2; 229 230 /* 231 * Cyrix and IDT cpus allow disabling of CPUID 232 * so the code below may return different results 233 * when it is executed before and after enabling 234 * the CPUID. Add "volatile" to not allow gcc to 235 * optimize the subsequent calls to this function. 236 */ 237 asm volatile ("pushfl \n\t" 238 "pushfl \n\t" 239 "popl %0 \n\t" 240 "movl %0, %1 \n\t" 241 "xorl %2, %0 \n\t" 242 "pushl %0 \n\t" 243 "popfl \n\t" 244 "pushfl \n\t" 245 "popl %0 \n\t" 246 "popfl \n\t" 247 248 : "=&r" (f1), "=&r" (f2) 249 : "ir" (flag)); 250 251 return ((f1^f2) & flag) != 0; 252 } 253 254 /* Probe for the CPUID instruction */ 255 int have_cpuid_p(void) 256 { 257 return flag_is_changeable_p(X86_EFLAGS_ID); 258 } 259 260 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 261 { 262 unsigned long lo, hi; 263 264 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 265 return; 266 267 /* Disable processor serial number: */ 268 269 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 270 lo |= 0x200000; 271 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 272 273 pr_notice("CPU serial number disabled.\n"); 274 clear_cpu_cap(c, X86_FEATURE_PN); 275 276 /* Disabling the serial number may affect the cpuid level */ 277 c->cpuid_level = cpuid_eax(0); 278 } 279 280 static int __init x86_serial_nr_setup(char *s) 281 { 282 disable_x86_serial_nr = 0; 283 return 1; 284 } 285 __setup("serialnumber", x86_serial_nr_setup); 286 #else 287 static inline int flag_is_changeable_p(u32 flag) 288 { 289 return 1; 290 } 291 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 292 { 293 } 294 #endif 295 296 static __init int setup_disable_smep(char *arg) 297 { 298 setup_clear_cpu_cap(X86_FEATURE_SMEP); 299 /* Check for things that depend on SMEP being enabled: */ 300 check_mpx_erratum(&boot_cpu_data); 301 return 1; 302 } 303 __setup("nosmep", setup_disable_smep); 304 305 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 306 { 307 if (cpu_has(c, X86_FEATURE_SMEP)) 308 cr4_set_bits(X86_CR4_SMEP); 309 } 310 311 static __init int setup_disable_smap(char *arg) 312 { 313 setup_clear_cpu_cap(X86_FEATURE_SMAP); 314 return 1; 315 } 316 __setup("nosmap", setup_disable_smap); 317 318 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 319 { 320 unsigned long eflags = native_save_fl(); 321 322 /* This should have been cleared long ago */ 323 BUG_ON(eflags & X86_EFLAGS_AC); 324 325 if (cpu_has(c, X86_FEATURE_SMAP)) { 326 #ifdef CONFIG_X86_SMAP 327 cr4_set_bits(X86_CR4_SMAP); 328 #else 329 cr4_clear_bits(X86_CR4_SMAP); 330 #endif 331 } 332 } 333 334 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 335 { 336 /* Check the boot processor, plus build option for UMIP. */ 337 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 338 goto out; 339 340 /* Check the current processor's cpuid bits. */ 341 if (!cpu_has(c, X86_FEATURE_UMIP)) 342 goto out; 343 344 cr4_set_bits(X86_CR4_UMIP); 345 346 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); 347 348 return; 349 350 out: 351 /* 352 * Make sure UMIP is disabled in case it was enabled in a 353 * previous boot (e.g., via kexec). 354 */ 355 cr4_clear_bits(X86_CR4_UMIP); 356 } 357 358 /* 359 * Protection Keys are not available in 32-bit mode. 360 */ 361 static bool pku_disabled; 362 363 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 364 { 365 /* check the boot processor, plus compile options for PKU: */ 366 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 367 return; 368 /* checks the actual processor's cpuid bits: */ 369 if (!cpu_has(c, X86_FEATURE_PKU)) 370 return; 371 if (pku_disabled) 372 return; 373 374 cr4_set_bits(X86_CR4_PKE); 375 /* 376 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 377 * cpuid bit to be set. We need to ensure that we 378 * update that bit in this CPU's "cpu_info". 379 */ 380 get_cpu_cap(c); 381 } 382 383 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 384 static __init int setup_disable_pku(char *arg) 385 { 386 /* 387 * Do not clear the X86_FEATURE_PKU bit. All of the 388 * runtime checks are against OSPKE so clearing the 389 * bit does nothing. 390 * 391 * This way, we will see "pku" in cpuinfo, but not 392 * "ospke", which is exactly what we want. It shows 393 * that the CPU has PKU, but the OS has not enabled it. 394 * This happens to be exactly how a system would look 395 * if we disabled the config option. 396 */ 397 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 398 pku_disabled = true; 399 return 1; 400 } 401 __setup("nopku", setup_disable_pku); 402 #endif /* CONFIG_X86_64 */ 403 404 /* 405 * Some CPU features depend on higher CPUID levels, which may not always 406 * be available due to CPUID level capping or broken virtualization 407 * software. Add those features to this table to auto-disable them. 408 */ 409 struct cpuid_dependent_feature { 410 u32 feature; 411 u32 level; 412 }; 413 414 static const struct cpuid_dependent_feature 415 cpuid_dependent_features[] = { 416 { X86_FEATURE_MWAIT, 0x00000005 }, 417 { X86_FEATURE_DCA, 0x00000009 }, 418 { X86_FEATURE_XSAVE, 0x0000000d }, 419 { 0, 0 } 420 }; 421 422 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 423 { 424 const struct cpuid_dependent_feature *df; 425 426 for (df = cpuid_dependent_features; df->feature; df++) { 427 428 if (!cpu_has(c, df->feature)) 429 continue; 430 /* 431 * Note: cpuid_level is set to -1 if unavailable, but 432 * extended_extended_level is set to 0 if unavailable 433 * and the legitimate extended levels are all negative 434 * when signed; hence the weird messing around with 435 * signs here... 436 */ 437 if (!((s32)df->level < 0 ? 438 (u32)df->level > (u32)c->extended_cpuid_level : 439 (s32)df->level > (s32)c->cpuid_level)) 440 continue; 441 442 clear_cpu_cap(c, df->feature); 443 if (!warn) 444 continue; 445 446 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 447 x86_cap_flag(df->feature), df->level); 448 } 449 } 450 451 /* 452 * Naming convention should be: <Name> [(<Codename>)] 453 * This table only is used unless init_<vendor>() below doesn't set it; 454 * in particular, if CPUID levels 0x80000002..4 are supported, this 455 * isn't used 456 */ 457 458 /* Look up CPU names by table lookup. */ 459 static const char *table_lookup_model(struct cpuinfo_x86 *c) 460 { 461 #ifdef CONFIG_X86_32 462 const struct legacy_cpu_model_info *info; 463 464 if (c->x86_model >= 16) 465 return NULL; /* Range check */ 466 467 if (!this_cpu) 468 return NULL; 469 470 info = this_cpu->legacy_models; 471 472 while (info->family) { 473 if (info->family == c->x86) 474 return info->model_names[c->x86_model]; 475 info++; 476 } 477 #endif 478 return NULL; /* Not found */ 479 } 480 481 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 482 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 483 484 void load_percpu_segment(int cpu) 485 { 486 #ifdef CONFIG_X86_32 487 loadsegment(fs, __KERNEL_PERCPU); 488 #else 489 __loadsegment_simple(gs, 0); 490 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 491 #endif 492 load_stack_canary_segment(); 493 } 494 495 #ifdef CONFIG_X86_32 496 /* The 32-bit entry code needs to find cpu_entry_area. */ 497 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 498 #endif 499 500 #ifdef CONFIG_X86_64 501 /* 502 * Special IST stacks which the CPU switches to when it calls 503 * an IST-marked descriptor entry. Up to 7 stacks (hardware 504 * limit), all of them are 4K, except the debug stack which 505 * is 8K. 506 */ 507 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 508 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 509 [DEBUG_STACK - 1] = DEBUG_STKSZ 510 }; 511 #endif 512 513 /* Load the original GDT from the per-cpu structure */ 514 void load_direct_gdt(int cpu) 515 { 516 struct desc_ptr gdt_descr; 517 518 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 519 gdt_descr.size = GDT_SIZE - 1; 520 load_gdt(&gdt_descr); 521 } 522 EXPORT_SYMBOL_GPL(load_direct_gdt); 523 524 /* Load a fixmap remapping of the per-cpu GDT */ 525 void load_fixmap_gdt(int cpu) 526 { 527 struct desc_ptr gdt_descr; 528 529 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 530 gdt_descr.size = GDT_SIZE - 1; 531 load_gdt(&gdt_descr); 532 } 533 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 534 535 /* 536 * Current gdt points %fs at the "master" per-cpu area: after this, 537 * it's on the real one. 538 */ 539 void switch_to_new_gdt(int cpu) 540 { 541 /* Load the original GDT */ 542 load_direct_gdt(cpu); 543 /* Reload the per-cpu base */ 544 load_percpu_segment(cpu); 545 } 546 547 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 548 549 static void get_model_name(struct cpuinfo_x86 *c) 550 { 551 unsigned int *v; 552 char *p, *q, *s; 553 554 if (c->extended_cpuid_level < 0x80000004) 555 return; 556 557 v = (unsigned int *)c->x86_model_id; 558 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 559 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 560 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 561 c->x86_model_id[48] = 0; 562 563 /* Trim whitespace */ 564 p = q = s = &c->x86_model_id[0]; 565 566 while (*p == ' ') 567 p++; 568 569 while (*p) { 570 /* Note the last non-whitespace index */ 571 if (!isspace(*p)) 572 s = q; 573 574 *q++ = *p++; 575 } 576 577 *(s + 1) = '\0'; 578 } 579 580 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 581 { 582 unsigned int n, dummy, ebx, ecx, edx, l2size; 583 584 n = c->extended_cpuid_level; 585 586 if (n >= 0x80000005) { 587 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 588 c->x86_cache_size = (ecx>>24) + (edx>>24); 589 #ifdef CONFIG_X86_64 590 /* On K8 L1 TLB is inclusive, so don't count it */ 591 c->x86_tlbsize = 0; 592 #endif 593 } 594 595 if (n < 0x80000006) /* Some chips just has a large L1. */ 596 return; 597 598 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 599 l2size = ecx >> 16; 600 601 #ifdef CONFIG_X86_64 602 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 603 #else 604 /* do processor-specific cache resizing */ 605 if (this_cpu->legacy_cache_size) 606 l2size = this_cpu->legacy_cache_size(c, l2size); 607 608 /* Allow user to override all this if necessary. */ 609 if (cachesize_override != -1) 610 l2size = cachesize_override; 611 612 if (l2size == 0) 613 return; /* Again, no L2 cache is possible */ 614 #endif 615 616 c->x86_cache_size = l2size; 617 } 618 619 u16 __read_mostly tlb_lli_4k[NR_INFO]; 620 u16 __read_mostly tlb_lli_2m[NR_INFO]; 621 u16 __read_mostly tlb_lli_4m[NR_INFO]; 622 u16 __read_mostly tlb_lld_4k[NR_INFO]; 623 u16 __read_mostly tlb_lld_2m[NR_INFO]; 624 u16 __read_mostly tlb_lld_4m[NR_INFO]; 625 u16 __read_mostly tlb_lld_1g[NR_INFO]; 626 627 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 628 { 629 if (this_cpu->c_detect_tlb) 630 this_cpu->c_detect_tlb(c); 631 632 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 633 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 634 tlb_lli_4m[ENTRIES]); 635 636 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 637 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 638 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 639 } 640 641 void detect_ht(struct cpuinfo_x86 *c) 642 { 643 #ifdef CONFIG_SMP 644 u32 eax, ebx, ecx, edx; 645 int index_msb, core_bits; 646 static bool printed; 647 648 if (!cpu_has(c, X86_FEATURE_HT)) 649 return; 650 651 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 652 goto out; 653 654 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 655 return; 656 657 cpuid(1, &eax, &ebx, &ecx, &edx); 658 659 smp_num_siblings = (ebx & 0xff0000) >> 16; 660 661 if (smp_num_siblings == 1) { 662 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 663 goto out; 664 } 665 666 if (smp_num_siblings <= 1) 667 goto out; 668 669 index_msb = get_count_order(smp_num_siblings); 670 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 671 672 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 673 674 index_msb = get_count_order(smp_num_siblings); 675 676 core_bits = get_count_order(c->x86_max_cores); 677 678 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 679 ((1 << core_bits) - 1); 680 681 out: 682 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 683 pr_info("CPU: Physical Processor ID: %d\n", 684 c->phys_proc_id); 685 pr_info("CPU: Processor Core ID: %d\n", 686 c->cpu_core_id); 687 printed = 1; 688 } 689 #endif 690 } 691 692 static void get_cpu_vendor(struct cpuinfo_x86 *c) 693 { 694 char *v = c->x86_vendor_id; 695 int i; 696 697 for (i = 0; i < X86_VENDOR_NUM; i++) { 698 if (!cpu_devs[i]) 699 break; 700 701 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 702 (cpu_devs[i]->c_ident[1] && 703 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 704 705 this_cpu = cpu_devs[i]; 706 c->x86_vendor = this_cpu->c_x86_vendor; 707 return; 708 } 709 } 710 711 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 712 "CPU: Your system may be unstable.\n", v); 713 714 c->x86_vendor = X86_VENDOR_UNKNOWN; 715 this_cpu = &default_cpu; 716 } 717 718 void cpu_detect(struct cpuinfo_x86 *c) 719 { 720 /* Get vendor name */ 721 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 722 (unsigned int *)&c->x86_vendor_id[0], 723 (unsigned int *)&c->x86_vendor_id[8], 724 (unsigned int *)&c->x86_vendor_id[4]); 725 726 c->x86 = 4; 727 /* Intel-defined flags: level 0x00000001 */ 728 if (c->cpuid_level >= 0x00000001) { 729 u32 junk, tfms, cap0, misc; 730 731 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 732 c->x86 = x86_family(tfms); 733 c->x86_model = x86_model(tfms); 734 c->x86_stepping = x86_stepping(tfms); 735 736 if (cap0 & (1<<19)) { 737 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 738 c->x86_cache_alignment = c->x86_clflush_size; 739 } 740 } 741 } 742 743 static void apply_forced_caps(struct cpuinfo_x86 *c) 744 { 745 int i; 746 747 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 748 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 749 c->x86_capability[i] |= cpu_caps_set[i]; 750 } 751 } 752 753 static void init_speculation_control(struct cpuinfo_x86 *c) 754 { 755 /* 756 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 757 * and they also have a different bit for STIBP support. Also, 758 * a hypervisor might have set the individual AMD bits even on 759 * Intel CPUs, for finer-grained selection of what's available. 760 */ 761 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 762 set_cpu_cap(c, X86_FEATURE_IBRS); 763 set_cpu_cap(c, X86_FEATURE_IBPB); 764 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 765 } 766 767 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 768 set_cpu_cap(c, X86_FEATURE_STIBP); 769 770 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 771 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 772 set_cpu_cap(c, X86_FEATURE_SSBD); 773 774 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 775 set_cpu_cap(c, X86_FEATURE_IBRS); 776 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 777 } 778 779 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 780 set_cpu_cap(c, X86_FEATURE_IBPB); 781 782 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 783 set_cpu_cap(c, X86_FEATURE_STIBP); 784 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 785 } 786 } 787 788 void get_cpu_cap(struct cpuinfo_x86 *c) 789 { 790 u32 eax, ebx, ecx, edx; 791 792 /* Intel-defined flags: level 0x00000001 */ 793 if (c->cpuid_level >= 0x00000001) { 794 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 795 796 c->x86_capability[CPUID_1_ECX] = ecx; 797 c->x86_capability[CPUID_1_EDX] = edx; 798 } 799 800 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 801 if (c->cpuid_level >= 0x00000006) 802 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 803 804 /* Additional Intel-defined flags: level 0x00000007 */ 805 if (c->cpuid_level >= 0x00000007) { 806 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 807 c->x86_capability[CPUID_7_0_EBX] = ebx; 808 c->x86_capability[CPUID_7_ECX] = ecx; 809 c->x86_capability[CPUID_7_EDX] = edx; 810 } 811 812 /* Extended state features: level 0x0000000d */ 813 if (c->cpuid_level >= 0x0000000d) { 814 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 815 816 c->x86_capability[CPUID_D_1_EAX] = eax; 817 } 818 819 /* Additional Intel-defined flags: level 0x0000000F */ 820 if (c->cpuid_level >= 0x0000000F) { 821 822 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 823 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 824 c->x86_capability[CPUID_F_0_EDX] = edx; 825 826 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 827 /* will be overridden if occupancy monitoring exists */ 828 c->x86_cache_max_rmid = ebx; 829 830 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 831 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 832 c->x86_capability[CPUID_F_1_EDX] = edx; 833 834 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 835 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 836 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 837 c->x86_cache_max_rmid = ecx; 838 c->x86_cache_occ_scale = ebx; 839 } 840 } else { 841 c->x86_cache_max_rmid = -1; 842 c->x86_cache_occ_scale = -1; 843 } 844 } 845 846 /* AMD-defined flags: level 0x80000001 */ 847 eax = cpuid_eax(0x80000000); 848 c->extended_cpuid_level = eax; 849 850 if ((eax & 0xffff0000) == 0x80000000) { 851 if (eax >= 0x80000001) { 852 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 853 854 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 855 c->x86_capability[CPUID_8000_0001_EDX] = edx; 856 } 857 } 858 859 if (c->extended_cpuid_level >= 0x80000007) { 860 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 861 862 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 863 c->x86_power = edx; 864 } 865 866 if (c->extended_cpuid_level >= 0x80000008) { 867 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 868 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 869 } 870 871 if (c->extended_cpuid_level >= 0x8000000a) 872 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 873 874 init_scattered_cpuid_features(c); 875 init_speculation_control(c); 876 877 /* 878 * Clear/Set all flags overridden by options, after probe. 879 * This needs to happen each time we re-probe, which may happen 880 * several times during CPU initialization. 881 */ 882 apply_forced_caps(c); 883 } 884 885 static void get_cpu_address_sizes(struct cpuinfo_x86 *c) 886 { 887 u32 eax, ebx, ecx, edx; 888 889 if (c->extended_cpuid_level >= 0x80000008) { 890 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 891 892 c->x86_virt_bits = (eax >> 8) & 0xff; 893 c->x86_phys_bits = eax & 0xff; 894 } 895 #ifdef CONFIG_X86_32 896 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 897 c->x86_phys_bits = 36; 898 #endif 899 } 900 901 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 902 { 903 #ifdef CONFIG_X86_32 904 int i; 905 906 /* 907 * First of all, decide if this is a 486 or higher 908 * It's a 486 if we can modify the AC flag 909 */ 910 if (flag_is_changeable_p(X86_EFLAGS_AC)) 911 c->x86 = 4; 912 else 913 c->x86 = 3; 914 915 for (i = 0; i < X86_VENDOR_NUM; i++) 916 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 917 c->x86_vendor_id[0] = 0; 918 cpu_devs[i]->c_identify(c); 919 if (c->x86_vendor_id[0]) { 920 get_cpu_vendor(c); 921 break; 922 } 923 } 924 #endif 925 } 926 927 static const __initconst struct x86_cpu_id cpu_no_speculation[] = { 928 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, 929 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, 930 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, 931 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, 932 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, 933 { X86_VENDOR_CENTAUR, 5 }, 934 { X86_VENDOR_INTEL, 5 }, 935 { X86_VENDOR_NSC, 5 }, 936 { X86_VENDOR_ANY, 4 }, 937 {} 938 }; 939 940 static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { 941 { X86_VENDOR_AMD }, 942 {} 943 }; 944 945 static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = { 946 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW }, 947 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT }, 948 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL }, 949 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW }, 950 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW }, 951 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, 952 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, 953 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, 954 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, 955 { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH }, 956 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, 957 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, 958 { X86_VENDOR_CENTAUR, 5, }, 959 { X86_VENDOR_INTEL, 5, }, 960 { X86_VENDOR_NSC, 5, }, 961 { X86_VENDOR_AMD, 0x12, }, 962 { X86_VENDOR_AMD, 0x11, }, 963 { X86_VENDOR_AMD, 0x10, }, 964 { X86_VENDOR_AMD, 0xf, }, 965 { X86_VENDOR_ANY, 4, }, 966 {} 967 }; 968 969 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 970 { 971 u64 ia32_cap = 0; 972 973 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) 974 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 975 976 if (!x86_match_cpu(cpu_no_spec_store_bypass) && 977 !(ia32_cap & ARCH_CAP_SSB_NO)) 978 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 979 980 if (x86_match_cpu(cpu_no_speculation)) 981 return; 982 983 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 984 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 985 986 if (x86_match_cpu(cpu_no_meltdown)) 987 return; 988 989 /* Rogue Data Cache Load? No! */ 990 if (ia32_cap & ARCH_CAP_RDCL_NO) 991 return; 992 993 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 994 } 995 996 /* 997 * Do minimum CPU detection early. 998 * Fields really needed: vendor, cpuid_level, family, model, mask, 999 * cache alignment. 1000 * The others are not touched to avoid unwanted side effects. 1001 * 1002 * WARNING: this function is only called on the boot CPU. Don't add code 1003 * here that is supposed to run on all CPUs. 1004 */ 1005 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1006 { 1007 #ifdef CONFIG_X86_64 1008 c->x86_clflush_size = 64; 1009 c->x86_phys_bits = 36; 1010 c->x86_virt_bits = 48; 1011 #else 1012 c->x86_clflush_size = 32; 1013 c->x86_phys_bits = 32; 1014 c->x86_virt_bits = 32; 1015 #endif 1016 c->x86_cache_alignment = c->x86_clflush_size; 1017 1018 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1019 c->extended_cpuid_level = 0; 1020 1021 /* cyrix could have cpuid enabled via c_identify()*/ 1022 if (have_cpuid_p()) { 1023 cpu_detect(c); 1024 get_cpu_vendor(c); 1025 get_cpu_cap(c); 1026 get_cpu_address_sizes(c); 1027 setup_force_cpu_cap(X86_FEATURE_CPUID); 1028 1029 if (this_cpu->c_early_init) 1030 this_cpu->c_early_init(c); 1031 1032 c->cpu_index = 0; 1033 filter_cpuid_features(c, false); 1034 1035 if (this_cpu->c_bsp_init) 1036 this_cpu->c_bsp_init(c); 1037 } else { 1038 identify_cpu_without_cpuid(c); 1039 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1040 } 1041 1042 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1043 1044 cpu_set_bug_bits(c); 1045 1046 fpu__init_system(c); 1047 1048 #ifdef CONFIG_X86_32 1049 /* 1050 * Regardless of whether PCID is enumerated, the SDM says 1051 * that it can't be enabled in 32-bit mode. 1052 */ 1053 setup_clear_cpu_cap(X86_FEATURE_PCID); 1054 #endif 1055 } 1056 1057 void __init early_cpu_init(void) 1058 { 1059 const struct cpu_dev *const *cdev; 1060 int count = 0; 1061 1062 #ifdef CONFIG_PROCESSOR_SELECT 1063 pr_info("KERNEL supported cpus:\n"); 1064 #endif 1065 1066 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1067 const struct cpu_dev *cpudev = *cdev; 1068 1069 if (count >= X86_VENDOR_NUM) 1070 break; 1071 cpu_devs[count] = cpudev; 1072 count++; 1073 1074 #ifdef CONFIG_PROCESSOR_SELECT 1075 { 1076 unsigned int j; 1077 1078 for (j = 0; j < 2; j++) { 1079 if (!cpudev->c_ident[j]) 1080 continue; 1081 pr_info(" %s %s\n", cpudev->c_vendor, 1082 cpudev->c_ident[j]); 1083 } 1084 } 1085 #endif 1086 } 1087 early_identify_cpu(&boot_cpu_data); 1088 } 1089 1090 /* 1091 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1092 * unfortunately, that's not true in practice because of early VIA 1093 * chips and (more importantly) broken virtualizers that are not easy 1094 * to detect. In the latter case it doesn't even *fail* reliably, so 1095 * probing for it doesn't even work. Disable it completely on 32-bit 1096 * unless we can find a reliable way to detect all the broken cases. 1097 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1098 */ 1099 static void detect_nopl(struct cpuinfo_x86 *c) 1100 { 1101 #ifdef CONFIG_X86_32 1102 clear_cpu_cap(c, X86_FEATURE_NOPL); 1103 #else 1104 set_cpu_cap(c, X86_FEATURE_NOPL); 1105 #endif 1106 } 1107 1108 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1109 { 1110 #ifdef CONFIG_X86_64 1111 /* 1112 * Empirically, writing zero to a segment selector on AMD does 1113 * not clear the base, whereas writing zero to a segment 1114 * selector on Intel does clear the base. Intel's behavior 1115 * allows slightly faster context switches in the common case 1116 * where GS is unused by the prev and next threads. 1117 * 1118 * Since neither vendor documents this anywhere that I can see, 1119 * detect it directly instead of hardcoding the choice by 1120 * vendor. 1121 * 1122 * I've designated AMD's behavior as the "bug" because it's 1123 * counterintuitive and less friendly. 1124 */ 1125 1126 unsigned long old_base, tmp; 1127 rdmsrl(MSR_FS_BASE, old_base); 1128 wrmsrl(MSR_FS_BASE, 1); 1129 loadsegment(fs, 0); 1130 rdmsrl(MSR_FS_BASE, tmp); 1131 if (tmp != 0) 1132 set_cpu_bug(c, X86_BUG_NULL_SEG); 1133 wrmsrl(MSR_FS_BASE, old_base); 1134 #endif 1135 } 1136 1137 static void generic_identify(struct cpuinfo_x86 *c) 1138 { 1139 c->extended_cpuid_level = 0; 1140 1141 if (!have_cpuid_p()) 1142 identify_cpu_without_cpuid(c); 1143 1144 /* cyrix could have cpuid enabled via c_identify()*/ 1145 if (!have_cpuid_p()) 1146 return; 1147 1148 cpu_detect(c); 1149 1150 get_cpu_vendor(c); 1151 1152 get_cpu_cap(c); 1153 1154 get_cpu_address_sizes(c); 1155 1156 if (c->cpuid_level >= 0x00000001) { 1157 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1158 #ifdef CONFIG_X86_32 1159 # ifdef CONFIG_SMP 1160 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1161 # else 1162 c->apicid = c->initial_apicid; 1163 # endif 1164 #endif 1165 c->phys_proc_id = c->initial_apicid; 1166 } 1167 1168 get_model_name(c); /* Default name */ 1169 1170 detect_nopl(c); 1171 1172 detect_null_seg_behavior(c); 1173 1174 /* 1175 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1176 * systems that run Linux at CPL > 0 may or may not have the 1177 * issue, but, even if they have the issue, there's absolutely 1178 * nothing we can do about it because we can't use the real IRET 1179 * instruction. 1180 * 1181 * NB: For the time being, only 32-bit kernels support 1182 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1183 * whether to apply espfix using paravirt hooks. If any 1184 * non-paravirt system ever shows up that does *not* have the 1185 * ESPFIX issue, we can change this. 1186 */ 1187 #ifdef CONFIG_X86_32 1188 # ifdef CONFIG_PARAVIRT 1189 do { 1190 extern void native_iret(void); 1191 if (pv_cpu_ops.iret == native_iret) 1192 set_cpu_bug(c, X86_BUG_ESPFIX); 1193 } while (0); 1194 # else 1195 set_cpu_bug(c, X86_BUG_ESPFIX); 1196 # endif 1197 #endif 1198 } 1199 1200 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1201 { 1202 /* 1203 * The heavy lifting of max_rmid and cache_occ_scale are handled 1204 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1205 * in case CQM bits really aren't there in this CPU. 1206 */ 1207 if (c != &boot_cpu_data) { 1208 boot_cpu_data.x86_cache_max_rmid = 1209 min(boot_cpu_data.x86_cache_max_rmid, 1210 c->x86_cache_max_rmid); 1211 } 1212 } 1213 1214 /* 1215 * Validate that ACPI/mptables have the same information about the 1216 * effective APIC id and update the package map. 1217 */ 1218 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1219 { 1220 #ifdef CONFIG_SMP 1221 unsigned int apicid, cpu = smp_processor_id(); 1222 1223 apicid = apic->cpu_present_to_apicid(cpu); 1224 1225 if (apicid != c->apicid) { 1226 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1227 cpu, apicid, c->initial_apicid); 1228 } 1229 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1230 #else 1231 c->logical_proc_id = 0; 1232 #endif 1233 } 1234 1235 /* 1236 * This does the hard work of actually picking apart the CPU stuff... 1237 */ 1238 static void identify_cpu(struct cpuinfo_x86 *c) 1239 { 1240 int i; 1241 1242 c->loops_per_jiffy = loops_per_jiffy; 1243 c->x86_cache_size = 0; 1244 c->x86_vendor = X86_VENDOR_UNKNOWN; 1245 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1246 c->x86_vendor_id[0] = '\0'; /* Unset */ 1247 c->x86_model_id[0] = '\0'; /* Unset */ 1248 c->x86_max_cores = 1; 1249 c->x86_coreid_bits = 0; 1250 c->cu_id = 0xff; 1251 #ifdef CONFIG_X86_64 1252 c->x86_clflush_size = 64; 1253 c->x86_phys_bits = 36; 1254 c->x86_virt_bits = 48; 1255 #else 1256 c->cpuid_level = -1; /* CPUID not detected */ 1257 c->x86_clflush_size = 32; 1258 c->x86_phys_bits = 32; 1259 c->x86_virt_bits = 32; 1260 #endif 1261 c->x86_cache_alignment = c->x86_clflush_size; 1262 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1263 1264 generic_identify(c); 1265 1266 if (this_cpu->c_identify) 1267 this_cpu->c_identify(c); 1268 1269 /* Clear/Set all flags overridden by options, after probe */ 1270 apply_forced_caps(c); 1271 1272 #ifdef CONFIG_X86_64 1273 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1274 #endif 1275 1276 /* 1277 * Vendor-specific initialization. In this section we 1278 * canonicalize the feature flags, meaning if there are 1279 * features a certain CPU supports which CPUID doesn't 1280 * tell us, CPUID claiming incorrect flags, or other bugs, 1281 * we handle them here. 1282 * 1283 * At the end of this section, c->x86_capability better 1284 * indicate the features this CPU genuinely supports! 1285 */ 1286 if (this_cpu->c_init) 1287 this_cpu->c_init(c); 1288 1289 /* Disable the PN if appropriate */ 1290 squash_the_stupid_serial_number(c); 1291 1292 /* Set up SMEP/SMAP/UMIP */ 1293 setup_smep(c); 1294 setup_smap(c); 1295 setup_umip(c); 1296 1297 /* 1298 * The vendor-specific functions might have changed features. 1299 * Now we do "generic changes." 1300 */ 1301 1302 /* Filter out anything that depends on CPUID levels we don't have */ 1303 filter_cpuid_features(c, true); 1304 1305 /* If the model name is still unset, do table lookup. */ 1306 if (!c->x86_model_id[0]) { 1307 const char *p; 1308 p = table_lookup_model(c); 1309 if (p) 1310 strcpy(c->x86_model_id, p); 1311 else 1312 /* Last resort... */ 1313 sprintf(c->x86_model_id, "%02x/%02x", 1314 c->x86, c->x86_model); 1315 } 1316 1317 #ifdef CONFIG_X86_64 1318 detect_ht(c); 1319 #endif 1320 1321 x86_init_rdrand(c); 1322 x86_init_cache_qos(c); 1323 setup_pku(c); 1324 1325 /* 1326 * Clear/Set all flags overridden by options, need do it 1327 * before following smp all cpus cap AND. 1328 */ 1329 apply_forced_caps(c); 1330 1331 /* 1332 * On SMP, boot_cpu_data holds the common feature set between 1333 * all CPUs; so make sure that we indicate which features are 1334 * common between the CPUs. The first time this routine gets 1335 * executed, c == &boot_cpu_data. 1336 */ 1337 if (c != &boot_cpu_data) { 1338 /* AND the already accumulated flags with these */ 1339 for (i = 0; i < NCAPINTS; i++) 1340 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1341 1342 /* OR, i.e. replicate the bug flags */ 1343 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1344 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1345 } 1346 1347 /* Init Machine Check Exception if available. */ 1348 mcheck_cpu_init(c); 1349 1350 select_idle_routine(c); 1351 1352 #ifdef CONFIG_NUMA 1353 numa_add_cpu(smp_processor_id()); 1354 #endif 1355 } 1356 1357 /* 1358 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1359 * on 32-bit kernels: 1360 */ 1361 #ifdef CONFIG_X86_32 1362 void enable_sep_cpu(void) 1363 { 1364 struct tss_struct *tss; 1365 int cpu; 1366 1367 if (!boot_cpu_has(X86_FEATURE_SEP)) 1368 return; 1369 1370 cpu = get_cpu(); 1371 tss = &per_cpu(cpu_tss_rw, cpu); 1372 1373 /* 1374 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1375 * see the big comment in struct x86_hw_tss's definition. 1376 */ 1377 1378 tss->x86_tss.ss1 = __KERNEL_CS; 1379 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1380 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1381 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1382 1383 put_cpu(); 1384 } 1385 #endif 1386 1387 void __init identify_boot_cpu(void) 1388 { 1389 identify_cpu(&boot_cpu_data); 1390 #ifdef CONFIG_X86_32 1391 sysenter_setup(); 1392 enable_sep_cpu(); 1393 #endif 1394 cpu_detect_tlb(&boot_cpu_data); 1395 } 1396 1397 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1398 { 1399 BUG_ON(c == &boot_cpu_data); 1400 identify_cpu(c); 1401 #ifdef CONFIG_X86_32 1402 enable_sep_cpu(); 1403 #endif 1404 mtrr_ap_init(); 1405 validate_apic_and_package_id(c); 1406 x86_spec_ctrl_setup_ap(); 1407 } 1408 1409 static __init int setup_noclflush(char *arg) 1410 { 1411 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1412 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1413 return 1; 1414 } 1415 __setup("noclflush", setup_noclflush); 1416 1417 void print_cpu_info(struct cpuinfo_x86 *c) 1418 { 1419 const char *vendor = NULL; 1420 1421 if (c->x86_vendor < X86_VENDOR_NUM) { 1422 vendor = this_cpu->c_vendor; 1423 } else { 1424 if (c->cpuid_level >= 0) 1425 vendor = c->x86_vendor_id; 1426 } 1427 1428 if (vendor && !strstr(c->x86_model_id, vendor)) 1429 pr_cont("%s ", vendor); 1430 1431 if (c->x86_model_id[0]) 1432 pr_cont("%s", c->x86_model_id); 1433 else 1434 pr_cont("%d86", c->x86); 1435 1436 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1437 1438 if (c->x86_stepping || c->cpuid_level >= 0) 1439 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1440 else 1441 pr_cont(")\n"); 1442 } 1443 1444 /* 1445 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1446 * But we need to keep a dummy __setup around otherwise it would 1447 * show up as an environment variable for init. 1448 */ 1449 static __init int setup_clearcpuid(char *arg) 1450 { 1451 return 1; 1452 } 1453 __setup("clearcpuid=", setup_clearcpuid); 1454 1455 #ifdef CONFIG_X86_64 1456 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1457 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1458 EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union); 1459 1460 /* 1461 * The following percpu variables are hot. Align current_task to 1462 * cacheline size such that they fall in the same cacheline. 1463 */ 1464 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1465 &init_task; 1466 EXPORT_PER_CPU_SYMBOL(current_task); 1467 1468 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1469 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1470 1471 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1472 1473 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1474 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1475 1476 /* May not be marked __init: used by software suspend */ 1477 void syscall_init(void) 1478 { 1479 extern char _entry_trampoline[]; 1480 extern char entry_SYSCALL_64_trampoline[]; 1481 1482 int cpu = smp_processor_id(); 1483 unsigned long SYSCALL64_entry_trampoline = 1484 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + 1485 (entry_SYSCALL_64_trampoline - _entry_trampoline); 1486 1487 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1488 if (static_cpu_has(X86_FEATURE_PTI)) 1489 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); 1490 else 1491 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1492 1493 #ifdef CONFIG_IA32_EMULATION 1494 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1495 /* 1496 * This only works on Intel CPUs. 1497 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1498 * This does not cause SYSENTER to jump to the wrong location, because 1499 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1500 */ 1501 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1502 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 1503 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1504 #else 1505 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1506 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1507 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1508 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1509 #endif 1510 1511 /* Flags to clear on syscall */ 1512 wrmsrl(MSR_SYSCALL_MASK, 1513 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1514 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1515 } 1516 1517 /* 1518 * Copies of the original ist values from the tss are only accessed during 1519 * debugging, no special alignment required. 1520 */ 1521 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1522 1523 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1524 DEFINE_PER_CPU(int, debug_stack_usage); 1525 1526 int is_debug_stack(unsigned long addr) 1527 { 1528 return __this_cpu_read(debug_stack_usage) || 1529 (addr <= __this_cpu_read(debug_stack_addr) && 1530 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1531 } 1532 NOKPROBE_SYMBOL(is_debug_stack); 1533 1534 DEFINE_PER_CPU(u32, debug_idt_ctr); 1535 1536 void debug_stack_set_zero(void) 1537 { 1538 this_cpu_inc(debug_idt_ctr); 1539 load_current_idt(); 1540 } 1541 NOKPROBE_SYMBOL(debug_stack_set_zero); 1542 1543 void debug_stack_reset(void) 1544 { 1545 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1546 return; 1547 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1548 load_current_idt(); 1549 } 1550 NOKPROBE_SYMBOL(debug_stack_reset); 1551 1552 #else /* CONFIG_X86_64 */ 1553 1554 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1555 EXPORT_PER_CPU_SYMBOL(current_task); 1556 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1557 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1558 1559 /* 1560 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1561 * the top of the kernel stack. Use an extra percpu variable to track the 1562 * top of the kernel stack directly. 1563 */ 1564 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1565 (unsigned long)&init_thread_union + THREAD_SIZE; 1566 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1567 1568 #ifdef CONFIG_CC_STACKPROTECTOR 1569 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1570 #endif 1571 1572 #endif /* CONFIG_X86_64 */ 1573 1574 /* 1575 * Clear all 6 debug registers: 1576 */ 1577 static void clear_all_debug_regs(void) 1578 { 1579 int i; 1580 1581 for (i = 0; i < 8; i++) { 1582 /* Ignore db4, db5 */ 1583 if ((i == 4) || (i == 5)) 1584 continue; 1585 1586 set_debugreg(0, i); 1587 } 1588 } 1589 1590 #ifdef CONFIG_KGDB 1591 /* 1592 * Restore debug regs if using kgdbwait and you have a kernel debugger 1593 * connection established. 1594 */ 1595 static void dbg_restore_debug_regs(void) 1596 { 1597 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1598 arch_kgdb_ops.correct_hw_break(); 1599 } 1600 #else /* ! CONFIG_KGDB */ 1601 #define dbg_restore_debug_regs() 1602 #endif /* ! CONFIG_KGDB */ 1603 1604 static void wait_for_master_cpu(int cpu) 1605 { 1606 #ifdef CONFIG_SMP 1607 /* 1608 * wait for ACK from master CPU before continuing 1609 * with AP initialization 1610 */ 1611 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1612 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1613 cpu_relax(); 1614 #endif 1615 } 1616 1617 /* 1618 * cpu_init() initializes state that is per-CPU. Some data is already 1619 * initialized (naturally) in the bootstrap process, such as the GDT 1620 * and IDT. We reload them nevertheless, this function acts as a 1621 * 'CPU state barrier', nothing should get across. 1622 * A lot of state is already set up in PDA init for 64 bit 1623 */ 1624 #ifdef CONFIG_X86_64 1625 1626 void cpu_init(void) 1627 { 1628 struct orig_ist *oist; 1629 struct task_struct *me; 1630 struct tss_struct *t; 1631 unsigned long v; 1632 int cpu = raw_smp_processor_id(); 1633 int i; 1634 1635 wait_for_master_cpu(cpu); 1636 1637 /* 1638 * Initialize the CR4 shadow before doing anything that could 1639 * try to read it. 1640 */ 1641 cr4_init_shadow(); 1642 1643 if (cpu) 1644 load_ucode_ap(); 1645 1646 t = &per_cpu(cpu_tss_rw, cpu); 1647 oist = &per_cpu(orig_ist, cpu); 1648 1649 #ifdef CONFIG_NUMA 1650 if (this_cpu_read(numa_node) == 0 && 1651 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1652 set_numa_node(early_cpu_to_node(cpu)); 1653 #endif 1654 1655 me = current; 1656 1657 pr_debug("Initializing CPU#%d\n", cpu); 1658 1659 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1660 1661 /* 1662 * Initialize the per-CPU GDT with the boot GDT, 1663 * and set up the GDT descriptor: 1664 */ 1665 1666 switch_to_new_gdt(cpu); 1667 loadsegment(fs, 0); 1668 1669 load_current_idt(); 1670 1671 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1672 syscall_init(); 1673 1674 wrmsrl(MSR_FS_BASE, 0); 1675 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1676 barrier(); 1677 1678 x86_configure_nx(); 1679 x2apic_setup(); 1680 1681 /* 1682 * set up and load the per-CPU TSS 1683 */ 1684 if (!oist->ist[0]) { 1685 char *estacks = get_cpu_entry_area(cpu)->exception_stacks; 1686 1687 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1688 estacks += exception_stack_sizes[v]; 1689 oist->ist[v] = t->x86_tss.ist[v] = 1690 (unsigned long)estacks; 1691 if (v == DEBUG_STACK-1) 1692 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1693 } 1694 } 1695 1696 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1697 1698 /* 1699 * <= is required because the CPU will access up to 1700 * 8 bits beyond the end of the IO permission bitmap. 1701 */ 1702 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1703 t->io_bitmap[i] = ~0UL; 1704 1705 mmgrab(&init_mm); 1706 me->active_mm = &init_mm; 1707 BUG_ON(me->mm); 1708 initialize_tlbstate_and_flush(); 1709 enter_lazy_tlb(&init_mm, me); 1710 1711 /* 1712 * Initialize the TSS. sp0 points to the entry trampoline stack 1713 * regardless of what task is running. 1714 */ 1715 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1716 load_TR_desc(); 1717 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1718 1719 load_mm_ldt(&init_mm); 1720 1721 clear_all_debug_regs(); 1722 dbg_restore_debug_regs(); 1723 1724 fpu__init_cpu(); 1725 1726 if (is_uv_system()) 1727 uv_cpu_init(); 1728 1729 load_fixmap_gdt(cpu); 1730 } 1731 1732 #else 1733 1734 void cpu_init(void) 1735 { 1736 int cpu = smp_processor_id(); 1737 struct task_struct *curr = current; 1738 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1739 1740 wait_for_master_cpu(cpu); 1741 1742 /* 1743 * Initialize the CR4 shadow before doing anything that could 1744 * try to read it. 1745 */ 1746 cr4_init_shadow(); 1747 1748 show_ucode_info_early(); 1749 1750 pr_info("Initializing CPU#%d\n", cpu); 1751 1752 if (cpu_feature_enabled(X86_FEATURE_VME) || 1753 boot_cpu_has(X86_FEATURE_TSC) || 1754 boot_cpu_has(X86_FEATURE_DE)) 1755 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1756 1757 load_current_idt(); 1758 switch_to_new_gdt(cpu); 1759 1760 /* 1761 * Set up and load the per-CPU TSS and LDT 1762 */ 1763 mmgrab(&init_mm); 1764 curr->active_mm = &init_mm; 1765 BUG_ON(curr->mm); 1766 initialize_tlbstate_and_flush(); 1767 enter_lazy_tlb(&init_mm, curr); 1768 1769 /* 1770 * Initialize the TSS. Don't bother initializing sp0, as the initial 1771 * task never enters user mode. 1772 */ 1773 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1774 load_TR_desc(); 1775 1776 load_mm_ldt(&init_mm); 1777 1778 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1779 1780 #ifdef CONFIG_DOUBLEFAULT 1781 /* Set up doublefault TSS pointer in the GDT */ 1782 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1783 #endif 1784 1785 clear_all_debug_regs(); 1786 dbg_restore_debug_regs(); 1787 1788 fpu__init_cpu(); 1789 1790 load_fixmap_gdt(cpu); 1791 } 1792 #endif 1793 1794 static void bsp_resume(void) 1795 { 1796 if (this_cpu->c_bsp_resume) 1797 this_cpu->c_bsp_resume(&boot_cpu_data); 1798 } 1799 1800 static struct syscore_ops cpu_syscore_ops = { 1801 .resume = bsp_resume, 1802 }; 1803 1804 static int __init init_cpu_syscore(void) 1805 { 1806 register_syscore_ops(&cpu_syscore_ops); 1807 return 0; 1808 } 1809 core_initcall(init_cpu_syscore); 1810 1811 /* 1812 * The microcode loader calls this upon late microcode load to recheck features, 1813 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1814 * hotplug lock. 1815 */ 1816 void microcode_check(void) 1817 { 1818 struct cpuinfo_x86 info; 1819 1820 perf_check_microcode(); 1821 1822 /* Reload CPUID max function as it might've changed. */ 1823 info.cpuid_level = cpuid_eax(0); 1824 1825 /* 1826 * Copy all capability leafs to pick up the synthetic ones so that 1827 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1828 * get overwritten in get_cpu_cap(). 1829 */ 1830 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1831 1832 get_cpu_cap(&info); 1833 1834 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1835 return; 1836 1837 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1838 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1839 } 1840