1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.rst 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - SYM_FUNC_START/END:Define functions in the symbol table. 19 * - idtentry: Define exception entry points. 20 */ 21#include <linux/linkage.h> 22#include <asm/segment.h> 23#include <asm/cache.h> 24#include <asm/errno.h> 25#include <asm/asm-offsets.h> 26#include <asm/msr.h> 27#include <asm/unistd.h> 28#include <asm/thread_info.h> 29#include <asm/hw_irq.h> 30#include <asm/page_types.h> 31#include <asm/irqflags.h> 32#include <asm/paravirt.h> 33#include <asm/percpu.h> 34#include <asm/asm.h> 35#include <asm/smap.h> 36#include <asm/pgtable_types.h> 37#include <asm/export.h> 38#include <asm/frame.h> 39#include <asm/trapnr.h> 40#include <asm/nospec-branch.h> 41#include <asm/fsgsbase.h> 42#include <linux/err.h> 43 44#include "calling.h" 45 46.code64 47.section .entry.text, "ax" 48 49/* 50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 51 * 52 * This is the only entry point used for 64-bit system calls. The 53 * hardware interface is reasonably well designed and the register to 54 * argument mapping Linux uses fits well with the registers that are 55 * available when SYSCALL is used. 56 * 57 * SYSCALL instructions can be found inlined in libc implementations as 58 * well as some other programs and libraries. There are also a handful 59 * of SYSCALL instructions in the vDSO used, for example, as a 60 * clock_gettimeofday fallback. 61 * 62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 63 * then loads new ss, cs, and rip from previously programmed MSRs. 64 * rflags gets masked by a value from another MSR (so CLD and CLAC 65 * are not needed). SYSCALL does not save anything on the stack 66 * and does not change rsp. 67 * 68 * Registers on entry: 69 * rax system call number 70 * rcx return address 71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 72 * rdi arg0 73 * rsi arg1 74 * rdx arg2 75 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 76 * r8 arg4 77 * r9 arg5 78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 79 * 80 * Only called from user space. 81 * 82 * When user can change pt_regs->foo always force IRET. That is because 83 * it deals with uncanonical addresses better. SYSRET has trouble 84 * with them due to bugs in both AMD and Intel CPUs. 85 */ 86 87SYM_CODE_START(entry_SYSCALL_64) 88 UNWIND_HINT_ENTRY 89 ENDBR 90 91 swapgs 92 /* tss.sp2 is scratch space. */ 93 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) 94 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 95 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp 96 97SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL) 98 ANNOTATE_NOENDBR 99 100 /* Construct struct pt_regs on stack */ 101 pushq $__USER_DS /* pt_regs->ss */ 102 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ 103 pushq %r11 /* pt_regs->flags */ 104 pushq $__USER_CS /* pt_regs->cs */ 105 pushq %rcx /* pt_regs->ip */ 106SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL) 107 pushq %rax /* pt_regs->orig_ax */ 108 109 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 110 111 /* IRQs are off. */ 112 movq %rsp, %rdi 113 /* Sign extend the lower 32bit as syscall numbers are treated as int */ 114 movslq %eax, %rsi 115 116 /* clobbers %rax, make sure it is after saving the syscall nr */ 117 IBRS_ENTER 118 UNTRAIN_RET 119 120 call do_syscall_64 /* returns with IRQs disabled */ 121 122 /* 123 * Try to use SYSRET instead of IRET if we're returning to 124 * a completely clean 64-bit userspace context. If we're not, 125 * go to the slow exit path. 126 * In the Xen PV case we must use iret anyway. 127 */ 128 129 ALTERNATIVE "", "jmp swapgs_restore_regs_and_return_to_usermode", \ 130 X86_FEATURE_XENPV 131 132 movq RCX(%rsp), %rcx 133 movq RIP(%rsp), %r11 134 135 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 136 jne swapgs_restore_regs_and_return_to_usermode 137 138 /* 139 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 140 * in kernel space. This essentially lets the user take over 141 * the kernel, since userspace controls RSP. 142 * 143 * If width of "canonical tail" ever becomes variable, this will need 144 * to be updated to remain correct on both old and new CPUs. 145 * 146 * Change top bits to match most significant bit (47th or 56th bit 147 * depending on paging mode) in the address. 148 */ 149#ifdef CONFIG_X86_5LEVEL 150 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 151 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 152#else 153 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 154 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 155#endif 156 157 /* If this changed %rcx, it was not canonical */ 158 cmpq %rcx, %r11 159 jne swapgs_restore_regs_and_return_to_usermode 160 161 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 162 jne swapgs_restore_regs_and_return_to_usermode 163 164 movq R11(%rsp), %r11 165 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 166 jne swapgs_restore_regs_and_return_to_usermode 167 168 /* 169 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 170 * restore RF properly. If the slowpath sets it for whatever reason, we 171 * need to restore it correctly. 172 * 173 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 174 * trap from userspace immediately after SYSRET. This would cause an 175 * infinite loop whenever #DB happens with register state that satisfies 176 * the opportunistic SYSRET conditions. For example, single-stepping 177 * this user code: 178 * 179 * movq $stuck_here, %rcx 180 * pushfq 181 * popq %r11 182 * stuck_here: 183 * 184 * would never get past 'stuck_here'. 185 */ 186 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 187 jnz swapgs_restore_regs_and_return_to_usermode 188 189 /* nothing to check for RSP */ 190 191 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 192 jne swapgs_restore_regs_and_return_to_usermode 193 194 /* 195 * We win! This label is here just for ease of understanding 196 * perf profiles. Nothing jumps here. 197 */ 198syscall_return_via_sysret: 199 IBRS_EXIT 200 POP_REGS pop_rdi=0 201 202 /* 203 * Now all regs are restored except RSP and RDI. 204 * Save old stack pointer and switch to trampoline stack. 205 */ 206 movq %rsp, %rdi 207 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 208 UNWIND_HINT_EMPTY 209 210 pushq RSP-RDI(%rdi) /* RSP */ 211 pushq (%rdi) /* RDI */ 212 213 /* 214 * We are on the trampoline stack. All regs except RDI are live. 215 * We can do future final exit work right here. 216 */ 217 STACKLEAK_ERASE_NOCLOBBER 218 219 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 220 221 popq %rdi 222 popq %rsp 223SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL) 224 ANNOTATE_NOENDBR 225 swapgs 226 sysretq 227SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL) 228 ANNOTATE_NOENDBR 229 int3 230SYM_CODE_END(entry_SYSCALL_64) 231 232/* 233 * %rdi: prev task 234 * %rsi: next task 235 */ 236.pushsection .text, "ax" 237SYM_FUNC_START(__switch_to_asm) 238 /* 239 * Save callee-saved registers 240 * This must match the order in inactive_task_frame 241 */ 242 pushq %rbp 243 pushq %rbx 244 pushq %r12 245 pushq %r13 246 pushq %r14 247 pushq %r15 248 249 /* switch stack */ 250 movq %rsp, TASK_threadsp(%rdi) 251 movq TASK_threadsp(%rsi), %rsp 252 253#ifdef CONFIG_STACKPROTECTOR 254 movq TASK_stack_canary(%rsi), %rbx 255 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset 256#endif 257 258 /* 259 * When switching from a shallower to a deeper call stack 260 * the RSB may either underflow or use entries populated 261 * with userspace addresses. On CPUs where those concerns 262 * exist, overwrite the RSB with entries which capture 263 * speculative execution to prevent attack. 264 */ 265 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 266 267 /* restore callee-saved registers */ 268 popq %r15 269 popq %r14 270 popq %r13 271 popq %r12 272 popq %rbx 273 popq %rbp 274 275 jmp __switch_to 276SYM_FUNC_END(__switch_to_asm) 277.popsection 278 279/* 280 * A newly forked process directly context switches into this address. 281 * 282 * rax: prev task we switched from 283 * rbx: kernel thread func (NULL for user thread) 284 * r12: kernel thread arg 285 */ 286.pushsection .text, "ax" 287 __FUNC_ALIGN 288SYM_CODE_START_NOALIGN(ret_from_fork) 289 UNWIND_HINT_EMPTY 290 ANNOTATE_NOENDBR // copy_thread 291 movq %rax, %rdi 292 call schedule_tail /* rdi: 'prev' task parameter */ 293 294 testq %rbx, %rbx /* from kernel_thread? */ 295 jnz 1f /* kernel threads are uncommon */ 296 2972: 298 UNWIND_HINT_REGS 299 movq %rsp, %rdi 300 call syscall_exit_to_user_mode /* returns with IRQs disabled */ 301 jmp swapgs_restore_regs_and_return_to_usermode 302 3031: 304 /* kernel thread */ 305 UNWIND_HINT_EMPTY 306 movq %r12, %rdi 307 CALL_NOSPEC rbx 308 /* 309 * A kernel thread is allowed to return here after successfully 310 * calling kernel_execve(). Exit to userspace to complete the execve() 311 * syscall. 312 */ 313 movq $0, RAX(%rsp) 314 jmp 2b 315SYM_CODE_END(ret_from_fork) 316.popsection 317 318.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 319#ifdef CONFIG_DEBUG_ENTRY 320 pushq %rax 321 SAVE_FLAGS 322 testl $X86_EFLAGS_IF, %eax 323 jz .Lokay_\@ 324 ud2 325.Lokay_\@: 326 popq %rax 327#endif 328.endm 329 330SYM_CODE_START_LOCAL(xen_error_entry) 331 UNWIND_HINT_FUNC 332 PUSH_AND_CLEAR_REGS save_ret=1 333 ENCODE_FRAME_POINTER 8 334 UNTRAIN_RET 335 RET 336SYM_CODE_END(xen_error_entry) 337 338/** 339 * idtentry_body - Macro to emit code calling the C function 340 * @cfunc: C function to be called 341 * @has_error_code: Hardware pushed error code on stack 342 */ 343.macro idtentry_body cfunc has_error_code:req 344 345 /* 346 * Call error_entry() and switch to the task stack if from userspace. 347 * 348 * When in XENPV, it is already in the task stack, and it can't fault 349 * for native_iret() nor native_load_gs_index() since XENPV uses its 350 * own pvops for IRET and load_gs_index(). And it doesn't need to 351 * switch the CR3. So it can skip invoking error_entry(). 352 */ 353 ALTERNATIVE "call error_entry; movq %rax, %rsp", \ 354 "call xen_error_entry", X86_FEATURE_XENPV 355 356 ENCODE_FRAME_POINTER 357 UNWIND_HINT_REGS 358 359 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/ 360 361 .if \has_error_code == 1 362 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 363 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 364 .endif 365 366 call \cfunc 367 368 /* For some configurations \cfunc ends up being a noreturn. */ 369 REACHABLE 370 371 jmp error_return 372.endm 373 374/** 375 * idtentry - Macro to generate entry stubs for simple IDT entries 376 * @vector: Vector number 377 * @asmsym: ASM symbol for the entry point 378 * @cfunc: C function to be called 379 * @has_error_code: Hardware pushed error code on stack 380 * 381 * The macro emits code to set up the kernel context for straight forward 382 * and simple IDT entries. No IST stack, no paranoid entry checks. 383 */ 384.macro idtentry vector asmsym cfunc has_error_code:req 385SYM_CODE_START(\asmsym) 386 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 387 ENDBR 388 ASM_CLAC 389 cld 390 391 .if \has_error_code == 0 392 pushq $-1 /* ORIG_RAX: no syscall to restart */ 393 .endif 394 395 .if \vector == X86_TRAP_BP 396 /* 397 * If coming from kernel space, create a 6-word gap to allow the 398 * int3 handler to emulate a call instruction. 399 */ 400 testb $3, CS-ORIG_RAX(%rsp) 401 jnz .Lfrom_usermode_no_gap_\@ 402 .rept 6 403 pushq 5*8(%rsp) 404 .endr 405 UNWIND_HINT_IRET_REGS offset=8 406.Lfrom_usermode_no_gap_\@: 407 .endif 408 409 idtentry_body \cfunc \has_error_code 410 411_ASM_NOKPROBE(\asmsym) 412SYM_CODE_END(\asmsym) 413.endm 414 415/* 416 * Interrupt entry/exit. 417 * 418 + The interrupt stubs push (vector) onto the stack, which is the error_code 419 * position of idtentry exceptions, and jump to one of the two idtentry points 420 * (common/spurious). 421 * 422 * common_interrupt is a hotpath, align it to a cache line 423 */ 424.macro idtentry_irq vector cfunc 425 .p2align CONFIG_X86_L1_CACHE_SHIFT 426 idtentry \vector asm_\cfunc \cfunc has_error_code=1 427.endm 428 429/* 430 * System vectors which invoke their handlers directly and are not 431 * going through the regular common device interrupt handling code. 432 */ 433.macro idtentry_sysvec vector cfunc 434 idtentry \vector asm_\cfunc \cfunc has_error_code=0 435.endm 436 437/** 438 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB 439 * @vector: Vector number 440 * @asmsym: ASM symbol for the entry point 441 * @cfunc: C function to be called 442 * 443 * The macro emits code to set up the kernel context for #MC and #DB 444 * 445 * If the entry comes from user space it uses the normal entry path 446 * including the return to user space work and preemption checks on 447 * exit. 448 * 449 * If hits in kernel mode then it needs to go through the paranoid 450 * entry as the exception can hit any random state. No preemption 451 * check on exit to keep the paranoid path simple. 452 */ 453.macro idtentry_mce_db vector asmsym cfunc 454SYM_CODE_START(\asmsym) 455 UNWIND_HINT_IRET_REGS 456 ENDBR 457 ASM_CLAC 458 cld 459 460 pushq $-1 /* ORIG_RAX: no syscall to restart */ 461 462 /* 463 * If the entry is from userspace, switch stacks and treat it as 464 * a normal entry. 465 */ 466 testb $3, CS-ORIG_RAX(%rsp) 467 jnz .Lfrom_usermode_switch_stack_\@ 468 469 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 470 call paranoid_entry 471 472 UNWIND_HINT_REGS 473 474 movq %rsp, %rdi /* pt_regs pointer */ 475 476 call \cfunc 477 478 jmp paranoid_exit 479 480 /* Switch to the regular task stack and use the noist entry point */ 481.Lfrom_usermode_switch_stack_\@: 482 idtentry_body noist_\cfunc, has_error_code=0 483 484_ASM_NOKPROBE(\asmsym) 485SYM_CODE_END(\asmsym) 486.endm 487 488#ifdef CONFIG_AMD_MEM_ENCRYPT 489/** 490 * idtentry_vc - Macro to generate entry stub for #VC 491 * @vector: Vector number 492 * @asmsym: ASM symbol for the entry point 493 * @cfunc: C function to be called 494 * 495 * The macro emits code to set up the kernel context for #VC. The #VC handler 496 * runs on an IST stack and needs to be able to cause nested #VC exceptions. 497 * 498 * To make this work the #VC entry code tries its best to pretend it doesn't use 499 * an IST stack by switching to the task stack if coming from user-space (which 500 * includes early SYSCALL entry path) or back to the stack in the IRET frame if 501 * entered from kernel-mode. 502 * 503 * If entered from kernel-mode the return stack is validated first, and if it is 504 * not safe to use (e.g. because it points to the entry stack) the #VC handler 505 * will switch to a fall-back stack (VC2) and call a special handler function. 506 * 507 * The macro is only used for one vector, but it is planned to be extended in 508 * the future for the #HV exception. 509 */ 510.macro idtentry_vc vector asmsym cfunc 511SYM_CODE_START(\asmsym) 512 UNWIND_HINT_IRET_REGS 513 ENDBR 514 ASM_CLAC 515 cld 516 517 /* 518 * If the entry is from userspace, switch stacks and treat it as 519 * a normal entry. 520 */ 521 testb $3, CS-ORIG_RAX(%rsp) 522 jnz .Lfrom_usermode_switch_stack_\@ 523 524 /* 525 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX. 526 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS 527 */ 528 call paranoid_entry 529 530 UNWIND_HINT_REGS 531 532 /* 533 * Switch off the IST stack to make it free for nested exceptions. The 534 * vc_switch_off_ist() function will switch back to the interrupted 535 * stack if it is safe to do so. If not it switches to the VC fall-back 536 * stack. 537 */ 538 movq %rsp, %rdi /* pt_regs pointer */ 539 call vc_switch_off_ist 540 movq %rax, %rsp /* Switch to new stack */ 541 542 ENCODE_FRAME_POINTER 543 UNWIND_HINT_REGS 544 545 /* Update pt_regs */ 546 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 547 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 548 549 movq %rsp, %rdi /* pt_regs pointer */ 550 551 call kernel_\cfunc 552 553 /* 554 * No need to switch back to the IST stack. The current stack is either 555 * identical to the stack in the IRET frame or the VC fall-back stack, 556 * so it is definitely mapped even with PTI enabled. 557 */ 558 jmp paranoid_exit 559 560 /* Switch to the regular task stack */ 561.Lfrom_usermode_switch_stack_\@: 562 idtentry_body user_\cfunc, has_error_code=1 563 564_ASM_NOKPROBE(\asmsym) 565SYM_CODE_END(\asmsym) 566.endm 567#endif 568 569/* 570 * Double fault entry. Straight paranoid. No checks from which context 571 * this comes because for the espfix induced #DF this would do the wrong 572 * thing. 573 */ 574.macro idtentry_df vector asmsym cfunc 575SYM_CODE_START(\asmsym) 576 UNWIND_HINT_IRET_REGS offset=8 577 ENDBR 578 ASM_CLAC 579 cld 580 581 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 582 call paranoid_entry 583 UNWIND_HINT_REGS 584 585 movq %rsp, %rdi /* pt_regs pointer into first argument */ 586 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 587 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 588 call \cfunc 589 590 /* For some configurations \cfunc ends up being a noreturn. */ 591 REACHABLE 592 593 jmp paranoid_exit 594 595_ASM_NOKPROBE(\asmsym) 596SYM_CODE_END(\asmsym) 597.endm 598 599/* 600 * Include the defines which emit the idt entries which are shared 601 * shared between 32 and 64 bit and emit the __irqentry_text_* markers 602 * so the stacktrace boundary checks work. 603 */ 604 __ALIGN 605 .globl __irqentry_text_start 606__irqentry_text_start: 607 608#include <asm/idtentry.h> 609 610 __ALIGN 611 .globl __irqentry_text_end 612__irqentry_text_end: 613 ANNOTATE_NOENDBR 614 615SYM_CODE_START_LOCAL(common_interrupt_return) 616SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL) 617 IBRS_EXIT 618#ifdef CONFIG_DEBUG_ENTRY 619 /* Assert that pt_regs indicates user mode. */ 620 testb $3, CS(%rsp) 621 jnz 1f 622 ud2 6231: 624#endif 625#ifdef CONFIG_XEN_PV 626 ALTERNATIVE "", "jmp xenpv_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV 627#endif 628 629 POP_REGS pop_rdi=0 630 631 /* 632 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 633 * Save old stack pointer and switch to trampoline stack. 634 */ 635 movq %rsp, %rdi 636 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 637 UNWIND_HINT_EMPTY 638 639 /* Copy the IRET frame to the trampoline stack. */ 640 pushq 6*8(%rdi) /* SS */ 641 pushq 5*8(%rdi) /* RSP */ 642 pushq 4*8(%rdi) /* EFLAGS */ 643 pushq 3*8(%rdi) /* CS */ 644 pushq 2*8(%rdi) /* RIP */ 645 646 /* Push user RDI on the trampoline stack. */ 647 pushq (%rdi) 648 649 /* 650 * We are on the trampoline stack. All regs except RDI are live. 651 * We can do future final exit work right here. 652 */ 653 STACKLEAK_ERASE_NOCLOBBER 654 655 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 656 657 /* Restore RDI. */ 658 popq %rdi 659 swapgs 660 jmp .Lnative_iret 661 662 663SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL) 664#ifdef CONFIG_DEBUG_ENTRY 665 /* Assert that pt_regs indicates kernel mode. */ 666 testb $3, CS(%rsp) 667 jz 1f 668 ud2 6691: 670#endif 671 POP_REGS 672 addq $8, %rsp /* skip regs->orig_ax */ 673 /* 674 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 675 * when returning from IPI handler. 676 */ 677#ifdef CONFIG_XEN_PV 678SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL) 679 ANNOTATE_NOENDBR 680 .byte 0xe9 681 .long .Lnative_iret - (. + 4) 682#endif 683 684.Lnative_iret: 685 UNWIND_HINT_IRET_REGS 686 /* 687 * Are we returning to a stack segment from the LDT? Note: in 688 * 64-bit mode SS:RSP on the exception stack is always valid. 689 */ 690#ifdef CONFIG_X86_ESPFIX64 691 testb $4, (SS-RIP)(%rsp) 692 jnz native_irq_return_ldt 693#endif 694 695SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL) 696 ANNOTATE_NOENDBR // exc_double_fault 697 /* 698 * This may fault. Non-paranoid faults on return to userspace are 699 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 700 * Double-faults due to espfix64 are handled in exc_double_fault. 701 * Other faults here are fatal. 702 */ 703 iretq 704 705#ifdef CONFIG_X86_ESPFIX64 706native_irq_return_ldt: 707 /* 708 * We are running with user GSBASE. All GPRs contain their user 709 * values. We have a percpu ESPFIX stack that is eight slots 710 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 711 * of the ESPFIX stack. 712 * 713 * We clobber RAX and RDI in this code. We stash RDI on the 714 * normal stack and RAX on the ESPFIX stack. 715 * 716 * The ESPFIX stack layout we set up looks like this: 717 * 718 * --- top of ESPFIX stack --- 719 * SS 720 * RSP 721 * RFLAGS 722 * CS 723 * RIP <-- RSP points here when we're done 724 * RAX <-- espfix_waddr points here 725 * --- bottom of ESPFIX stack --- 726 */ 727 728 pushq %rdi /* Stash user RDI */ 729 swapgs /* to kernel GS */ 730 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 731 732 movq PER_CPU_VAR(espfix_waddr), %rdi 733 movq %rax, (0*8)(%rdi) /* user RAX */ 734 movq (1*8)(%rsp), %rax /* user RIP */ 735 movq %rax, (1*8)(%rdi) 736 movq (2*8)(%rsp), %rax /* user CS */ 737 movq %rax, (2*8)(%rdi) 738 movq (3*8)(%rsp), %rax /* user RFLAGS */ 739 movq %rax, (3*8)(%rdi) 740 movq (5*8)(%rsp), %rax /* user SS */ 741 movq %rax, (5*8)(%rdi) 742 movq (4*8)(%rsp), %rax /* user RSP */ 743 movq %rax, (4*8)(%rdi) 744 /* Now RAX == RSP. */ 745 746 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 747 748 /* 749 * espfix_stack[31:16] == 0. The page tables are set up such that 750 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 751 * espfix_waddr for any X. That is, there are 65536 RO aliases of 752 * the same page. Set up RSP so that RSP[31:16] contains the 753 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 754 * still points to an RO alias of the ESPFIX stack. 755 */ 756 orq PER_CPU_VAR(espfix_stack), %rax 757 758 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 759 swapgs /* to user GS */ 760 popq %rdi /* Restore user RDI */ 761 762 movq %rax, %rsp 763 UNWIND_HINT_IRET_REGS offset=8 764 765 /* 766 * At this point, we cannot write to the stack any more, but we can 767 * still read. 768 */ 769 popq %rax /* Restore user RAX */ 770 771 /* 772 * RSP now points to an ordinary IRET frame, except that the page 773 * is read-only and RSP[31:16] are preloaded with the userspace 774 * values. We can now IRET back to userspace. 775 */ 776 jmp native_irq_return_iret 777#endif 778SYM_CODE_END(common_interrupt_return) 779_ASM_NOKPROBE(common_interrupt_return) 780 781/* 782 * Reload gs selector with exception handling 783 * edi: new selector 784 * 785 * Is in entry.text as it shouldn't be instrumented. 786 */ 787SYM_FUNC_START(asm_load_gs_index) 788 FRAME_BEGIN 789 swapgs 790.Lgs_change: 791 ANNOTATE_NOENDBR // error_entry 792 movl %edi, %gs 7932: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 794 swapgs 795 FRAME_END 796 RET 797 798 /* running with kernelgs */ 799.Lbad_gs: 800 swapgs /* switch back to user gs */ 801.macro ZAP_GS 802 /* This can't be a string because the preprocessor needs to see it. */ 803 movl $__USER_DS, %eax 804 movl %eax, %gs 805.endm 806 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 807 xorl %eax, %eax 808 movl %eax, %gs 809 jmp 2b 810 811 _ASM_EXTABLE(.Lgs_change, .Lbad_gs) 812 813SYM_FUNC_END(asm_load_gs_index) 814EXPORT_SYMBOL(asm_load_gs_index) 815 816#ifdef CONFIG_XEN_PV 817/* 818 * A note on the "critical region" in our callback handler. 819 * We want to avoid stacking callback handlers due to events occurring 820 * during handling of the last event. To do this, we keep events disabled 821 * until we've done all processing. HOWEVER, we must enable events before 822 * popping the stack frame (can't be done atomically) and so it would still 823 * be possible to get enough handler activations to overflow the stack. 824 * Although unlikely, bugs of that kind are hard to track down, so we'd 825 * like to avoid the possibility. 826 * So, on entry to the handler we detect whether we interrupted an 827 * existing activation in its critical region -- if so, we pop the current 828 * activation and restart the handler using the previous one. 829 * 830 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs) 831 */ 832 __FUNC_ALIGN 833SYM_CODE_START_LOCAL_NOALIGN(exc_xen_hypervisor_callback) 834 835/* 836 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 837 * see the correct pointer to the pt_regs 838 */ 839 UNWIND_HINT_FUNC 840 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 841 UNWIND_HINT_REGS 842 843 call xen_pv_evtchn_do_upcall 844 845 jmp error_return 846SYM_CODE_END(exc_xen_hypervisor_callback) 847 848/* 849 * Hypervisor uses this for application faults while it executes. 850 * We get here for two reasons: 851 * 1. Fault while reloading DS, ES, FS or GS 852 * 2. Fault while executing IRET 853 * Category 1 we do not need to fix up as Xen has already reloaded all segment 854 * registers that could be reloaded and zeroed the others. 855 * Category 2 we fix up by killing the current process. We cannot use the 856 * normal Linux return path in this case because if we use the IRET hypercall 857 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 858 * We distinguish between categories by comparing each saved segment register 859 * with its current contents: any discrepancy means we in category 1. 860 */ 861 __FUNC_ALIGN 862SYM_CODE_START_NOALIGN(xen_failsafe_callback) 863 UNWIND_HINT_EMPTY 864 ENDBR 865 movl %ds, %ecx 866 cmpw %cx, 0x10(%rsp) 867 jne 1f 868 movl %es, %ecx 869 cmpw %cx, 0x18(%rsp) 870 jne 1f 871 movl %fs, %ecx 872 cmpw %cx, 0x20(%rsp) 873 jne 1f 874 movl %gs, %ecx 875 cmpw %cx, 0x28(%rsp) 876 jne 1f 877 /* All segments match their saved values => Category 2 (Bad IRET). */ 878 movq (%rsp), %rcx 879 movq 8(%rsp), %r11 880 addq $0x30, %rsp 881 pushq $0 /* RIP */ 882 UNWIND_HINT_IRET_REGS offset=8 883 jmp asm_exc_general_protection 8841: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 885 movq (%rsp), %rcx 886 movq 8(%rsp), %r11 887 addq $0x30, %rsp 888 UNWIND_HINT_IRET_REGS 889 pushq $-1 /* orig_ax = -1 => not a system call */ 890 PUSH_AND_CLEAR_REGS 891 ENCODE_FRAME_POINTER 892 jmp error_return 893SYM_CODE_END(xen_failsafe_callback) 894#endif /* CONFIG_XEN_PV */ 895 896/* 897 * Save all registers in pt_regs. Return GSBASE related information 898 * in EBX depending on the availability of the FSGSBASE instructions: 899 * 900 * FSGSBASE R/EBX 901 * N 0 -> SWAPGS on exit 902 * 1 -> no SWAPGS on exit 903 * 904 * Y GSBASE value at entry, must be restored in paranoid_exit 905 * 906 * R14 - old CR3 907 * R15 - old SPEC_CTRL 908 */ 909SYM_CODE_START_LOCAL(paranoid_entry) 910 UNWIND_HINT_FUNC 911 PUSH_AND_CLEAR_REGS save_ret=1 912 ENCODE_FRAME_POINTER 8 913 914 /* 915 * Always stash CR3 in %r14. This value will be restored, 916 * verbatim, at exit. Needed if paranoid_entry interrupted 917 * another entry that already switched to the user CR3 value 918 * but has not yet returned to userspace. 919 * 920 * This is also why CS (stashed in the "iret frame" by the 921 * hardware at entry) can not be used: this may be a return 922 * to kernel code, but with a user CR3 value. 923 * 924 * Switching CR3 does not depend on kernel GSBASE so it can 925 * be done before switching to the kernel GSBASE. This is 926 * required for FSGSBASE because the kernel GSBASE has to 927 * be retrieved from a kernel internal table. 928 */ 929 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 930 931 /* 932 * Handling GSBASE depends on the availability of FSGSBASE. 933 * 934 * Without FSGSBASE the kernel enforces that negative GSBASE 935 * values indicate kernel GSBASE. With FSGSBASE no assumptions 936 * can be made about the GSBASE value when entering from user 937 * space. 938 */ 939 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE 940 941 /* 942 * Read the current GSBASE and store it in %rbx unconditionally, 943 * retrieve and set the current CPUs kernel GSBASE. The stored value 944 * has to be restored in paranoid_exit unconditionally. 945 * 946 * The unconditional write to GS base below ensures that no subsequent 947 * loads based on a mispredicted GS base can happen, therefore no LFENCE 948 * is needed here. 949 */ 950 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx 951 jmp .Lparanoid_gsbase_done 952 953.Lparanoid_entry_checkgs: 954 /* EBX = 1 -> kernel GSBASE active, no restore required */ 955 movl $1, %ebx 956 957 /* 958 * The kernel-enforced convention is a negative GSBASE indicates 959 * a kernel value. No SWAPGS needed on entry and exit. 960 */ 961 movl $MSR_GS_BASE, %ecx 962 rdmsr 963 testl %edx, %edx 964 js .Lparanoid_kernel_gsbase 965 966 /* EBX = 0 -> SWAPGS required on exit */ 967 xorl %ebx, %ebx 968 swapgs 969.Lparanoid_kernel_gsbase: 970 FENCE_SWAPGS_KERNEL_ENTRY 971.Lparanoid_gsbase_done: 972 973 /* 974 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like 975 * CR3 above, keep the old value in a callee saved register. 976 */ 977 IBRS_ENTER save_reg=%r15 978 UNTRAIN_RET 979 980 RET 981SYM_CODE_END(paranoid_entry) 982 983/* 984 * "Paranoid" exit path from exception stack. This is invoked 985 * only on return from non-NMI IST interrupts that came 986 * from kernel space. 987 * 988 * We may be returning to very strange contexts (e.g. very early 989 * in syscall entry), so checking for preemption here would 990 * be complicated. Fortunately, there's no good reason to try 991 * to handle preemption here. 992 * 993 * R/EBX contains the GSBASE related information depending on the 994 * availability of the FSGSBASE instructions: 995 * 996 * FSGSBASE R/EBX 997 * N 0 -> SWAPGS on exit 998 * 1 -> no SWAPGS on exit 999 * 1000 * Y User space GSBASE, must be restored unconditionally 1001 * 1002 * R14 - old CR3 1003 * R15 - old SPEC_CTRL 1004 */ 1005SYM_CODE_START_LOCAL(paranoid_exit) 1006 UNWIND_HINT_REGS 1007 1008 /* 1009 * Must restore IBRS state before both CR3 and %GS since we need access 1010 * to the per-CPU x86_spec_ctrl_shadow variable. 1011 */ 1012 IBRS_EXIT save_reg=%r15 1013 1014 /* 1015 * The order of operations is important. RESTORE_CR3 requires 1016 * kernel GSBASE. 1017 * 1018 * NB to anyone to try to optimize this code: this code does 1019 * not execute at all for exceptions from user mode. Those 1020 * exceptions go through error_exit instead. 1021 */ 1022 RESTORE_CR3 scratch_reg=%rax save_reg=%r14 1023 1024 /* Handle the three GSBASE cases */ 1025 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE 1026 1027 /* With FSGSBASE enabled, unconditionally restore GSBASE */ 1028 wrgsbase %rbx 1029 jmp restore_regs_and_return_to_kernel 1030 1031.Lparanoid_exit_checkgs: 1032 /* On non-FSGSBASE systems, conditionally do SWAPGS */ 1033 testl %ebx, %ebx 1034 jnz restore_regs_and_return_to_kernel 1035 1036 /* We are returning to a context with user GSBASE */ 1037 swapgs 1038 jmp restore_regs_and_return_to_kernel 1039SYM_CODE_END(paranoid_exit) 1040 1041/* 1042 * Switch GS and CR3 if needed. 1043 */ 1044SYM_CODE_START_LOCAL(error_entry) 1045 UNWIND_HINT_FUNC 1046 1047 PUSH_AND_CLEAR_REGS save_ret=1 1048 ENCODE_FRAME_POINTER 8 1049 1050 testb $3, CS+8(%rsp) 1051 jz .Lerror_kernelspace 1052 1053 /* 1054 * We entered from user mode or we're pretending to have entered 1055 * from user mode due to an IRET fault. 1056 */ 1057 swapgs 1058 FENCE_SWAPGS_USER_ENTRY 1059 /* We have user CR3. Change to kernel CR3. */ 1060 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1061 IBRS_ENTER 1062 UNTRAIN_RET 1063 1064 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */ 1065.Lerror_entry_from_usermode_after_swapgs: 1066 1067 /* Put us onto the real thread stack. */ 1068 call sync_regs 1069 RET 1070 1071 /* 1072 * There are two places in the kernel that can potentially fault with 1073 * usergs. Handle them here. B stepping K8s sometimes report a 1074 * truncated RIP for IRET exceptions returning to compat mode. Check 1075 * for these here too. 1076 */ 1077.Lerror_kernelspace: 1078 leaq native_irq_return_iret(%rip), %rcx 1079 cmpq %rcx, RIP+8(%rsp) 1080 je .Lerror_bad_iret 1081 movl %ecx, %eax /* zero extend */ 1082 cmpq %rax, RIP+8(%rsp) 1083 je .Lbstep_iret 1084 cmpq $.Lgs_change, RIP+8(%rsp) 1085 jne .Lerror_entry_done_lfence 1086 1087 /* 1088 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1089 * gsbase and proceed. We'll fix up the exception and land in 1090 * .Lgs_change's error handler with kernel gsbase. 1091 */ 1092 swapgs 1093 1094 /* 1095 * Issue an LFENCE to prevent GS speculation, regardless of whether it is a 1096 * kernel or user gsbase. 1097 */ 1098.Lerror_entry_done_lfence: 1099 FENCE_SWAPGS_KERNEL_ENTRY 1100 leaq 8(%rsp), %rax /* return pt_regs pointer */ 1101 ANNOTATE_UNRET_END 1102 RET 1103 1104.Lbstep_iret: 1105 /* Fix truncated RIP */ 1106 movq %rcx, RIP+8(%rsp) 1107 /* fall through */ 1108 1109.Lerror_bad_iret: 1110 /* 1111 * We came from an IRET to user mode, so we have user 1112 * gsbase and CR3. Switch to kernel gsbase and CR3: 1113 */ 1114 swapgs 1115 FENCE_SWAPGS_USER_ENTRY 1116 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1117 IBRS_ENTER 1118 UNTRAIN_RET 1119 1120 /* 1121 * Pretend that the exception came from user mode: set up pt_regs 1122 * as if we faulted immediately after IRET. 1123 */ 1124 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */ 1125 call fixup_bad_iret 1126 mov %rax, %rdi 1127 jmp .Lerror_entry_from_usermode_after_swapgs 1128SYM_CODE_END(error_entry) 1129 1130SYM_CODE_START_LOCAL(error_return) 1131 UNWIND_HINT_REGS 1132 DEBUG_ENTRY_ASSERT_IRQS_OFF 1133 testb $3, CS(%rsp) 1134 jz restore_regs_and_return_to_kernel 1135 jmp swapgs_restore_regs_and_return_to_usermode 1136SYM_CODE_END(error_return) 1137 1138/* 1139 * Runs on exception stack. Xen PV does not go through this path at all, 1140 * so we can use real assembly here. 1141 * 1142 * Registers: 1143 * %r14: Used to save/restore the CR3 of the interrupted context 1144 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1145 */ 1146SYM_CODE_START(asm_exc_nmi) 1147 UNWIND_HINT_IRET_REGS 1148 ENDBR 1149 1150 /* 1151 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1152 * the iretq it performs will take us out of NMI context. 1153 * This means that we can have nested NMIs where the next 1154 * NMI is using the top of the stack of the previous NMI. We 1155 * can't let it execute because the nested NMI will corrupt the 1156 * stack of the previous NMI. NMI handlers are not re-entrant 1157 * anyway. 1158 * 1159 * To handle this case we do the following: 1160 * Check the a special location on the stack that contains 1161 * a variable that is set when NMIs are executing. 1162 * The interrupted task's stack is also checked to see if it 1163 * is an NMI stack. 1164 * If the variable is not set and the stack is not the NMI 1165 * stack then: 1166 * o Set the special variable on the stack 1167 * o Copy the interrupt frame into an "outermost" location on the 1168 * stack 1169 * o Copy the interrupt frame into an "iret" location on the stack 1170 * o Continue processing the NMI 1171 * If the variable is set or the previous stack is the NMI stack: 1172 * o Modify the "iret" location to jump to the repeat_nmi 1173 * o return back to the first NMI 1174 * 1175 * Now on exit of the first NMI, we first clear the stack variable 1176 * The NMI stack will tell any nested NMIs at that point that it is 1177 * nested. Then we pop the stack normally with iret, and if there was 1178 * a nested NMI that updated the copy interrupt stack frame, a 1179 * jump will be made to the repeat_nmi code that will handle the second 1180 * NMI. 1181 * 1182 * However, espfix prevents us from directly returning to userspace 1183 * with a single IRET instruction. Similarly, IRET to user mode 1184 * can fault. We therefore handle NMIs from user space like 1185 * other IST entries. 1186 */ 1187 1188 ASM_CLAC 1189 cld 1190 1191 /* Use %rdx as our temp variable throughout */ 1192 pushq %rdx 1193 1194 testb $3, CS-RIP+8(%rsp) 1195 jz .Lnmi_from_kernel 1196 1197 /* 1198 * NMI from user mode. We need to run on the thread stack, but we 1199 * can't go through the normal entry paths: NMIs are masked, and 1200 * we don't want to enable interrupts, because then we'll end 1201 * up in an awkward situation in which IRQs are on but NMIs 1202 * are off. 1203 * 1204 * We also must not push anything to the stack before switching 1205 * stacks lest we corrupt the "NMI executing" variable. 1206 */ 1207 1208 swapgs 1209 FENCE_SWAPGS_USER_ENTRY 1210 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1211 movq %rsp, %rdx 1212 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp 1213 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1214 pushq 5*8(%rdx) /* pt_regs->ss */ 1215 pushq 4*8(%rdx) /* pt_regs->rsp */ 1216 pushq 3*8(%rdx) /* pt_regs->flags */ 1217 pushq 2*8(%rdx) /* pt_regs->cs */ 1218 pushq 1*8(%rdx) /* pt_regs->rip */ 1219 UNWIND_HINT_IRET_REGS 1220 pushq $-1 /* pt_regs->orig_ax */ 1221 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1222 ENCODE_FRAME_POINTER 1223 1224 IBRS_ENTER 1225 UNTRAIN_RET 1226 1227 /* 1228 * At this point we no longer need to worry about stack damage 1229 * due to nesting -- we're on the normal thread stack and we're 1230 * done with the NMI stack. 1231 */ 1232 1233 movq %rsp, %rdi 1234 movq $-1, %rsi 1235 call exc_nmi 1236 1237 /* 1238 * Return back to user mode. We must *not* do the normal exit 1239 * work, because we don't want to enable interrupts. 1240 */ 1241 jmp swapgs_restore_regs_and_return_to_usermode 1242 1243.Lnmi_from_kernel: 1244 /* 1245 * Here's what our stack frame will look like: 1246 * +---------------------------------------------------------+ 1247 * | original SS | 1248 * | original Return RSP | 1249 * | original RFLAGS | 1250 * | original CS | 1251 * | original RIP | 1252 * +---------------------------------------------------------+ 1253 * | temp storage for rdx | 1254 * +---------------------------------------------------------+ 1255 * | "NMI executing" variable | 1256 * +---------------------------------------------------------+ 1257 * | iret SS } Copied from "outermost" frame | 1258 * | iret Return RSP } on each loop iteration; overwritten | 1259 * | iret RFLAGS } by a nested NMI to force another | 1260 * | iret CS } iteration if needed. | 1261 * | iret RIP } | 1262 * +---------------------------------------------------------+ 1263 * | outermost SS } initialized in first_nmi; | 1264 * | outermost Return RSP } will not be changed before | 1265 * | outermost RFLAGS } NMI processing is done. | 1266 * | outermost CS } Copied to "iret" frame on each | 1267 * | outermost RIP } iteration. | 1268 * +---------------------------------------------------------+ 1269 * | pt_regs | 1270 * +---------------------------------------------------------+ 1271 * 1272 * The "original" frame is used by hardware. Before re-enabling 1273 * NMIs, we need to be done with it, and we need to leave enough 1274 * space for the asm code here. 1275 * 1276 * We return by executing IRET while RSP points to the "iret" frame. 1277 * That will either return for real or it will loop back into NMI 1278 * processing. 1279 * 1280 * The "outermost" frame is copied to the "iret" frame on each 1281 * iteration of the loop, so each iteration starts with the "iret" 1282 * frame pointing to the final return target. 1283 */ 1284 1285 /* 1286 * Determine whether we're a nested NMI. 1287 * 1288 * If we interrupted kernel code between repeat_nmi and 1289 * end_repeat_nmi, then we are a nested NMI. We must not 1290 * modify the "iret" frame because it's being written by 1291 * the outer NMI. That's okay; the outer NMI handler is 1292 * about to about to call exc_nmi() anyway, so we can just 1293 * resume the outer NMI. 1294 */ 1295 1296 movq $repeat_nmi, %rdx 1297 cmpq 8(%rsp), %rdx 1298 ja 1f 1299 movq $end_repeat_nmi, %rdx 1300 cmpq 8(%rsp), %rdx 1301 ja nested_nmi_out 13021: 1303 1304 /* 1305 * Now check "NMI executing". If it's set, then we're nested. 1306 * This will not detect if we interrupted an outer NMI just 1307 * before IRET. 1308 */ 1309 cmpl $1, -8(%rsp) 1310 je nested_nmi 1311 1312 /* 1313 * Now test if the previous stack was an NMI stack. This covers 1314 * the case where we interrupt an outer NMI after it clears 1315 * "NMI executing" but before IRET. We need to be careful, though: 1316 * there is one case in which RSP could point to the NMI stack 1317 * despite there being no NMI active: naughty userspace controls 1318 * RSP at the very beginning of the SYSCALL targets. We can 1319 * pull a fast one on naughty userspace, though: we program 1320 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1321 * if it controls the kernel's RSP. We set DF before we clear 1322 * "NMI executing". 1323 */ 1324 lea 6*8(%rsp), %rdx 1325 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1326 cmpq %rdx, 4*8(%rsp) 1327 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1328 ja first_nmi 1329 1330 subq $EXCEPTION_STKSZ, %rdx 1331 cmpq %rdx, 4*8(%rsp) 1332 /* If it is below the NMI stack, it is a normal NMI */ 1333 jb first_nmi 1334 1335 /* Ah, it is within the NMI stack. */ 1336 1337 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1338 jz first_nmi /* RSP was user controlled. */ 1339 1340 /* This is a nested NMI. */ 1341 1342nested_nmi: 1343 /* 1344 * Modify the "iret" frame to point to repeat_nmi, forcing another 1345 * iteration of NMI handling. 1346 */ 1347 subq $8, %rsp 1348 leaq -10*8(%rsp), %rdx 1349 pushq $__KERNEL_DS 1350 pushq %rdx 1351 pushfq 1352 pushq $__KERNEL_CS 1353 pushq $repeat_nmi 1354 1355 /* Put stack back */ 1356 addq $(6*8), %rsp 1357 1358nested_nmi_out: 1359 popq %rdx 1360 1361 /* We are returning to kernel mode, so this cannot result in a fault. */ 1362 iretq 1363 1364first_nmi: 1365 /* Restore rdx. */ 1366 movq (%rsp), %rdx 1367 1368 /* Make room for "NMI executing". */ 1369 pushq $0 1370 1371 /* Leave room for the "iret" frame */ 1372 subq $(5*8), %rsp 1373 1374 /* Copy the "original" frame to the "outermost" frame */ 1375 .rept 5 1376 pushq 11*8(%rsp) 1377 .endr 1378 UNWIND_HINT_IRET_REGS 1379 1380 /* Everything up to here is safe from nested NMIs */ 1381 1382#ifdef CONFIG_DEBUG_ENTRY 1383 /* 1384 * For ease of testing, unmask NMIs right away. Disabled by 1385 * default because IRET is very expensive. 1386 */ 1387 pushq $0 /* SS */ 1388 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1389 addq $8, (%rsp) /* Fix up RSP */ 1390 pushfq /* RFLAGS */ 1391 pushq $__KERNEL_CS /* CS */ 1392 pushq $1f /* RIP */ 1393 iretq /* continues at repeat_nmi below */ 1394 UNWIND_HINT_IRET_REGS 13951: 1396#endif 1397 1398repeat_nmi: 1399 ANNOTATE_NOENDBR // this code 1400 /* 1401 * If there was a nested NMI, the first NMI's iret will return 1402 * here. But NMIs are still enabled and we can take another 1403 * nested NMI. The nested NMI checks the interrupted RIP to see 1404 * if it is between repeat_nmi and end_repeat_nmi, and if so 1405 * it will just return, as we are about to repeat an NMI anyway. 1406 * This makes it safe to copy to the stack frame that a nested 1407 * NMI will update. 1408 * 1409 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1410 * we're repeating an NMI, gsbase has the same value that it had on 1411 * the first iteration. paranoid_entry will load the kernel 1412 * gsbase if needed before we call exc_nmi(). "NMI executing" 1413 * is zero. 1414 */ 1415 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1416 1417 /* 1418 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1419 * here must not modify the "iret" frame while we're writing to 1420 * it or it will end up containing garbage. 1421 */ 1422 addq $(10*8), %rsp 1423 .rept 5 1424 pushq -6*8(%rsp) 1425 .endr 1426 subq $(5*8), %rsp 1427end_repeat_nmi: 1428 ANNOTATE_NOENDBR // this code 1429 1430 /* 1431 * Everything below this point can be preempted by a nested NMI. 1432 * If this happens, then the inner NMI will change the "iret" 1433 * frame to point back to repeat_nmi. 1434 */ 1435 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1436 1437 /* 1438 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1439 * as we should not be calling schedule in NMI context. 1440 * Even with normal interrupts enabled. An NMI should not be 1441 * setting NEED_RESCHED or anything that normal interrupts and 1442 * exceptions might do. 1443 */ 1444 call paranoid_entry 1445 UNWIND_HINT_REGS 1446 1447 movq %rsp, %rdi 1448 movq $-1, %rsi 1449 call exc_nmi 1450 1451 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */ 1452 IBRS_EXIT save_reg=%r15 1453 1454 /* Always restore stashed CR3 value (see paranoid_entry) */ 1455 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1456 1457 /* 1458 * The above invocation of paranoid_entry stored the GSBASE 1459 * related information in R/EBX depending on the availability 1460 * of FSGSBASE. 1461 * 1462 * If FSGSBASE is enabled, restore the saved GSBASE value 1463 * unconditionally, otherwise take the conditional SWAPGS path. 1464 */ 1465 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE 1466 1467 wrgsbase %rbx 1468 jmp nmi_restore 1469 1470nmi_no_fsgsbase: 1471 /* EBX == 0 -> invoke SWAPGS */ 1472 testl %ebx, %ebx 1473 jnz nmi_restore 1474 1475nmi_swapgs: 1476 swapgs 1477 1478nmi_restore: 1479 POP_REGS 1480 1481 /* 1482 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1483 * at the "iret" frame. 1484 */ 1485 addq $6*8, %rsp 1486 1487 /* 1488 * Clear "NMI executing". Set DF first so that we can easily 1489 * distinguish the remaining code between here and IRET from 1490 * the SYSCALL entry and exit paths. 1491 * 1492 * We arguably should just inspect RIP instead, but I (Andy) wrote 1493 * this code when I had the misapprehension that Xen PV supported 1494 * NMIs, and Xen PV would break that approach. 1495 */ 1496 std 1497 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1498 1499 /* 1500 * iretq reads the "iret" frame and exits the NMI stack in a 1501 * single instruction. We are returning to kernel mode, so this 1502 * cannot result in a fault. Similarly, we don't need to worry 1503 * about espfix64 on the way back to kernel mode. 1504 */ 1505 iretq 1506SYM_CODE_END(asm_exc_nmi) 1507 1508#ifndef CONFIG_IA32_EMULATION 1509/* 1510 * This handles SYSCALL from 32-bit code. There is no way to program 1511 * MSRs to fully disable 32-bit SYSCALL. 1512 */ 1513SYM_CODE_START(ignore_sysret) 1514 UNWIND_HINT_EMPTY 1515 ENDBR 1516 mov $-ENOSYS, %eax 1517 sysretl 1518SYM_CODE_END(ignore_sysret) 1519#endif 1520 1521.pushsection .text, "ax" 1522 __FUNC_ALIGN 1523SYM_CODE_START_NOALIGN(rewind_stack_and_make_dead) 1524 UNWIND_HINT_FUNC 1525 /* Prevent any naive code from trying to unwind to our caller. */ 1526 xorl %ebp, %ebp 1527 1528 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rax 1529 leaq -PTREGS_SIZE(%rax), %rsp 1530 UNWIND_HINT_REGS 1531 1532 call make_task_dead 1533SYM_CODE_END(rewind_stack_and_make_dead) 1534.popsection 1535