1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 * Copyright (C) 2017 SiFive 5 */ 6 7 #include <linux/mm.h> 8 #include <asm/tlbflush.h> 9 #include <asm/cacheflush.h> 10 11 /* 12 * When necessary, performs a deferred icache flush for the given MM context, 13 * on the local CPU. RISC-V has no direct mechanism for instruction cache 14 * shoot downs, so instead we send an IPI that informs the remote harts they 15 * need to flush their local instruction caches. To avoid pathologically slow 16 * behavior in a common case (a bunch of single-hart processes on a many-hart 17 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently 18 * executing a MM context and instead schedule a deferred local instruction 19 * cache flush to be performed before execution resumes on each hart. This 20 * actually performs that local instruction cache flush, which implicitly only 21 * refers to the current hart. 22 */ 23 static inline void flush_icache_deferred(struct mm_struct *mm) 24 { 25 #ifdef CONFIG_SMP 26 unsigned int cpu = smp_processor_id(); 27 cpumask_t *mask = &mm->context.icache_stale_mask; 28 29 if (cpumask_test_cpu(cpu, mask)) { 30 cpumask_clear_cpu(cpu, mask); 31 /* 32 * Ensure the remote hart's writes are visible to this hart. 33 * This pairs with a barrier in flush_icache_mm. 34 */ 35 smp_mb(); 36 local_flush_icache_all(); 37 } 38 39 #endif 40 } 41 42 void switch_mm(struct mm_struct *prev, struct mm_struct *next, 43 struct task_struct *task) 44 { 45 unsigned int cpu; 46 47 if (unlikely(prev == next)) 48 return; 49 50 /* 51 * Mark the current MM context as inactive, and the next as 52 * active. This is at least used by the icache flushing 53 * routines in order to determine who should be flushed. 54 */ 55 cpu = smp_processor_id(); 56 57 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 58 cpumask_set_cpu(cpu, mm_cpumask(next)); 59 60 csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE); 61 local_flush_tlb_all(); 62 63 flush_icache_deferred(next); 64 } 65