1a8fed1bcSAleksa Paunovic /* SPDX-License-Identifier: GPL-2.0-only */ 2a8fed1bcSAleksa Paunovic /* 3a8fed1bcSAleksa Paunovic * Copyright (C) 2025 MIPS. 4a8fed1bcSAleksa Paunovic */ 5a8fed1bcSAleksa Paunovic 6a8fed1bcSAleksa Paunovic #ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H 7a8fed1bcSAleksa Paunovic #define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H 8a8fed1bcSAleksa Paunovic 9a8fed1bcSAleksa Paunovic #include <linux/types.h> 10a8fed1bcSAleksa Paunovic 11a8fed1bcSAleksa Paunovic #define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL 0 12a8fed1bcSAleksa Paunovic 13a8fed1bcSAleksa Paunovic #ifndef __ASSEMBLER__ 14a8fed1bcSAleksa Paunovic struct riscv_isa_vendor_ext_data_list; 15a8fed1bcSAleksa Paunovic extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips; 16a8fed1bcSAleksa Paunovic #endif 17a8fed1bcSAleksa Paunovic 18*1d4ce63eSAleksa Paunovic /* Extension specific instructions */ 19*1d4ce63eSAleksa Paunovic 20*1d4ce63eSAleksa Paunovic /* 21*1d4ce63eSAleksa Paunovic * All of the xmipsexectl extension instructions are 22*1d4ce63eSAleksa Paunovic * ‘hint’ encodings of the SLLI instruction, 23*1d4ce63eSAleksa Paunovic * with rd = 0, rs1 = 0 and imm = 1 for IHB, imm = 3 for EHB, 24*1d4ce63eSAleksa Paunovic * and imm = 5 for PAUSE. 25*1d4ce63eSAleksa Paunovic * MIPS.PAUSE is an alternative opcode which is implemented to have the 26*1d4ce63eSAleksa Paunovic * same behavior as PAUSE on some MIPS RISCV cores. 27*1d4ce63eSAleksa Paunovic * MIPS.EHB clears all execution hazards before allowing 28*1d4ce63eSAleksa Paunovic * any subsequent instructions to execute. 29*1d4ce63eSAleksa Paunovic * MIPS.IHB clears all instruction hazards before 30*1d4ce63eSAleksa Paunovic * allowing any subsequent instructions to fetch. 31*1d4ce63eSAleksa Paunovic */ 32*1d4ce63eSAleksa Paunovic 33*1d4ce63eSAleksa Paunovic #define MIPS_PAUSE ".4byte 0x00501013\n\t" 34*1d4ce63eSAleksa Paunovic #define MIPS_EHB ".4byte 0x00301013\n\t" 35*1d4ce63eSAleksa Paunovic #define MIPS_IHB ".4byte 0x00101013\n\t" 36*1d4ce63eSAleksa Paunovic 37a8fed1bcSAleksa Paunovic #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H 38