1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2025 MIPS. 4 */ 5 6 #ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H 7 #define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H 8 9 #include <linux/types.h> 10 11 #define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL 0 12 13 #ifndef __ASSEMBLER__ 14 struct riscv_isa_vendor_ext_data_list; 15 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips; 16 #endif 17 18 /* Extension specific instructions */ 19 20 /* 21 * All of the xmipsexectl extension instructions are 22 * ‘hint’ encodings of the SLLI instruction, 23 * with rd = 0, rs1 = 0 and imm = 1 for IHB, imm = 3 for EHB, 24 * and imm = 5 for PAUSE. 25 * MIPS.PAUSE is an alternative opcode which is implemented to have the 26 * same behavior as PAUSE on some MIPS RISCV cores. 27 * MIPS.EHB clears all execution hazards before allowing 28 * any subsequent instructions to execute. 29 * MIPS.IHB clears all instruction hazards before 30 * allowing any subsequent instructions to fetch. 31 */ 32 33 #define MIPS_PAUSE ".4byte 0x00501013\n\t" 34 #define MIPS_EHB ".4byte 0x00301013\n\t" 35 #define MIPS_IHB ".4byte 0x00101013\n\t" 36 37 #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H 38