1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd 4 * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/dts-v1/; 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 model = "SpacemiT K3"; 15 compatible = "spacemit,k3"; 16 17 cpus: cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 timebase-frequency = <24000000>; 21 22 cpu_0: cpu@0 { 23 compatible = "spacemit,x100", "riscv"; 24 device_type = "cpu"; 25 reg = <0>; 26 riscv,isa-base = "rv64i"; 27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 28 "sha", "shcounterenw", "shgatpa", "shtvala", 29 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 30 "smstateen", "ssaia", "ssccptr", "sscofpmf", 31 "sscounterenw", "ssnpm", "ssstateen", "sstc", 32 "sstvala", "sstvecd", "ssu64xl", "svade", 33 "svinval", "svnapot", "svpbmt", "za64rs", 34 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 35 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 36 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 37 "ziccamoa", "ziccif", "zicclsm", "zicntr", 38 "zicond", "zicsr", "zifencei", "zihintntl", 39 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 40 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 41 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 42 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 43 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 44 riscv,cbom-block-size = <64>; 45 riscv,cbop-block-size = <64>; 46 riscv,cboz-block-size = <64>; 47 i-cache-block-size = <64>; 48 i-cache-size = <65536>; 49 i-cache-sets = <256>; 50 d-cache-block-size = <64>; 51 d-cache-size = <65536>; 52 d-cache-sets = <256>; 53 next-level-cache = <&l2_cache0>; 54 mmu-type = "riscv,sv39"; 55 56 cpu0_intc: interrupt-controller { 57 compatible = "riscv,cpu-intc"; 58 #interrupt-cells = <1>; 59 interrupt-controller; 60 }; 61 }; 62 63 cpu_1: cpu@1 { 64 compatible = "spacemit,x100", "riscv"; 65 device_type = "cpu"; 66 reg = <1>; 67 riscv,isa-base = "rv64i"; 68 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 69 "sha", "shcounterenw", "shgatpa", "shtvala", 70 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 71 "smstateen", "ssaia", "ssccptr", "sscofpmf", 72 "sscounterenw", "ssnpm", "ssstateen", "sstc", 73 "sstvala", "sstvecd", "ssu64xl", "svade", 74 "svinval", "svnapot", "svpbmt", "za64rs", 75 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 76 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 77 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 78 "ziccamoa", "ziccif", "zicclsm", "zicntr", 79 "zicond", "zicsr", "zifencei", "zihintntl", 80 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 81 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 82 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 83 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 84 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 85 riscv,cbom-block-size = <64>; 86 riscv,cbop-block-size = <64>; 87 riscv,cboz-block-size = <64>; 88 i-cache-block-size = <64>; 89 i-cache-size = <65536>; 90 i-cache-sets = <256>; 91 d-cache-block-size = <64>; 92 d-cache-size = <65536>; 93 d-cache-sets = <256>; 94 next-level-cache = <&l2_cache0>; 95 mmu-type = "riscv,sv39"; 96 97 cpu1_intc: interrupt-controller { 98 compatible = "riscv,cpu-intc"; 99 #interrupt-cells = <1>; 100 interrupt-controller; 101 }; 102 }; 103 104 cpu_2: cpu@2 { 105 compatible = "spacemit,x100", "riscv"; 106 device_type = "cpu"; 107 reg = <2>; 108 riscv,isa-base = "rv64i"; 109 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 110 "sha", "shcounterenw", "shgatpa", "shtvala", 111 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 112 "smstateen", "ssaia", "ssccptr", "sscofpmf", 113 "sscounterenw", "ssnpm", "ssstateen", "sstc", 114 "sstvala", "sstvecd", "ssu64xl", "svade", 115 "svinval", "svnapot", "svpbmt", "za64rs", 116 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 117 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 118 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 119 "ziccamoa", "ziccif", "zicclsm", "zicntr", 120 "zicond", "zicsr", "zifencei", "zihintntl", 121 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 122 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 123 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 124 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 125 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 126 riscv,cbom-block-size = <64>; 127 riscv,cbop-block-size = <64>; 128 riscv,cboz-block-size = <64>; 129 i-cache-block-size = <64>; 130 i-cache-size = <65536>; 131 i-cache-sets = <256>; 132 d-cache-block-size = <64>; 133 d-cache-size = <65536>; 134 d-cache-sets = <256>; 135 next-level-cache = <&l2_cache0>; 136 mmu-type = "riscv,sv39"; 137 138 cpu2_intc: interrupt-controller { 139 compatible = "riscv,cpu-intc"; 140 #interrupt-cells = <1>; 141 interrupt-controller; 142 }; 143 }; 144 145 cpu_3: cpu@3 { 146 compatible = "spacemit,x100", "riscv"; 147 device_type = "cpu"; 148 reg = <3>; 149 riscv,isa-base = "rv64i"; 150 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 151 "sha", "shcounterenw", "shgatpa", "shtvala", 152 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 153 "smstateen", "ssaia", "ssccptr", "sscofpmf", 154 "sscounterenw", "ssnpm", "ssstateen", "sstc", 155 "sstvala", "sstvecd", "ssu64xl", "svade", 156 "svinval", "svnapot", "svpbmt", "za64rs", 157 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 158 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 159 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 160 "ziccamoa", "ziccif", "zicclsm", "zicntr", 161 "zicond", "zicsr", "zifencei", "zihintntl", 162 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 163 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 164 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 165 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 166 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 167 riscv,cbom-block-size = <64>; 168 riscv,cbop-block-size = <64>; 169 riscv,cboz-block-size = <64>; 170 i-cache-block-size = <64>; 171 i-cache-size = <65536>; 172 i-cache-sets = <256>; 173 d-cache-block-size = <64>; 174 d-cache-size = <65536>; 175 d-cache-sets = <256>; 176 next-level-cache = <&l2_cache0>; 177 mmu-type = "riscv,sv39"; 178 179 cpu3_intc: interrupt-controller { 180 compatible = "riscv,cpu-intc"; 181 #interrupt-cells = <1>; 182 interrupt-controller; 183 }; 184 }; 185 186 cpu_4: cpu@4 { 187 compatible = "spacemit,x100", "riscv"; 188 device_type = "cpu"; 189 reg = <4>; 190 riscv,isa-base = "rv64i"; 191 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 192 "sha", "shcounterenw", "shgatpa", "shtvala", 193 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 194 "smstateen", "ssaia", "ssccptr", "sscofpmf", 195 "sscounterenw", "ssnpm", "ssstateen", "sstc", 196 "sstvala", "sstvecd", "ssu64xl", "svade", 197 "svinval", "svnapot", "svpbmt", "za64rs", 198 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 199 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 200 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 201 "ziccamoa", "ziccif", "zicclsm", "zicntr", 202 "zicond", "zicsr", "zifencei", "zihintntl", 203 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 204 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 205 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 206 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 207 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 208 riscv,cbom-block-size = <64>; 209 riscv,cbop-block-size = <64>; 210 riscv,cboz-block-size = <64>; 211 i-cache-block-size = <64>; 212 i-cache-size = <65536>; 213 i-cache-sets = <256>; 214 d-cache-block-size = <64>; 215 d-cache-size = <65536>; 216 d-cache-sets = <256>; 217 next-level-cache = <&l2_cache1>; 218 mmu-type = "riscv,sv39"; 219 220 cpu4_intc: interrupt-controller { 221 compatible = "riscv,cpu-intc"; 222 #interrupt-cells = <1>; 223 interrupt-controller; 224 }; 225 }; 226 227 cpu_5: cpu@5 { 228 compatible = "spacemit,x100", "riscv"; 229 device_type = "cpu"; 230 reg = <5>; 231 riscv,isa-base = "rv64i"; 232 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 233 "sha", "shcounterenw", "shgatpa", "shtvala", 234 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 235 "smstateen", "ssaia", "ssccptr", "sscofpmf", 236 "sscounterenw", "ssnpm", "ssstateen", "sstc", 237 "sstvala", "sstvecd", "ssu64xl", "svade", 238 "svinval", "svnapot", "svpbmt", "za64rs", 239 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 240 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 241 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 242 "ziccamoa", "ziccif", "zicclsm", "zicntr", 243 "zicond", "zicsr", "zifencei", "zihintntl", 244 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 245 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 246 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 247 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 248 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 249 riscv,cbom-block-size = <64>; 250 riscv,cbop-block-size = <64>; 251 riscv,cboz-block-size = <64>; 252 i-cache-block-size = <64>; 253 i-cache-size = <65536>; 254 i-cache-sets = <256>; 255 d-cache-block-size = <64>; 256 d-cache-size = <65536>; 257 d-cache-sets = <256>; 258 next-level-cache = <&l2_cache1>; 259 mmu-type = "riscv,sv39"; 260 261 cpu5_intc: interrupt-controller { 262 compatible = "riscv,cpu-intc"; 263 #interrupt-cells = <1>; 264 interrupt-controller; 265 }; 266 }; 267 268 cpu_6: cpu@6 { 269 compatible = "spacemit,x100", "riscv"; 270 device_type = "cpu"; 271 reg = <6>; 272 riscv,isa-base = "rv64i"; 273 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 274 "sha", "shcounterenw", "shgatpa", "shtvala", 275 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 276 "smstateen", "ssaia", "ssccptr", "sscofpmf", 277 "sscounterenw", "ssnpm", "ssstateen", "sstc", 278 "sstvala", "sstvecd", "ssu64xl", "svade", 279 "svinval", "svnapot", "svpbmt", "za64rs", 280 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 281 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 282 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 283 "ziccamoa", "ziccif", "zicclsm", "zicntr", 284 "zicond", "zicsr", "zifencei", "zihintntl", 285 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 286 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 287 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 288 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 289 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 290 riscv,cbom-block-size = <64>; 291 riscv,cbop-block-size = <64>; 292 riscv,cboz-block-size = <64>; 293 i-cache-block-size = <64>; 294 i-cache-size = <65536>; 295 i-cache-sets = <256>; 296 d-cache-block-size = <64>; 297 d-cache-size = <65536>; 298 d-cache-sets = <256>; 299 next-level-cache = <&l2_cache1>; 300 mmu-type = "riscv,sv39"; 301 302 cpu6_intc: interrupt-controller { 303 compatible = "riscv,cpu-intc"; 304 #interrupt-cells = <1>; 305 interrupt-controller; 306 }; 307 }; 308 309 cpu_7: cpu@7 { 310 compatible = "spacemit,x100", "riscv"; 311 device_type = "cpu"; 312 reg = <7>; 313 riscv,isa-base = "rv64i"; 314 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 315 "sha", "shcounterenw", "shgatpa", "shtvala", 316 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 317 "smstateen", "ssaia", "ssccptr", "sscofpmf", 318 "sscounterenw", "ssnpm", "ssstateen", "sstc", 319 "sstvala", "sstvecd", "ssu64xl", "svade", 320 "svinval", "svnapot", "svpbmt", "za64rs", 321 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 322 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 323 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 324 "ziccamoa", "ziccif", "zicclsm", "zicntr", 325 "zicond", "zicsr", "zifencei", "zihintntl", 326 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 327 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 328 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 329 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 330 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 331 riscv,cbom-block-size = <64>; 332 riscv,cbop-block-size = <64>; 333 riscv,cboz-block-size = <64>; 334 i-cache-block-size = <64>; 335 i-cache-size = <65536>; 336 i-cache-sets = <256>; 337 d-cache-block-size = <64>; 338 d-cache-size = <65536>; 339 d-cache-sets = <256>; 340 next-level-cache = <&l2_cache1>; 341 mmu-type = "riscv,sv39"; 342 343 cpu7_intc: interrupt-controller { 344 compatible = "riscv,cpu-intc"; 345 #interrupt-cells = <1>; 346 interrupt-controller; 347 }; 348 }; 349 350 l2_cache0: cache-controller-0 { 351 compatible = "cache"; 352 cache-block-size = <64>; 353 cache-level = <2>; 354 cache-size = <4194304>; 355 cache-sets = <4096>; 356 cache-unified; 357 }; 358 359 l2_cache1: cache-controller-1 { 360 compatible = "cache"; 361 cache-block-size = <64>; 362 cache-level = <2>; 363 cache-size = <4194304>; 364 cache-sets = <4096>; 365 cache-unified; 366 }; 367 368 cpu-map { 369 cluster0 { 370 core0 { 371 cpu = <&cpu_0>; 372 }; 373 core1 { 374 cpu = <&cpu_1>; 375 }; 376 core2 { 377 cpu = <&cpu_2>; 378 }; 379 core3 { 380 cpu = <&cpu_3>; 381 }; 382 }; 383 384 cluster1 { 385 core0 { 386 cpu = <&cpu_4>; 387 }; 388 core1 { 389 cpu = <&cpu_5>; 390 }; 391 core2 { 392 cpu = <&cpu_6>; 393 }; 394 core3 { 395 cpu = <&cpu_7>; 396 }; 397 }; 398 }; 399 }; 400 401 soc: soc { 402 compatible = "simple-bus"; 403 interrupt-parent = <&saplic>; 404 #address-cells = <2>; 405 #size-cells = <2>; 406 dma-noncoherent; 407 ranges; 408 409 uart0: serial@d4017000 { 410 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 411 reg = <0x0 0xd4017000 0x0 0x100>; 412 reg-shift = <2>; 413 reg-io-width = <4>; 414 clock-frequency = <14700000>; 415 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; 416 status = "disabled"; 417 }; 418 419 uart2: serial@d4017100 { 420 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 421 reg = <0x0 0xd4017100 0x0 0x100>; 422 reg-shift = <2>; 423 reg-io-width = <4>; 424 clock-frequency = <14700000>; 425 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 426 status = "disabled"; 427 }; 428 429 uart3: serial@d4017200 { 430 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 431 reg = <0x0 0xd4017200 0x0 0x100>; 432 reg-shift = <2>; 433 reg-io-width = <4>; 434 clock-frequency = <14700000>; 435 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; 436 status = "disabled"; 437 }; 438 439 uart4: serial@d4017300 { 440 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 441 reg = <0x0 0xd4017300 0x0 0x100>; 442 reg-shift = <2>; 443 reg-io-width = <4>; 444 clock-frequency = <14700000>; 445 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; 446 status = "disabled"; 447 }; 448 449 uart5: serial@d4017400 { 450 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 451 reg = <0x0 0xd4017400 0x0 0x100>; 452 reg-shift = <2>; 453 reg-io-width = <4>; 454 clock-frequency = <14700000>; 455 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; 456 status = "disabled"; 457 }; 458 459 uart6: serial@d4017500 { 460 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 461 reg = <0x0 0xd4017500 0x0 0x100>; 462 reg-shift = <2>; 463 reg-io-width = <4>; 464 clock-frequency = <14700000>; 465 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 466 status = "disabled"; 467 }; 468 469 uart7: serial@d4017600 { 470 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 471 reg = <0x0 0xd4017600 0x0 0x100>; 472 reg-shift = <2>; 473 reg-io-width = <4>; 474 clock-frequency = <14700000>; 475 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; 476 status = "disabled"; 477 }; 478 479 uart8: serial@d4017700 { 480 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 481 reg = <0x0 0xd4017700 0x0 0x100>; 482 reg-shift = <2>; 483 reg-io-width = <4>; 484 clock-frequency = <14700000>; 485 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; 486 status = "disabled"; 487 }; 488 489 uart9: serial@d4017800 { 490 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 491 reg = <0x0 0xd4017800 0x0 0x100>; 492 reg-shift = <2>; 493 reg-io-width = <4>; 494 clock-frequency = <14700000>; 495 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; 496 status = "disabled"; 497 }; 498 499 uart10: serial@d401f000 { 500 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 501 reg = <0x0 0xd401f000 0x0 0x100>; 502 reg-shift = <2>; 503 reg-io-width = <4>; 504 clock-frequency = <14700000>; 505 interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; 506 status = "disabled"; 507 }; 508 509 simsic: interrupt-controller@e0400000 { 510 compatible = "spacemit,k3-imsics", "riscv,imsics"; 511 reg = <0x0 0xe0400000 0x0 0x200000>; 512 #interrupt-cells = <0>; 513 #msi-cells = <0>; 514 interrupt-controller; 515 interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, 516 <&cpu2_intc 9>, <&cpu3_intc 9>, 517 <&cpu4_intc 9>, <&cpu5_intc 9>, 518 <&cpu6_intc 9>, <&cpu7_intc 9>; 519 msi-controller; 520 riscv,guest-index-bits = <6>; 521 riscv,hart-index-bits = <4>; 522 riscv,num-guest-ids = <511>; 523 riscv,num-ids = <511>; 524 }; 525 526 saplic: interrupt-controller@e0804000 { 527 compatible = "spacemit,k3-aplic", "riscv,aplic"; 528 reg = <0x0 0xe0804000 0x0 0x4000>; 529 #interrupt-cells = <2>; 530 interrupt-controller; 531 msi-parent = <&simsic>; 532 riscv,num-sources = <512>; 533 }; 534 535 clint: timer@e081c000 { 536 compatible = "spacemit,k3-clint", "sifive,clint0"; 537 reg = <0x0 0xe081c000 0x0 0x4000>; 538 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 539 <&cpu1_intc 3>, <&cpu1_intc 7>, 540 <&cpu2_intc 3>, <&cpu2_intc 7>, 541 <&cpu3_intc 3>, <&cpu3_intc 7>, 542 <&cpu4_intc 3>, <&cpu4_intc 7>, 543 <&cpu5_intc 3>, <&cpu5_intc 7>, 544 <&cpu6_intc 3>, <&cpu6_intc 7>, 545 <&cpu7_intc 3>, <&cpu7_intc 7>; 546 }; 547 548 mimsic: interrupt-controller@f1000000 { 549 compatible = "spacemit,k3-imsics", "riscv,imsics"; 550 reg = <0x0 0xf1000000 0x0 0x10000>; 551 #interrupt-cells = <0>; 552 #msi-cells = <0>; 553 interrupt-controller; 554 interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, 555 <&cpu2_intc 11>, <&cpu3_intc 11>, 556 <&cpu4_intc 11>, <&cpu5_intc 11>, 557 <&cpu6_intc 11>, <&cpu7_intc 11>; 558 msi-controller; 559 riscv,guest-index-bits = <6>; 560 riscv,hart-index-bits = <4>; 561 riscv,num-guest-ids = <511>; 562 riscv,num-ids = <511>; 563 status = "reserved"; 564 }; 565 566 maplic: interrupt-controller@f1800000 { 567 compatible = "spacemit,k3-aplic", "riscv,aplic"; 568 reg = <0x0 0xf1800000 0x0 0x4000>; 569 #interrupt-cells = <2>; 570 interrupt-controller; 571 msi-parent = <&mimsic>; 572 riscv,children = <&saplic>; 573 riscv,delegation = <&saplic 1 512>; 574 riscv,num-sources = <512>; 575 status = "reserved"; 576 }; 577 }; 578}; 579