1*63e572b1SMichael Opdenacker// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*63e572b1SMichael Opdenacker/* 3*63e572b1SMichael Opdenacker * Copyright (C) 2025 Michael Opdenacker <michael.opdenacker@rootcommit.com> 4*63e572b1SMichael Opdenacker */ 5*63e572b1SMichael Opdenacker 6*63e572b1SMichael Opdenacker/dts-v1/; 7*63e572b1SMichael Opdenacker 8*63e572b1SMichael Opdenacker#include "k1.dtsi" 9*63e572b1SMichael Opdenacker#include "k1-pinctrl.dtsi" 10*63e572b1SMichael Opdenacker 11*63e572b1SMichael Opdenacker/ { 12*63e572b1SMichael Opdenacker model = "OrangePi R2S"; 13*63e572b1SMichael Opdenacker compatible = "xunlong,orangepi-r2s", "spacemit,k1"; 14*63e572b1SMichael Opdenacker 15*63e572b1SMichael Opdenacker aliases { 16*63e572b1SMichael Opdenacker serial0 = &uart0; 17*63e572b1SMichael Opdenacker ethernet0 = ð0; 18*63e572b1SMichael Opdenacker ethernet1 = ð1; 19*63e572b1SMichael Opdenacker }; 20*63e572b1SMichael Opdenacker 21*63e572b1SMichael Opdenacker chosen { 22*63e572b1SMichael Opdenacker stdout-path = "serial0"; 23*63e572b1SMichael Opdenacker }; 24*63e572b1SMichael Opdenacker}; 25*63e572b1SMichael Opdenacker 26*63e572b1SMichael Opdenacker&emmc { 27*63e572b1SMichael Opdenacker bus-width = <8>; 28*63e572b1SMichael Opdenacker mmc-hs400-1_8v; 29*63e572b1SMichael Opdenacker mmc-hs400-enhanced-strobe; 30*63e572b1SMichael Opdenacker non-removable; 31*63e572b1SMichael Opdenacker no-sd; 32*63e572b1SMichael Opdenacker no-sdio; 33*63e572b1SMichael Opdenacker status = "okay"; 34*63e572b1SMichael Opdenacker}; 35*63e572b1SMichael Opdenacker 36*63e572b1SMichael Opdenackerð0 { 37*63e572b1SMichael Opdenacker phy-handle = <&rgmii0>; 38*63e572b1SMichael Opdenacker phy-mode = "rgmii-id"; 39*63e572b1SMichael Opdenacker pinctrl-names = "default"; 40*63e572b1SMichael Opdenacker pinctrl-0 = <&gmac0_cfg>; 41*63e572b1SMichael Opdenacker rx-internal-delay-ps = <0>; 42*63e572b1SMichael Opdenacker tx-internal-delay-ps = <0>; 43*63e572b1SMichael Opdenacker status = "okay"; 44*63e572b1SMichael Opdenacker 45*63e572b1SMichael Opdenacker mdio-bus { 46*63e572b1SMichael Opdenacker #address-cells = <0x1>; 47*63e572b1SMichael Opdenacker #size-cells = <0x0>; 48*63e572b1SMichael Opdenacker 49*63e572b1SMichael Opdenacker reset-gpios = <&gpio K1_GPIO(110) GPIO_ACTIVE_LOW>; 50*63e572b1SMichael Opdenacker reset-delay-us = <10000>; 51*63e572b1SMichael Opdenacker reset-post-delay-us = <100000>; 52*63e572b1SMichael Opdenacker 53*63e572b1SMichael Opdenacker rgmii0: phy@1 { 54*63e572b1SMichael Opdenacker reg = <0x1>; 55*63e572b1SMichael Opdenacker }; 56*63e572b1SMichael Opdenacker }; 57*63e572b1SMichael Opdenacker}; 58*63e572b1SMichael Opdenacker 59*63e572b1SMichael Opdenackerð1 { 60*63e572b1SMichael Opdenacker phy-handle = <&rgmii1>; 61*63e572b1SMichael Opdenacker phy-mode = "rgmii-id"; 62*63e572b1SMichael Opdenacker pinctrl-names = "default"; 63*63e572b1SMichael Opdenacker pinctrl-0 = <&gmac1_cfg>; 64*63e572b1SMichael Opdenacker rx-internal-delay-ps = <0>; 65*63e572b1SMichael Opdenacker tx-internal-delay-ps = <250>; 66*63e572b1SMichael Opdenacker status = "okay"; 67*63e572b1SMichael Opdenacker 68*63e572b1SMichael Opdenacker mdio-bus { 69*63e572b1SMichael Opdenacker #address-cells = <0x1>; 70*63e572b1SMichael Opdenacker #size-cells = <0x0>; 71*63e572b1SMichael Opdenacker 72*63e572b1SMichael Opdenacker reset-gpios = <&gpio K1_GPIO(115) GPIO_ACTIVE_LOW>; 73*63e572b1SMichael Opdenacker reset-delay-us = <10000>; 74*63e572b1SMichael Opdenacker reset-post-delay-us = <100000>; 75*63e572b1SMichael Opdenacker 76*63e572b1SMichael Opdenacker rgmii1: phy@1 { 77*63e572b1SMichael Opdenacker reg = <0x1>; 78*63e572b1SMichael Opdenacker }; 79*63e572b1SMichael Opdenacker }; 80*63e572b1SMichael Opdenacker}; 81*63e572b1SMichael Opdenacker 82*63e572b1SMichael Opdenacker&pdma { 83*63e572b1SMichael Opdenacker status = "okay"; 84*63e572b1SMichael Opdenacker}; 85*63e572b1SMichael Opdenacker 86*63e572b1SMichael Opdenacker&uart0 { 87*63e572b1SMichael Opdenacker pinctrl-names = "default"; 88*63e572b1SMichael Opdenacker pinctrl-0 = <&uart0_2_cfg>; 89*63e572b1SMichael Opdenacker status = "okay"; 90*63e572b1SMichael Opdenacker}; 91