1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> 5 */ 6 7#include <dt-bindings/clock/sophgo,cv1800.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include "cv18xx-reset.h" 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 osc: oscillator { 17 compatible = "fixed-clock"; 18 clock-output-names = "osc_25m"; 19 #clock-cells = <0>; 20 }; 21 22 soc { 23 compatible = "simple-bus"; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges; 27 28 rst: reset-controller@3003000 { 29 compatible = "sophgo,cv1800b-reset"; 30 reg = <0x3003000 0x1000>; 31 #reset-cells = <1>; 32 }; 33 34 mdio: mdio-mux@3009800 { 35 compatible = "mdio-mux-mmioreg", "mdio-mux"; 36 reg = <0x3009800 0x4>; 37 #address-cells = <1>; 38 #size-cells = <0>; 39 mdio-parent-bus = <&gmac0_mdio>; 40 mux-mask = <0x80>; 41 status = "disabled"; 42 43 internal_mdio: mdio@0 { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 reg = <0>; 47 48 internal_ephy: phy@0 { 49 compatible = "ethernet-phy-ieee802.3-c22"; 50 reg = <1>; 51 }; 52 }; 53 54 external_mdio: mdio@80 { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 reg = <0x80>; 58 }; 59 }; 60 61 gpio0: gpio@3020000 { 62 compatible = "snps,dw-apb-gpio"; 63 reg = <0x3020000 0x1000>; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 resets = <&rst RST_GPIO0>; 67 68 porta: gpio-controller@0 { 69 compatible = "snps,dw-apb-gpio-port"; 70 gpio-controller; 71 #gpio-cells = <2>; 72 ngpios = <32>; 73 reg = <0>; 74 interrupt-controller; 75 #interrupt-cells = <2>; 76 interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>; 77 }; 78 }; 79 80 gpio1: gpio@3021000 { 81 compatible = "snps,dw-apb-gpio"; 82 reg = <0x3021000 0x1000>; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 resets = <&rst RST_GPIO1>; 86 87 portb: gpio-controller@0 { 88 compatible = "snps,dw-apb-gpio-port"; 89 gpio-controller; 90 #gpio-cells = <2>; 91 ngpios = <32>; 92 reg = <0>; 93 interrupt-controller; 94 #interrupt-cells = <2>; 95 interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; 96 }; 97 }; 98 99 gpio2: gpio@3022000 { 100 compatible = "snps,dw-apb-gpio"; 101 reg = <0x3022000 0x1000>; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 resets = <&rst RST_GPIO2>; 105 106 portc: gpio-controller@0 { 107 compatible = "snps,dw-apb-gpio-port"; 108 gpio-controller; 109 #gpio-cells = <2>; 110 ngpios = <32>; 111 reg = <0>; 112 interrupt-controller; 113 #interrupt-cells = <2>; 114 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 115 }; 116 }; 117 118 gpio3: gpio@3023000 { 119 compatible = "snps,dw-apb-gpio"; 120 reg = <0x3023000 0x1000>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 resets = <&rst RST_GPIO3>; 124 125 portd: gpio-controller@0 { 126 compatible = "snps,dw-apb-gpio-port"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 ngpios = <32>; 130 reg = <0>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>; 134 }; 135 }; 136 137 saradc: adc@30f0000 { 138 compatible = "sophgo,cv1800b-saradc"; 139 reg = <0x030f0000 0x1000>; 140 clocks = <&clk CLK_SARADC>; 141 interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 status = "disabled"; 145 146 channel@0 { 147 reg = <0>; 148 }; 149 150 channel@1 { 151 reg = <1>; 152 }; 153 154 channel@2 { 155 reg = <2>; 156 }; 157 }; 158 159 i2c0: i2c@4000000 { 160 compatible = "snps,designware-i2c"; 161 reg = <0x04000000 0x10000>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; 165 clock-names = "ref", "pclk"; 166 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 167 resets = <&rst RST_I2C0>; 168 status = "disabled"; 169 }; 170 171 i2c1: i2c@4010000 { 172 compatible = "snps,designware-i2c"; 173 reg = <0x04010000 0x10000>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; 177 clock-names = "ref", "pclk"; 178 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 179 resets = <&rst RST_I2C1>; 180 status = "disabled"; 181 }; 182 183 i2c2: i2c@4020000 { 184 compatible = "snps,designware-i2c"; 185 reg = <0x04020000 0x10000>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; 189 clock-names = "ref", "pclk"; 190 interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>; 191 resets = <&rst RST_I2C2>; 192 status = "disabled"; 193 }; 194 195 i2c3: i2c@4030000 { 196 compatible = "snps,designware-i2c"; 197 reg = <0x04030000 0x10000>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; 201 clock-names = "ref", "pclk"; 202 interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>; 203 resets = <&rst RST_I2C3>; 204 status = "disabled"; 205 }; 206 207 i2c4: i2c@4040000 { 208 compatible = "snps,designware-i2c"; 209 reg = <0x04040000 0x10000>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; 213 clock-names = "ref", "pclk"; 214 interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>; 215 resets = <&rst RST_I2C4>; 216 status = "disabled"; 217 }; 218 219 gmac0: ethernet@4070000 { 220 compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a"; 221 reg = <0x04070000 0x10000>; 222 clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; 223 clock-names = "stmmaceth", "ptp_ref"; 224 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 225 interrupt-names = "macirq"; 226 phy-handle = <&internal_ephy>; 227 phy-mode = "internal"; 228 resets = <&rst RST_ETH0>; 229 reset-names = "stmmaceth"; 230 rx-fifo-depth = <8192>; 231 tx-fifo-depth = <8192>; 232 snps,multicast-filter-bins = <0>; 233 snps,perfect-filter-entries = <1>; 234 snps,aal; 235 snps,txpbl = <8>; 236 snps,rxpbl = <8>; 237 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 238 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 239 snps,axi-config = <&gmac0_stmmac_axi_setup>; 240 status = "disabled"; 241 242 gmac0_mdio: mdio { 243 compatible = "snps,dwmac-mdio"; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 }; 247 248 gmac0_mtl_rx_setup: rx-queues-config { 249 snps,rx-queues-to-use = <1>; 250 queue0 {}; 251 }; 252 253 gmac0_mtl_tx_setup: tx-queues-config { 254 snps,tx-queues-to-use = <1>; 255 queue0 {}; 256 }; 257 258 gmac0_stmmac_axi_setup: stmmac-axi-config { 259 snps,blen = <16 8 4 0 0 0 0>; 260 snps,rd_osr_lmt = <2>; 261 snps,wr_osr_lmt = <1>; 262 }; 263 }; 264 265 uart0: serial@4140000 { 266 compatible = "snps,dw-apb-uart"; 267 reg = <0x04140000 0x100>; 268 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; 270 clock-names = "baudclk", "apb_pclk"; 271 reg-shift = <2>; 272 reg-io-width = <4>; 273 resets = <&rst RST_UART0>; 274 status = "disabled"; 275 }; 276 277 uart1: serial@4150000 { 278 compatible = "snps,dw-apb-uart"; 279 reg = <0x04150000 0x100>; 280 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; 282 clock-names = "baudclk", "apb_pclk"; 283 reg-shift = <2>; 284 reg-io-width = <4>; 285 resets = <&rst RST_UART1>; 286 status = "disabled"; 287 }; 288 289 uart2: serial@4160000 { 290 compatible = "snps,dw-apb-uart"; 291 reg = <0x04160000 0x100>; 292 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; 294 clock-names = "baudclk", "apb_pclk"; 295 reg-shift = <2>; 296 reg-io-width = <4>; 297 resets = <&rst RST_UART2>; 298 status = "disabled"; 299 }; 300 301 uart3: serial@4170000 { 302 compatible = "snps,dw-apb-uart"; 303 reg = <0x04170000 0x100>; 304 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; 306 clock-names = "baudclk", "apb_pclk"; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 resets = <&rst RST_UART3>; 310 status = "disabled"; 311 }; 312 313 spi0: spi@4180000 { 314 compatible = "snps,dw-apb-ssi"; 315 reg = <0x04180000 0x10000>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; 319 clock-names = "ssi_clk", "pclk"; 320 interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>; 321 resets = <&rst RST_SPI0>; 322 status = "disabled"; 323 }; 324 325 spi1: spi@4190000 { 326 compatible = "snps,dw-apb-ssi"; 327 reg = <0x04190000 0x10000>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; 331 clock-names = "ssi_clk", "pclk"; 332 interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>; 333 resets = <&rst RST_SPI1>; 334 status = "disabled"; 335 }; 336 337 spi2: spi@41a0000 { 338 compatible = "snps,dw-apb-ssi"; 339 reg = <0x041a0000 0x10000>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; 343 clock-names = "ssi_clk", "pclk"; 344 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 345 resets = <&rst RST_SPI2>; 346 status = "disabled"; 347 }; 348 349 spi3: spi@41b0000 { 350 compatible = "snps,dw-apb-ssi"; 351 reg = <0x041b0000 0x10000>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; 355 clock-names = "ssi_clk", "pclk"; 356 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 357 resets = <&rst RST_SPI3>; 358 status = "disabled"; 359 }; 360 361 uart4: serial@41c0000 { 362 compatible = "snps,dw-apb-uart"; 363 reg = <0x041c0000 0x100>; 364 interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; 366 clock-names = "baudclk", "apb_pclk"; 367 reg-shift = <2>; 368 reg-io-width = <4>; 369 resets = <&rst RST_UART4>; 370 status = "disabled"; 371 }; 372 373 sdhci0: mmc@4310000 { 374 compatible = "sophgo,cv1800b-dwcmshc"; 375 reg = <0x4310000 0x1000>; 376 interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clk CLK_AXI4_SD0>, 378 <&clk CLK_SD0>; 379 clock-names = "core", "bus"; 380 status = "disabled"; 381 }; 382 383 sdhci1: mmc@4320000 { 384 compatible = "sophgo,cv1800b-dwcmshc"; 385 reg = <0x4320000 0x1000>; 386 interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clk CLK_AXI4_SD1>, 388 <&clk CLK_SD1>; 389 clock-names = "core", "bus"; 390 status = "disabled"; 391 }; 392 393 dmac: dma-controller@4330000 { 394 compatible = "snps,axi-dma-1.01a"; 395 reg = <0x04330000 0x1000>; 396 interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; 398 clock-names = "core-clk", "cfgr-clk"; 399 #dma-cells = <1>; 400 dma-channels = <8>; 401 snps,block-size = <1024 1024 1024 1024 402 1024 1024 1024 1024>; 403 snps,priority = <0 1 2 3 4 5 6 7>; 404 snps,dma-masters = <2>; 405 snps,data-width = <2>; 406 status = "disabled"; 407 }; 408 409 rtc@5025000 { 410 compatible = "sophgo,cv1800b-rtc", "syscon"; 411 reg = <0x5025000 0x2000>; 412 interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, 413 <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, 414 <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-names = "alarm", "longpress", "vbat"; 416 clocks = <&clk CLK_RTC_25M>, 417 <&clk CLK_SRC_RTC_SYS_0>; 418 clock-names = "rtc", "mcu"; 419 }; 420 }; 421}; 422