172296bdeSPaul Walmsley// SPDX-License-Identifier: (GPL-2.0 OR MIT) 272296bdeSPaul Walmsley/* Copyright (c) 2018-2019 SiFive, Inc */ 372296bdeSPaul Walmsley 472296bdeSPaul Walmsley/dts-v1/; 572296bdeSPaul Walmsley 672296bdeSPaul Walmsley#include <dt-bindings/clock/sifive-fu540-prci.h> 772296bdeSPaul Walmsley 872296bdeSPaul Walmsley/ { 972296bdeSPaul Walmsley #address-cells = <2>; 1072296bdeSPaul Walmsley #size-cells = <2>; 1172296bdeSPaul Walmsley compatible = "sifive,fu540-c000", "sifive,fu540"; 1272296bdeSPaul Walmsley 1372296bdeSPaul Walmsley aliases { 1472296bdeSPaul Walmsley serial0 = &uart0; 1572296bdeSPaul Walmsley serial1 = &uart1; 1672296bdeSPaul Walmsley }; 1772296bdeSPaul Walmsley 1872296bdeSPaul Walmsley chosen { 1972296bdeSPaul Walmsley }; 2072296bdeSPaul Walmsley 2172296bdeSPaul Walmsley cpus { 2272296bdeSPaul Walmsley #address-cells = <1>; 2372296bdeSPaul Walmsley #size-cells = <0>; 2472296bdeSPaul Walmsley cpu0: cpu@0 { 2572296bdeSPaul Walmsley compatible = "sifive,e51", "sifive,rocket0", "riscv"; 2672296bdeSPaul Walmsley device_type = "cpu"; 2772296bdeSPaul Walmsley i-cache-block-size = <64>; 2872296bdeSPaul Walmsley i-cache-sets = <128>; 2972296bdeSPaul Walmsley i-cache-size = <16384>; 3072296bdeSPaul Walmsley reg = <0>; 3172296bdeSPaul Walmsley riscv,isa = "rv64imac"; 3272296bdeSPaul Walmsley status = "disabled"; 3372296bdeSPaul Walmsley cpu0_intc: interrupt-controller { 3472296bdeSPaul Walmsley #interrupt-cells = <1>; 3572296bdeSPaul Walmsley compatible = "riscv,cpu-intc"; 3672296bdeSPaul Walmsley interrupt-controller; 3772296bdeSPaul Walmsley }; 3872296bdeSPaul Walmsley }; 3972296bdeSPaul Walmsley cpu1: cpu@1 { 4072296bdeSPaul Walmsley compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 4172296bdeSPaul Walmsley d-cache-block-size = <64>; 4272296bdeSPaul Walmsley d-cache-sets = <64>; 4372296bdeSPaul Walmsley d-cache-size = <32768>; 4472296bdeSPaul Walmsley d-tlb-sets = <1>; 4572296bdeSPaul Walmsley d-tlb-size = <32>; 4672296bdeSPaul Walmsley device_type = "cpu"; 4772296bdeSPaul Walmsley i-cache-block-size = <64>; 4872296bdeSPaul Walmsley i-cache-sets = <64>; 4972296bdeSPaul Walmsley i-cache-size = <32768>; 5072296bdeSPaul Walmsley i-tlb-sets = <1>; 5172296bdeSPaul Walmsley i-tlb-size = <32>; 5272296bdeSPaul Walmsley mmu-type = "riscv,sv39"; 5372296bdeSPaul Walmsley reg = <1>; 5472296bdeSPaul Walmsley riscv,isa = "rv64imafdc"; 5572296bdeSPaul Walmsley tlb-split; 5672296bdeSPaul Walmsley cpu1_intc: interrupt-controller { 5772296bdeSPaul Walmsley #interrupt-cells = <1>; 5872296bdeSPaul Walmsley compatible = "riscv,cpu-intc"; 5972296bdeSPaul Walmsley interrupt-controller; 6072296bdeSPaul Walmsley }; 6172296bdeSPaul Walmsley }; 6272296bdeSPaul Walmsley cpu2: cpu@2 { 6372296bdeSPaul Walmsley clock-frequency = <0>; 6472296bdeSPaul Walmsley compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 6572296bdeSPaul Walmsley d-cache-block-size = <64>; 6672296bdeSPaul Walmsley d-cache-sets = <64>; 6772296bdeSPaul Walmsley d-cache-size = <32768>; 6872296bdeSPaul Walmsley d-tlb-sets = <1>; 6972296bdeSPaul Walmsley d-tlb-size = <32>; 7072296bdeSPaul Walmsley device_type = "cpu"; 7172296bdeSPaul Walmsley i-cache-block-size = <64>; 7272296bdeSPaul Walmsley i-cache-sets = <64>; 7372296bdeSPaul Walmsley i-cache-size = <32768>; 7472296bdeSPaul Walmsley i-tlb-sets = <1>; 7572296bdeSPaul Walmsley i-tlb-size = <32>; 7672296bdeSPaul Walmsley mmu-type = "riscv,sv39"; 7772296bdeSPaul Walmsley reg = <2>; 7872296bdeSPaul Walmsley riscv,isa = "rv64imafdc"; 7972296bdeSPaul Walmsley tlb-split; 8072296bdeSPaul Walmsley cpu2_intc: interrupt-controller { 8172296bdeSPaul Walmsley #interrupt-cells = <1>; 8272296bdeSPaul Walmsley compatible = "riscv,cpu-intc"; 8372296bdeSPaul Walmsley interrupt-controller; 8472296bdeSPaul Walmsley }; 8572296bdeSPaul Walmsley }; 8672296bdeSPaul Walmsley cpu3: cpu@3 { 8772296bdeSPaul Walmsley clock-frequency = <0>; 8872296bdeSPaul Walmsley compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 8972296bdeSPaul Walmsley d-cache-block-size = <64>; 9072296bdeSPaul Walmsley d-cache-sets = <64>; 9172296bdeSPaul Walmsley d-cache-size = <32768>; 9272296bdeSPaul Walmsley d-tlb-sets = <1>; 9372296bdeSPaul Walmsley d-tlb-size = <32>; 9472296bdeSPaul Walmsley device_type = "cpu"; 9572296bdeSPaul Walmsley i-cache-block-size = <64>; 9672296bdeSPaul Walmsley i-cache-sets = <64>; 9772296bdeSPaul Walmsley i-cache-size = <32768>; 9872296bdeSPaul Walmsley i-tlb-sets = <1>; 9972296bdeSPaul Walmsley i-tlb-size = <32>; 10072296bdeSPaul Walmsley mmu-type = "riscv,sv39"; 10172296bdeSPaul Walmsley reg = <3>; 10272296bdeSPaul Walmsley riscv,isa = "rv64imafdc"; 10372296bdeSPaul Walmsley tlb-split; 10472296bdeSPaul Walmsley cpu3_intc: interrupt-controller { 10572296bdeSPaul Walmsley #interrupt-cells = <1>; 10672296bdeSPaul Walmsley compatible = "riscv,cpu-intc"; 10772296bdeSPaul Walmsley interrupt-controller; 10872296bdeSPaul Walmsley }; 10972296bdeSPaul Walmsley }; 11072296bdeSPaul Walmsley cpu4: cpu@4 { 11172296bdeSPaul Walmsley clock-frequency = <0>; 11272296bdeSPaul Walmsley compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 11372296bdeSPaul Walmsley d-cache-block-size = <64>; 11472296bdeSPaul Walmsley d-cache-sets = <64>; 11572296bdeSPaul Walmsley d-cache-size = <32768>; 11672296bdeSPaul Walmsley d-tlb-sets = <1>; 11772296bdeSPaul Walmsley d-tlb-size = <32>; 11872296bdeSPaul Walmsley device_type = "cpu"; 11972296bdeSPaul Walmsley i-cache-block-size = <64>; 12072296bdeSPaul Walmsley i-cache-sets = <64>; 12172296bdeSPaul Walmsley i-cache-size = <32768>; 12272296bdeSPaul Walmsley i-tlb-sets = <1>; 12372296bdeSPaul Walmsley i-tlb-size = <32>; 12472296bdeSPaul Walmsley mmu-type = "riscv,sv39"; 12572296bdeSPaul Walmsley reg = <4>; 12672296bdeSPaul Walmsley riscv,isa = "rv64imafdc"; 12772296bdeSPaul Walmsley tlb-split; 12872296bdeSPaul Walmsley cpu4_intc: interrupt-controller { 12972296bdeSPaul Walmsley #interrupt-cells = <1>; 13072296bdeSPaul Walmsley compatible = "riscv,cpu-intc"; 13172296bdeSPaul Walmsley interrupt-controller; 13272296bdeSPaul Walmsley }; 13372296bdeSPaul Walmsley }; 13472296bdeSPaul Walmsley }; 13572296bdeSPaul Walmsley soc { 13672296bdeSPaul Walmsley #address-cells = <2>; 13772296bdeSPaul Walmsley #size-cells = <2>; 13872296bdeSPaul Walmsley compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; 13972296bdeSPaul Walmsley ranges; 14072296bdeSPaul Walmsley plic0: interrupt-controller@c000000 { 14172296bdeSPaul Walmsley #interrupt-cells = <1>; 14272296bdeSPaul Walmsley compatible = "sifive,plic-1.0.0"; 14372296bdeSPaul Walmsley reg = <0x0 0xc000000 0x0 0x4000000>; 14472296bdeSPaul Walmsley riscv,ndev = <53>; 14572296bdeSPaul Walmsley interrupt-controller; 14672296bdeSPaul Walmsley interrupts-extended = < 14772296bdeSPaul Walmsley &cpu0_intc 0xffffffff 14872296bdeSPaul Walmsley &cpu1_intc 0xffffffff &cpu1_intc 9 14972296bdeSPaul Walmsley &cpu2_intc 0xffffffff &cpu2_intc 9 15072296bdeSPaul Walmsley &cpu3_intc 0xffffffff &cpu3_intc 9 15172296bdeSPaul Walmsley &cpu4_intc 0xffffffff &cpu4_intc 9>; 15272296bdeSPaul Walmsley }; 15372296bdeSPaul Walmsley prci: clock-controller@10000000 { 15472296bdeSPaul Walmsley compatible = "sifive,fu540-c000-prci"; 15572296bdeSPaul Walmsley reg = <0x0 0x10000000 0x0 0x1000>; 15672296bdeSPaul Walmsley clocks = <&hfclk>, <&rtcclk>; 15772296bdeSPaul Walmsley #clock-cells = <1>; 15872296bdeSPaul Walmsley }; 15972296bdeSPaul Walmsley uart0: serial@10010000 { 16072296bdeSPaul Walmsley compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 16172296bdeSPaul Walmsley reg = <0x0 0x10010000 0x0 0x1000>; 16272296bdeSPaul Walmsley interrupt-parent = <&plic0>; 16372296bdeSPaul Walmsley interrupts = <4>; 16472296bdeSPaul Walmsley clocks = <&prci PRCI_CLK_TLCLK>; 16545b03df2SYash Shah status = "disabled"; 16672296bdeSPaul Walmsley }; 16772296bdeSPaul Walmsley uart1: serial@10011000 { 16872296bdeSPaul Walmsley compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 16972296bdeSPaul Walmsley reg = <0x0 0x10011000 0x0 0x1000>; 17072296bdeSPaul Walmsley interrupt-parent = <&plic0>; 17172296bdeSPaul Walmsley interrupts = <5>; 17272296bdeSPaul Walmsley clocks = <&prci PRCI_CLK_TLCLK>; 17345b03df2SYash Shah status = "disabled"; 17472296bdeSPaul Walmsley }; 17572296bdeSPaul Walmsley i2c0: i2c@10030000 { 17672296bdeSPaul Walmsley compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; 17772296bdeSPaul Walmsley reg = <0x0 0x10030000 0x0 0x1000>; 17872296bdeSPaul Walmsley interrupt-parent = <&plic0>; 17972296bdeSPaul Walmsley interrupts = <50>; 18072296bdeSPaul Walmsley clocks = <&prci PRCI_CLK_TLCLK>; 18172296bdeSPaul Walmsley reg-shift = <2>; 18272296bdeSPaul Walmsley reg-io-width = <1>; 18372296bdeSPaul Walmsley #address-cells = <1>; 18472296bdeSPaul Walmsley #size-cells = <0>; 18545b03df2SYash Shah status = "disabled"; 18672296bdeSPaul Walmsley }; 18772296bdeSPaul Walmsley qspi0: spi@10040000 { 18872296bdeSPaul Walmsley compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 18972296bdeSPaul Walmsley reg = <0x0 0x10040000 0x0 0x1000 19072296bdeSPaul Walmsley 0x0 0x20000000 0x0 0x10000000>; 19172296bdeSPaul Walmsley interrupt-parent = <&plic0>; 19272296bdeSPaul Walmsley interrupts = <51>; 19372296bdeSPaul Walmsley clocks = <&prci PRCI_CLK_TLCLK>; 19472296bdeSPaul Walmsley #address-cells = <1>; 19572296bdeSPaul Walmsley #size-cells = <0>; 19645b03df2SYash Shah status = "disabled"; 19772296bdeSPaul Walmsley }; 19872296bdeSPaul Walmsley qspi1: spi@10041000 { 19972296bdeSPaul Walmsley compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 20072296bdeSPaul Walmsley reg = <0x0 0x10041000 0x0 0x1000 20172296bdeSPaul Walmsley 0x0 0x30000000 0x0 0x10000000>; 20272296bdeSPaul Walmsley interrupt-parent = <&plic0>; 20372296bdeSPaul Walmsley interrupts = <52>; 20472296bdeSPaul Walmsley clocks = <&prci PRCI_CLK_TLCLK>; 20572296bdeSPaul Walmsley #address-cells = <1>; 20672296bdeSPaul Walmsley #size-cells = <0>; 20745b03df2SYash Shah status = "disabled"; 20872296bdeSPaul Walmsley }; 20972296bdeSPaul Walmsley qspi2: spi@10050000 { 21072296bdeSPaul Walmsley compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 21172296bdeSPaul Walmsley reg = <0x0 0x10050000 0x0 0x1000>; 21272296bdeSPaul Walmsley interrupt-parent = <&plic0>; 21372296bdeSPaul Walmsley interrupts = <6>; 21472296bdeSPaul Walmsley clocks = <&prci PRCI_CLK_TLCLK>; 21572296bdeSPaul Walmsley #address-cells = <1>; 21672296bdeSPaul Walmsley #size-cells = <0>; 21745b03df2SYash Shah status = "disabled"; 21872296bdeSPaul Walmsley }; 21926091eefSYash Shah eth0: ethernet@10090000 { 22026091eefSYash Shah compatible = "sifive,fu540-c000-gem"; 22126091eefSYash Shah interrupt-parent = <&plic0>; 22226091eefSYash Shah interrupts = <53>; 22326091eefSYash Shah reg = <0x0 0x10090000 0x0 0x2000 22426091eefSYash Shah 0x0 0x100a0000 0x0 0x1000>; 22526091eefSYash Shah local-mac-address = [00 00 00 00 00 00]; 22626091eefSYash Shah clock-names = "pclk", "hclk"; 22726091eefSYash Shah clocks = <&prci PRCI_CLK_GEMGXLPLL>, 22826091eefSYash Shah <&prci PRCI_CLK_GEMGXLPLL>; 22926091eefSYash Shah #address-cells = <1>; 23026091eefSYash Shah #size-cells = <0>; 23126091eefSYash Shah status = "disabled"; 23226091eefSYash Shah }; 233*b45e0c30SYash Shah pwm0: pwm@10020000 { 234*b45e0c30SYash Shah compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; 235*b45e0c30SYash Shah reg = <0x0 0x10020000 0x0 0x1000>; 236*b45e0c30SYash Shah interrupt-parent = <&plic0>; 237*b45e0c30SYash Shah interrupts = <42 43 44 45>; 238*b45e0c30SYash Shah clocks = <&prci PRCI_CLK_TLCLK>; 239*b45e0c30SYash Shah #pwm-cells = <3>; 240*b45e0c30SYash Shah status = "disabled"; 241*b45e0c30SYash Shah }; 242*b45e0c30SYash Shah pwm1: pwm@10021000 { 243*b45e0c30SYash Shah compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; 244*b45e0c30SYash Shah reg = <0x0 0x10021000 0x0 0x1000>; 245*b45e0c30SYash Shah interrupt-parent = <&plic0>; 246*b45e0c30SYash Shah interrupts = <46 47 48 49>; 247*b45e0c30SYash Shah clocks = <&prci PRCI_CLK_TLCLK>; 248*b45e0c30SYash Shah #pwm-cells = <3>; 249*b45e0c30SYash Shah status = "disabled"; 250*b45e0c30SYash Shah }; 25126091eefSYash Shah 25272296bdeSPaul Walmsley }; 25372296bdeSPaul Walmsley}; 254