1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2025 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-icicle-kit-fabric.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10 11/ { 12 aliases { 13 ethernet0 = &mac1; 14 serial0 = &mmuart0; 15 serial1 = &mmuart1; 16 serial2 = &mmuart2; 17 serial3 = &mmuart3; 18 serial4 = &mmuart4; 19 }; 20 21 chosen { 22 stdout-path = "serial1:115200n8"; 23 }; 24 25 leds { 26 compatible = "gpio-leds"; 27 28 led-1 { 29 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 30 color = <LED_COLOR_ID_RED>; 31 label = "led1"; 32 }; 33 34 led-2 { 35 gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; 36 color = <LED_COLOR_ID_RED>; 37 label = "led2"; 38 }; 39 40 led-3 { 41 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; 42 color = <LED_COLOR_ID_AMBER>; 43 label = "led3"; 44 }; 45 46 led-4 { 47 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 48 color = <LED_COLOR_ID_AMBER>; 49 label = "led4"; 50 }; 51 }; 52 53 ddrc_cache_lo: memory@80000000 { 54 device_type = "memory"; 55 reg = <0x0 0x80000000 0x0 0x40000000>; 56 }; 57 58 ddrc_cache_hi: memory@1040000000 { 59 device_type = "memory"; 60 reg = <0x10 0x40000000 0x0 0x40000000>; 61 }; 62 63 reserved-memory { 64 #address-cells = <2>; 65 #size-cells = <2>; 66 ranges; 67 68 hss_payload: region@bfc00000 { 69 reg = <0x0 0xbfc00000 0x0 0x400000>; 70 no-map; 71 }; 72 }; 73}; 74 75&core_pwm0 { 76 status = "okay"; 77}; 78 79&gpio2 { 80 interrupts = <53>, <53>, <53>, <53>, 81 <53>, <53>, <53>, <53>, 82 <53>, <53>, <53>, <53>, 83 <53>, <53>, <53>, <53>, 84 <53>, <53>, <53>, <53>, 85 <53>, <53>, <53>, <53>, 86 <53>, <53>, <53>, <53>, 87 <53>, <53>, <53>, <53>; 88 status = "okay"; 89}; 90 91&i2c0 { 92 status = "okay"; 93}; 94 95&i2c1 { 96 status = "okay"; 97 98 power-monitor@10 { 99 compatible = "microchip,pac1934"; 100 reg = <0x10>; 101 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 channel@1 { 106 reg = <0x1>; 107 shunt-resistor-micro-ohms = <10000>; 108 label = "VDDREG"; 109 }; 110 111 channel@2 { 112 reg = <0x2>; 113 shunt-resistor-micro-ohms = <10000>; 114 label = "VDDA25"; 115 }; 116 117 channel@3 { 118 reg = <0x3>; 119 shunt-resistor-micro-ohms = <10000>; 120 label = "VDD25"; 121 }; 122 123 channel@4 { 124 reg = <0x4>; 125 shunt-resistor-micro-ohms = <10000>; 126 label = "VDDA_REG"; 127 }; 128 }; 129}; 130 131&i2c2 { 132 status = "okay"; 133}; 134 135&ihc { 136 status = "okay"; 137}; 138 139&mac0 { 140 phy-mode = "sgmii"; 141 phy-handle = <&phy0>; 142 status = "okay"; 143}; 144 145&mac1 { 146 phy-mode = "sgmii"; 147 phy-handle = <&phy1>; 148 status = "okay"; 149 150 phy1: ethernet-phy@9 { 151 reg = <9>; 152 }; 153 154 phy0: ethernet-phy@8 { 155 reg = <8>; 156 }; 157}; 158 159&mbox { 160 status = "okay"; 161}; 162 163&mmc { 164 bus-width = <4>; 165 disable-wp; 166 cap-sd-highspeed; 167 cap-mmc-highspeed; 168 mmc-ddr-1_8v; 169 mmc-hs200-1_8v; 170 sd-uhs-sdr12; 171 sd-uhs-sdr25; 172 sd-uhs-sdr50; 173 sd-uhs-sdr104; 174 status = "okay"; 175}; 176 177&mmuart1 { 178 status = "okay"; 179}; 180 181&mmuart2 { 182 status = "okay"; 183}; 184 185&mmuart3 { 186 status = "okay"; 187}; 188 189&mmuart4 { 190 status = "okay"; 191}; 192 193&pcie { 194 status = "okay"; 195}; 196 197&qspi { 198 status = "okay"; 199}; 200 201&refclk { 202 clock-frequency = <125000000>; 203}; 204 205&refclk_ccc { 206 clock-frequency = <50000000>; 207}; 208 209&rtc { 210 status = "okay"; 211}; 212 213&spi0 { 214 status = "okay"; 215}; 216 217&spi1 { 218 status = "okay"; 219}; 220 221&syscontroller { 222 status = "okay"; 223}; 224 225&syscontroller_qspi { 226 /* 227 * The flash *is* there, but Icicle kits that have engineering sample 228 * silicon (write?) access to this flash to non-functional. The system 229 * controller itself can actually access it, but the MSS cannot write 230 * an image there. Instantiating a coreQSPI in the fabric & connecting 231 * it to the flash instead should work though. Pre-production or later 232 * silicon does not have this issue. 233 */ 234 status = "disabled"; 235 236 sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT 237 compatible = "jedec,spi-nor"; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 spi-max-frequency = <20000000>; 241 spi-rx-bus-width = <1>; 242 reg = <0>; 243 }; 244}; 245 246&usb { 247 status = "okay"; 248 dr_mode = "host"; 249}; 250