1*acc21153SValentina Fernandez// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*acc21153SValentina Fernandez/* Copyright (c) 2020-2025 Microchip Technology Inc */ 3*acc21153SValentina Fernandez 4*acc21153SValentina Fernandez/ { 5*acc21153SValentina Fernandez core_pwm0: pwm@40000000 { 6*acc21153SValentina Fernandez compatible = "microchip,corepwm-rtl-v4"; 7*acc21153SValentina Fernandez reg = <0x0 0x40000000 0x0 0xF0>; 8*acc21153SValentina Fernandez microchip,sync-update-mask = /bits/ 32 <0>; 9*acc21153SValentina Fernandez #pwm-cells = <3>; 10*acc21153SValentina Fernandez clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>; 11*acc21153SValentina Fernandez status = "disabled"; 12*acc21153SValentina Fernandez }; 13*acc21153SValentina Fernandez 14*acc21153SValentina Fernandez i2c2: i2c@40000200 { 15*acc21153SValentina Fernandez compatible = "microchip,corei2c-rtl-v7"; 16*acc21153SValentina Fernandez reg = <0x0 0x40000200 0x0 0x100>; 17*acc21153SValentina Fernandez #address-cells = <1>; 18*acc21153SValentina Fernandez #size-cells = <0>; 19*acc21153SValentina Fernandez clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>; 20*acc21153SValentina Fernandez interrupt-parent = <&plic>; 21*acc21153SValentina Fernandez interrupts = <122>; 22*acc21153SValentina Fernandez clock-frequency = <100000>; 23*acc21153SValentina Fernandez status = "disabled"; 24*acc21153SValentina Fernandez }; 25*acc21153SValentina Fernandez 26*acc21153SValentina Fernandez ihc: mailbox { 27*acc21153SValentina Fernandez compatible = "microchip,sbi-ipc"; 28*acc21153SValentina Fernandez interrupt-parent = <&plic>; 29*acc21153SValentina Fernandez interrupts = <180>, <179>, <178>, <177>; 30*acc21153SValentina Fernandez interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; 31*acc21153SValentina Fernandez #mbox-cells = <1>; 32*acc21153SValentina Fernandez status = "disabled"; 33*acc21153SValentina Fernandez }; 34*acc21153SValentina Fernandez 35*acc21153SValentina Fernandez mailbox@50000000 { 36*acc21153SValentina Fernandez compatible = "microchip,miv-ihc-rtl-v2"; 37*acc21153SValentina Fernandez reg = <0x0 0x50000000 0x0 0x1c000>; 38*acc21153SValentina Fernandez interrupt-parent = <&plic>; 39*acc21153SValentina Fernandez interrupts = <180>, <179>, <178>, <177>; 40*acc21153SValentina Fernandez interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; 41*acc21153SValentina Fernandez #mbox-cells = <1>; 42*acc21153SValentina Fernandez microchip,ihc-chan-disabled-mask = /bits/ 16 <0>; 43*acc21153SValentina Fernandez status = "disabled"; 44*acc21153SValentina Fernandez }; 45*acc21153SValentina Fernandez 46*acc21153SValentina Fernandez refclk_ccc: clock-cccref { 47*acc21153SValentina Fernandez compatible = "fixed-clock"; 48*acc21153SValentina Fernandez #clock-cells = <0>; 49*acc21153SValentina Fernandez }; 50*acc21153SValentina Fernandez}; 51*acc21153SValentina Fernandez 52*acc21153SValentina Fernandez&ccc_sw { 53*acc21153SValentina Fernandez clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, 54*acc21153SValentina Fernandez <&refclk_ccc>, <&refclk_ccc>; 55*acc21153SValentina Fernandez clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", 56*acc21153SValentina Fernandez "dll0_ref", "dll1_ref"; 57*acc21153SValentina Fernandez status = "okay"; 58*acc21153SValentina Fernandez}; 59