1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2025 Microchip Technology Inc */ 3 4/ { 5 core_pwm0: pwm@40000000 { 6 compatible = "microchip,corepwm-rtl-v4"; 7 reg = <0x0 0x40000000 0x0 0xF0>; 8 microchip,sync-update-mask = /bits/ 32 <0>; 9 #pwm-cells = <3>; 10 clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>; 11 status = "disabled"; 12 }; 13 14 i2c2: i2c@40000200 { 15 compatible = "microchip,corei2c-rtl-v7"; 16 reg = <0x0 0x40000200 0x0 0x100>; 17 #address-cells = <1>; 18 #size-cells = <0>; 19 clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>; 20 interrupt-parent = <&plic>; 21 interrupts = <122>; 22 clock-frequency = <100000>; 23 status = "disabled"; 24 }; 25 26 ihc: mailbox { 27 compatible = "microchip,sbi-ipc"; 28 interrupt-parent = <&plic>; 29 interrupts = <180>, <179>, <178>, <177>; 30 interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; 31 #mbox-cells = <1>; 32 status = "disabled"; 33 }; 34 35 mailbox@50000000 { 36 compatible = "microchip,miv-ihc-rtl-v2"; 37 reg = <0x0 0x50000000 0x0 0x1c000>; 38 interrupt-parent = <&plic>; 39 interrupts = <180>, <179>, <178>, <177>; 40 interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; 41 #mbox-cells = <1>; 42 microchip,ihc-chan-disabled-mask = /bits/ 16 <0>; 43 status = "disabled"; 44 }; 45 46 refclk_ccc: clock-cccref { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 }; 50}; 51 52&ccc_sw { 53 clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, 54 <&refclk_ccc>, <&refclk_ccc>; 55 clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", 56 "dll0_ref", "dll1_ref"; 57 status = "okay"; 58}; 59