1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance counter support for Power12 processors. 4 * 5 * Copyright 2026 Athira Rajeev, IBM Corporation. 6 */ 7 8 #define pr_fmt(fmt) "power12-pmu: " fmt 9 10 #include "isa207-common.h" 11 12 /* 13 * Raw event encoding for Power12: 14 * 15 * 60 56 52 48 44 40 36 32 16 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 17 * | | [ ] [ src_match ] [ src_mask ] | [ ] [ l2l3_sel ] [ thresh_ctl ] 18 * | | | | | | 19 * | | *- IFM (Linux) | | thresh start/stop -* 20 * | *- BHRB (Linux) | src_sel 21 * *- EBB (Linux) *invert_bit 22 * 23 * 28 24 20 16 12 8 4 0 24 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 25 * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] | m [ pmcxsel ] 26 * | | | | | | | 27 * | | | | | | *- mark 28 * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual 29 * | | sdar_mode | 30 * | *- sampling mode for marked events *- combine 31 * | 32 * *- thresh_sel 33 * 34 * Below uses IBM bit numbering. 35 * 36 * MMCR1[x:y] = unit (PMCxUNIT) 37 * MMCR1[24] = pmc1combine[0] 38 * MMCR1[25] = pmc1combine[1] 39 * MMCR1[26] = pmc2combine[0] 40 * MMCR1[27] = pmc2combine[1] 41 * MMCR1[28] = pmc3combine[0] 42 * MMCR1[29] = pmc3combine[1] 43 * MMCR1[30] = pmc4combine[0] 44 * MMCR1[31] = pmc4combine[1] 45 * 46 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 47 * MMCR1[20:27] = thresh_ctl 48 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 49 * MMCR1[20:27] = thresh_ctl 50 * else 51 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 52 * 53 * if thresh_sel: 54 * MMCRA[45:47] = thresh_sel 55 * 56 * if l2l3_sel: 57 * MMCR2[56:60] = l2l3_sel[0:4] 58 * 59 * MMCR1[16] = cache_sel[0] 60 * MMCR1[17] = cache_sel[1] 61 * MMCR1[18] = radix_scope_qual 62 * 63 * if mark: 64 * MMCRA[63] = 1 (SAMPLE_ENABLE) 65 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 66 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 67 * 68 * if EBB and BHRB: 69 * MMCRA[32:33] = IFM 70 * 71 * MMCRA[SDAR_MODE] = sdar_mode[0:1] 72 */ 73 74 /* 75 * Some power12 event codes. 76 */ 77 #define EVENT(_name, _code) enum{_name = _code} 78 79 #include "power12-events-list.h" 80 81 #undef EVENT 82 83 /* MMCRA IFM bits - POWER12 */ 84 #define POWER12_MMCRA_IFM1 0x0000000040000000UL 85 #define POWER12_MMCRA_IFM2 0x0000000080000000UL 86 #define POWER12_MMCRA_IFM3 0x00000000C0000000UL 87 #define POWER12_MMCRA_BHRB_MASK 0x00000000C0000000UL 88 89 extern u64 PERF_REG_EXTENDED_MASK; 90 91 /* Table of alternatives, sorted by column 0 */ 92 static const unsigned int power12_event_alternatives[][MAX_ALT] = { 93 { PM_INST_CMPL_ALT, PM_INST_CMPL }, 94 { PM_CYC_ALT, PM_CYC }, 95 }; 96 97 static int power12_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 98 { 99 int num_alt = 0; 100 101 num_alt = isa207_get_alternatives(event, alt, 102 ARRAY_SIZE(power12_event_alternatives), flags, 103 power12_event_alternatives); 104 105 return num_alt; 106 } 107 108 static int power12_check_attr_config(struct perf_event *ev) 109 { 110 u64 val; 111 u64 event = ev->attr.config; 112 113 val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 114 if (val == 0x10 || isa3XX_check_attr_config(ev)) 115 return -EINVAL; 116 117 return 0; 118 } 119 120 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 121 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 122 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_FIN); 123 GENERIC_EVENT_ATTR(branch-misses, PM_MPRED_BR_FIN); 124 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 125 GENERIC_EVENT_ATTR(cache-misses, PM_LD_DEMAND_MISS_L1_FIN); 126 GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS); 127 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES); 128 129 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 130 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 131 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS); 132 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 133 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 134 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 135 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ); 136 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 137 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 138 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PF_MISS_L3); 139 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 140 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 141 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 142 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 143 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 144 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 145 146 static struct attribute *power12_events_attr[] = { 147 GENERIC_EVENT_PTR(PM_CYC), 148 GENERIC_EVENT_PTR(PM_INST_CMPL), 149 GENERIC_EVENT_PTR(PM_BR_FIN), 150 GENERIC_EVENT_PTR(PM_MPRED_BR_FIN), 151 GENERIC_EVENT_PTR(PM_LD_REF_L1), 152 GENERIC_EVENT_PTR(PM_LD_DEMAND_MISS_L1_FIN), 153 GENERIC_EVENT_PTR(MEM_LOADS), 154 GENERIC_EVENT_PTR(MEM_STORES), 155 CACHE_EVENT_PTR(PM_LD_MISS_L1), 156 CACHE_EVENT_PTR(PM_LD_REF_L1), 157 CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS), 158 CACHE_EVENT_PTR(PM_ST_MISS_L1), 159 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 160 CACHE_EVENT_PTR(PM_INST_FROM_L1), 161 CACHE_EVENT_PTR(PM_IC_PREF_REQ), 162 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 163 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 164 CACHE_EVENT_PTR(PM_L3_PF_MISS_L3), 165 CACHE_EVENT_PTR(PM_L2_ST_MISS), 166 CACHE_EVENT_PTR(PM_L2_ST), 167 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 168 CACHE_EVENT_PTR(PM_BR_CMPL), 169 CACHE_EVENT_PTR(PM_DTLB_MISS), 170 CACHE_EVENT_PTR(PM_ITLB_MISS), 171 NULL 172 }; 173 174 static const struct attribute_group power12_pmu_events_group = { 175 .name = "events", 176 .attrs = power12_events_attr, 177 }; 178 179 PMU_FORMAT_ATTR(event, "config:0-59"); 180 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 181 PMU_FORMAT_ATTR(mark, "config:8"); 182 PMU_FORMAT_ATTR(combine, "config:10-11"); 183 PMU_FORMAT_ATTR(unit, "config:12-15"); 184 PMU_FORMAT_ATTR(pmc, "config:16-19"); 185 PMU_FORMAT_ATTR(cache_sel, "config:20-21"); 186 PMU_FORMAT_ATTR(sdar_mode, "config:22-23"); 187 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 188 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 189 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 190 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 191 PMU_FORMAT_ATTR(l2l3_sel, "config:40-44"); 192 PMU_FORMAT_ATTR(src_sel, "config:45-46"); 193 PMU_FORMAT_ATTR(invert_bit, "config:47"); 194 PMU_FORMAT_ATTR(src_mask, "config:48-53"); 195 PMU_FORMAT_ATTR(src_match, "config:54-59"); 196 PMU_FORMAT_ATTR(radix_scope, "config:9"); 197 PMU_FORMAT_ATTR(thresh_cmp, "config1:0-17"); 198 199 static struct attribute *power12_pmu_format_attr[] = { 200 &format_attr_event.attr, 201 &format_attr_pmcxsel.attr, 202 &format_attr_mark.attr, 203 &format_attr_combine.attr, 204 &format_attr_unit.attr, 205 &format_attr_pmc.attr, 206 &format_attr_cache_sel.attr, 207 &format_attr_sdar_mode.attr, 208 &format_attr_sample_mode.attr, 209 &format_attr_thresh_sel.attr, 210 &format_attr_thresh_stop.attr, 211 &format_attr_thresh_start.attr, 212 &format_attr_l2l3_sel.attr, 213 &format_attr_src_sel.attr, 214 &format_attr_invert_bit.attr, 215 &format_attr_src_mask.attr, 216 &format_attr_src_match.attr, 217 &format_attr_radix_scope.attr, 218 &format_attr_thresh_cmp.attr, 219 NULL, 220 }; 221 222 static const struct attribute_group power12_pmu_format_group = { 223 .name = "format", 224 .attrs = power12_pmu_format_attr, 225 }; 226 227 static const struct attribute_group *power12_pmu_attr_groups[] = { 228 &power12_pmu_format_group, 229 &power12_pmu_events_group, 230 NULL, 231 }; 232 233 static int power12_generic_events[] = { 234 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 235 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 236 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_FIN, 237 [PERF_COUNT_HW_BRANCH_MISSES] = PM_MPRED_BR_FIN, 238 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 239 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_DEMAND_MISS_L1_FIN, 240 }; 241 242 static u64 power12_bhrb_filter_map(u64 branch_sample_type) 243 { 244 u64 pmu_bhrb_filter = 0; 245 246 /* BHRB and regular PMU events share the same privilege state 247 * filter configuration. BHRB is always recorded along with a 248 * regular PMU event. As the privilege state filter is handled 249 * in the basic PMC configuration of the accompanying regular 250 * PMU event, we ignore any separate BHRB specific request. 251 */ 252 253 /* No branch filter requested */ 254 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 255 return pmu_bhrb_filter; 256 257 /* Invalid branch filter options - HW does not support */ 258 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 259 return -1; 260 261 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) { 262 pmu_bhrb_filter |= POWER12_MMCRA_IFM2; 263 return pmu_bhrb_filter; 264 } 265 266 if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) { 267 pmu_bhrb_filter |= POWER12_MMCRA_IFM3; 268 return pmu_bhrb_filter; 269 } 270 271 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 272 return -1; 273 274 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 275 pmu_bhrb_filter |= POWER12_MMCRA_IFM1; 276 return pmu_bhrb_filter; 277 } 278 279 /* Every thing else is unsupported */ 280 return -1; 281 } 282 283 static void power12_config_bhrb(u64 pmu_bhrb_filter) 284 { 285 pmu_bhrb_filter &= POWER12_MMCRA_BHRB_MASK; 286 287 /* Enable BHRB filter in PMU */ 288 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 289 } 290 291 #define C(x) PERF_COUNT_HW_CACHE_##x 292 293 /* 294 * Table of generalized cache-related events. 295 * 0 means not supported, -1 means nonsensical, other values 296 * are event codes. 297 */ 298 static u64 power12_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 299 [C(L1D)] = { 300 [C(OP_READ)] = { 301 [C(RESULT_ACCESS)] = PM_LD_REF_L1, 302 [C(RESULT_MISS)] = PM_LD_MISS_L1, 303 }, 304 [C(OP_WRITE)] = { 305 [C(RESULT_ACCESS)] = 0, 306 [C(RESULT_MISS)] = PM_ST_MISS_L1, 307 }, 308 [C(OP_PREFETCH)] = { 309 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS, 310 [C(RESULT_MISS)] = 0, 311 }, 312 }, 313 [C(L1I)] = { 314 [C(OP_READ)] = { 315 [C(RESULT_ACCESS)] = PM_INST_FROM_L1, 316 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS, 317 }, 318 [C(OP_WRITE)] = { 319 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS, 320 [C(RESULT_MISS)] = -1, 321 }, 322 [C(OP_PREFETCH)] = { 323 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ, 324 [C(RESULT_MISS)] = 0, 325 }, 326 }, 327 [C(LL)] = { 328 [C(OP_READ)] = { 329 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3, 330 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS, 331 }, 332 [C(OP_WRITE)] = { 333 [C(RESULT_ACCESS)] = PM_L2_ST, 334 [C(RESULT_MISS)] = PM_L2_ST_MISS, 335 }, 336 [C(OP_PREFETCH)] = { 337 [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3, 338 [C(RESULT_MISS)] = 0, 339 }, 340 }, 341 [C(DTLB)] = { 342 [C(OP_READ)] = { 343 [C(RESULT_ACCESS)] = 0, 344 [C(RESULT_MISS)] = PM_DTLB_MISS, 345 }, 346 [C(OP_WRITE)] = { 347 [C(RESULT_ACCESS)] = -1, 348 [C(RESULT_MISS)] = -1, 349 }, 350 [C(OP_PREFETCH)] = { 351 [C(RESULT_ACCESS)] = -1, 352 [C(RESULT_MISS)] = -1, 353 }, 354 }, 355 [C(ITLB)] = { 356 [C(OP_READ)] = { 357 [C(RESULT_ACCESS)] = 0, 358 [C(RESULT_MISS)] = PM_ITLB_MISS, 359 }, 360 [C(OP_WRITE)] = { 361 [C(RESULT_ACCESS)] = -1, 362 [C(RESULT_MISS)] = -1, 363 }, 364 [C(OP_PREFETCH)] = { 365 [C(RESULT_ACCESS)] = -1, 366 [C(RESULT_MISS)] = -1, 367 }, 368 }, 369 [C(BPU)] = { 370 [C(OP_READ)] = { 371 [C(RESULT_ACCESS)] = PM_BR_CMPL, 372 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL, 373 }, 374 [C(OP_WRITE)] = { 375 [C(RESULT_ACCESS)] = -1, 376 [C(RESULT_MISS)] = -1, 377 }, 378 [C(OP_PREFETCH)] = { 379 [C(RESULT_ACCESS)] = -1, 380 [C(RESULT_MISS)] = -1, 381 }, 382 }, 383 [C(NODE)] = { 384 [C(OP_READ)] = { 385 [C(RESULT_ACCESS)] = -1, 386 [C(RESULT_MISS)] = -1, 387 }, 388 [C(OP_WRITE)] = { 389 [C(RESULT_ACCESS)] = -1, 390 [C(RESULT_MISS)] = -1, 391 }, 392 [C(OP_PREFETCH)] = { 393 [C(RESULT_ACCESS)] = -1, 394 [C(RESULT_MISS)] = -1, 395 }, 396 }, 397 }; 398 399 #undef C 400 401 /* 402 * Set the MMCR0[CC56RUN] bit to enable counting for 403 * PMC5 and PMC6 regardless of the state of CTRL[RUN], 404 * so that we can use counters 5 and 6 as PM_INST_CMPL and 405 * PM_CYC. 406 */ 407 static int power12_compute_mmcr(u64 event[], int n_ev, 408 unsigned int hwc[], struct mmcr_regs *mmcr, 409 struct perf_event *pevents[], u32 flags) 410 { 411 int ret; 412 413 ret = isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags); 414 if (!ret) 415 mmcr->mmcr0 |= MMCR0_C56RUN; 416 return ret; 417 } 418 419 static struct power_pmu power12_pmu = { 420 .name = "Power12", 421 .n_counter = MAX_PMU_COUNTERS, 422 .add_fields = ISA207_ADD_FIELDS, 423 .test_adder = ISA207_TEST_ADDER, 424 .group_constraint_mask = CNST_CACHE_PMC4_MASK, 425 .group_constraint_val = CNST_CACHE_PMC4_VAL, 426 .compute_mmcr = power12_compute_mmcr, 427 .config_bhrb = power12_config_bhrb, 428 .bhrb_filter_map = power12_bhrb_filter_map, 429 .get_constraint = isa207_get_constraint, 430 .get_alternatives = power12_get_alternatives, 431 .get_mem_data_src = isa207_get_mem_data_src, 432 .get_mem_weight = isa207_get_mem_weight, 433 .disable_pmc = isa207_disable_pmc, 434 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S | 435 PPMU_ARCH_31 | PPMU_HAS_ATTR_CONFIG1 | 436 PPMU_P10, 437 .n_generic = ARRAY_SIZE(power12_generic_events), 438 .generic_events = power12_generic_events, 439 .cache_events = &power12_cache_events, 440 .attr_groups = power12_pmu_attr_groups, 441 .bhrb_nr = 32, 442 .capabilities = PERF_PMU_CAP_EXTENDED_REGS, 443 .check_attr_config = power12_check_attr_config, 444 }; 445 446 int __init init_power12_pmu(void) 447 { 448 unsigned int pvr; 449 int rc; 450 451 pvr = mfspr(SPRN_PVR); 452 if (PVR_VER(pvr) != PVR_POWER12) 453 return -ENODEV; 454 455 /* Set the PERF_REG_EXTENDED_MASK here */ 456 PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31; 457 458 rc = register_power_pmu(&power12_pmu); 459 if (rc) 460 return rc; 461 462 /* Tell userspace that EBB is supported */ 463 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 464 465 return 0; 466 } 467