1*aca7cf5bSAthira Rajeev /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*aca7cf5bSAthira Rajeev /* 3*aca7cf5bSAthira Rajeev * Performance counter support for POWER12 processors. 4*aca7cf5bSAthira Rajeev * 5*aca7cf5bSAthira Rajeev * Copyright 2026 Athira Rajeev, IBM Corporation. 6*aca7cf5bSAthira Rajeev */ 7*aca7cf5bSAthira Rajeev 8*aca7cf5bSAthira Rajeev /* 9*aca7cf5bSAthira Rajeev * Power12 event codes. 10*aca7cf5bSAthira Rajeev */ 11*aca7cf5bSAthira Rajeev EVENT(PM_CYC, 0x600f4); 12*aca7cf5bSAthira Rajeev EVENT(PM_DISP_STALL_CYC, 0x100f8); 13*aca7cf5bSAthira Rajeev EVENT(PM_EXEC_STALL, 0x30008); 14*aca7cf5bSAthira Rajeev EVENT(PM_INST_CMPL, 0x500fa); 15*aca7cf5bSAthira Rajeev EVENT(PM_BR_CMPL, 0x4d05e); 16*aca7cf5bSAthira Rajeev EVENT(PM_BR_MPRED_CMPL, 0x400f6); 17*aca7cf5bSAthira Rajeev EVENT(PM_BR_FIN, 0x10068); 18*aca7cf5bSAthira Rajeev EVENT(PM_MPRED_BR_FIN, 0x27098); 19*aca7cf5bSAthira Rajeev EVENT(PM_LD_DEMAND_MISS_L1_FIN, 0x400f0); 20*aca7cf5bSAthira Rajeev 21*aca7cf5bSAthira Rajeev /* All L1 D cache load references counted at finish, gated by reject */ 22*aca7cf5bSAthira Rajeev EVENT(PM_LD_REF_L1, 0x100fc); 23*aca7cf5bSAthira Rajeev /* Load Missed L1 */ 24*aca7cf5bSAthira Rajeev EVENT(PM_LD_MISS_L1, 0x3e054); 25*aca7cf5bSAthira Rajeev /* Store Missed L1 */ 26*aca7cf5bSAthira Rajeev EVENT(PM_ST_MISS_L1, 0x300f0); 27*aca7cf5bSAthira Rajeev /* L1 cache data prefetches */ 28*aca7cf5bSAthira Rajeev EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c); 29*aca7cf5bSAthira Rajeev /* Demand iCache Miss */ 30*aca7cf5bSAthira Rajeev EVENT(PM_L1_ICACHE_MISS, 0x200fc); 31*aca7cf5bSAthira Rajeev /* Instruction fetches from L1 */ 32*aca7cf5bSAthira Rajeev EVENT(PM_INST_FROM_L1, 0x04080); 33*aca7cf5bSAthira Rajeev /* Instruction Demand sectors writtent into IL1 */ 34*aca7cf5bSAthira Rajeev EVENT(PM_INST_FROM_L1MISS, 0x03F00000001C040); 35*aca7cf5bSAthira Rajeev /* Instruction prefetch written into IL1 */ 36*aca7cf5bSAthira Rajeev EVENT(PM_IC_PREF_REQ, 0x040a0); 37*aca7cf5bSAthira Rajeev /* The data cache was reloaded from local core's L3 due to a demand load */ 38*aca7cf5bSAthira Rajeev EVENT(PM_DATA_FROM_L3, 0x10340000003C040); 39*aca7cf5bSAthira Rajeev /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 40*aca7cf5bSAthira Rajeev EVENT(PM_DATA_FROM_L3MISS, 0x300fe); 41*aca7cf5bSAthira Rajeev /* All successful D-side store dispatches for this thread */ 42*aca7cf5bSAthira Rajeev EVENT(PM_L2_ST, 0x010000046080); 43*aca7cf5bSAthira Rajeev /* All successful D-side store dispatches for this thread that were L2 Miss */ 44*aca7cf5bSAthira Rajeev EVENT(PM_L2_ST_MISS, 0x26880); 45*aca7cf5bSAthira Rajeev /* Total HW L3 prefetches(Load+store) */ 46*aca7cf5bSAthira Rajeev EVENT(PM_L3_PF_MISS_L3, 0x100000016080); 47*aca7cf5bSAthira Rajeev /* Data PTEG reload */ 48*aca7cf5bSAthira Rajeev EVENT(PM_DTLB_MISS, 0x300fc); 49*aca7cf5bSAthira Rajeev /* ITLB Reloaded */ 50*aca7cf5bSAthira Rajeev EVENT(PM_ITLB_MISS, 0x400fc); 51*aca7cf5bSAthira Rajeev 52*aca7cf5bSAthira Rajeev EVENT(PM_CYC_ALT, 0x0001e); 53*aca7cf5bSAthira Rajeev EVENT(PM_INST_CMPL_ALT, 0x00002); 54*aca7cf5bSAthira Rajeev 55*aca7cf5bSAthira Rajeev /* 56*aca7cf5bSAthira Rajeev * Memory Access Events 57*aca7cf5bSAthira Rajeev * 58*aca7cf5bSAthira Rajeev * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) 59*aca7cf5bSAthira Rajeev * To enable capturing of memory profiling, these MMCRA bits 60*aca7cf5bSAthira Rajeev * needs to be programmed and corresponding raw event format 61*aca7cf5bSAthira Rajeev * encoding. 62*aca7cf5bSAthira Rajeev * 63*aca7cf5bSAthira Rajeev * MMCRA bits encoding needed are 64*aca7cf5bSAthira Rajeev * SM (Sampling Mode) 65*aca7cf5bSAthira Rajeev * EM (Eligibility for Random Sampling) 66*aca7cf5bSAthira Rajeev * TECE (Threshold Event Counter Event) 67*aca7cf5bSAthira Rajeev * TS (Threshold Start Event) 68*aca7cf5bSAthira Rajeev * TE (Threshold End Event) 69*aca7cf5bSAthira Rajeev * 70*aca7cf5bSAthira Rajeev * Corresponding Raw Encoding bits: 71*aca7cf5bSAthira Rajeev * sample [EM,SM] 72*aca7cf5bSAthira Rajeev * thresh_sel (TECE) 73*aca7cf5bSAthira Rajeev * thresh start (TS) 74*aca7cf5bSAthira Rajeev * thresh end (TE) 75*aca7cf5bSAthira Rajeev */ 76*aca7cf5bSAthira Rajeev 77*aca7cf5bSAthira Rajeev EVENT(MEM_LOADS, 0x35340401e0); 78*aca7cf5bSAthira Rajeev EVENT(MEM_STORES, 0x353c0401e0); 79