1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Performance counter support for POWER12 processors. 4 * 5 * Copyright 2026 Athira Rajeev, IBM Corporation. 6 */ 7 8 /* 9 * Power12 event codes. 10 */ 11 EVENT(PM_CYC, 0x600f4); 12 EVENT(PM_DISP_STALL_CYC, 0x100f8); 13 EVENT(PM_EXEC_STALL, 0x30008); 14 EVENT(PM_INST_CMPL, 0x500fa); 15 EVENT(PM_BR_CMPL, 0x4d05e); 16 EVENT(PM_BR_MPRED_CMPL, 0x400f6); 17 EVENT(PM_BR_FIN, 0x10068); 18 EVENT(PM_MPRED_BR_FIN, 0x27098); 19 EVENT(PM_LD_DEMAND_MISS_L1_FIN, 0x400f0); 20 21 /* All L1 D cache load references counted at finish, gated by reject */ 22 EVENT(PM_LD_REF_L1, 0x100fc); 23 /* Load Missed L1 */ 24 EVENT(PM_LD_MISS_L1, 0x3e054); 25 /* Store Missed L1 */ 26 EVENT(PM_ST_MISS_L1, 0x300f0); 27 /* L1 cache data prefetches */ 28 EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c); 29 /* Demand iCache Miss */ 30 EVENT(PM_L1_ICACHE_MISS, 0x200fc); 31 /* Instruction fetches from L1 */ 32 EVENT(PM_INST_FROM_L1, 0x04080); 33 /* Instruction Demand sectors writtent into IL1 */ 34 EVENT(PM_INST_FROM_L1MISS, 0x03F00000001C040); 35 /* Instruction prefetch written into IL1 */ 36 EVENT(PM_IC_PREF_REQ, 0x040a0); 37 /* The data cache was reloaded from local core's L3 due to a demand load */ 38 EVENT(PM_DATA_FROM_L3, 0x10340000003C040); 39 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 40 EVENT(PM_DATA_FROM_L3MISS, 0x300fe); 41 /* All successful D-side store dispatches for this thread */ 42 EVENT(PM_L2_ST, 0x010000046080); 43 /* All successful D-side store dispatches for this thread that were L2 Miss */ 44 EVENT(PM_L2_ST_MISS, 0x26880); 45 /* Total HW L3 prefetches(Load+store) */ 46 EVENT(PM_L3_PF_MISS_L3, 0x100000016080); 47 /* Data PTEG reload */ 48 EVENT(PM_DTLB_MISS, 0x300fc); 49 /* ITLB Reloaded */ 50 EVENT(PM_ITLB_MISS, 0x400fc); 51 52 EVENT(PM_CYC_ALT, 0x0001e); 53 EVENT(PM_INST_CMPL_ALT, 0x00002); 54 55 /* 56 * Memory Access Events 57 * 58 * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) 59 * To enable capturing of memory profiling, these MMCRA bits 60 * needs to be programmed and corresponding raw event format 61 * encoding. 62 * 63 * MMCRA bits encoding needed are 64 * SM (Sampling Mode) 65 * EM (Eligibility for Random Sampling) 66 * TECE (Threshold Event Counter Event) 67 * TS (Threshold Start Event) 68 * TE (Threshold End Event) 69 * 70 * Corresponding Raw Encoding bits: 71 * sample [EM,SM] 72 * thresh_sel (TECE) 73 * thresh start (TS) 74 * thresh end (TE) 75 */ 76 77 EVENT(MEM_LOADS, 0x35340401e0); 78 EVENT(MEM_STORES, 0x353c0401e0); 79