1/* 2 * Boot code and exception vectors for Book3E processors 3 * 4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <asm/reg.h> 14#include <asm/page.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cputable.h> 18#include <asm/setup.h> 19#include <asm/thread_info.h> 20#include <asm/exception-64e.h> 21#include <asm/bug.h> 22#include <asm/irqflags.h> 23#include <asm/ptrace.h> 24#include <asm/ppc-opcode.h> 25#include <asm/mmu.h> 26 27/* XXX This will ultimately add space for a special exception save 28 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 29 * when taking special interrupts. For now we don't support that, 30 * special interrupts from within a non-standard level will probably 31 * blow you up 32 */ 33#define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE 34 35/* Exception prolog code for all exceptions */ 36#define EXCEPTION_PROLOG(n, type, addition) \ 37 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 38 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 39 std r10,PACA_EX##type+EX_R10(r13); \ 40 std r11,PACA_EX##type+EX_R11(r13); \ 41 mfcr r10; /* save CR */ \ 42 addition; /* additional code for that exc. */ \ 43 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 44 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 45 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 46 type##_SET_KSTACK; /* get special stack if necessary */\ 47 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 48 beq 1f; /* branch around if supervisor */ \ 49 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 501: cmpdi cr1,r1,0; /* check if SP makes sense */ \ 51 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 52 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 53 54/* Exception type-specific macros */ 55#define GEN_SET_KSTACK \ 56 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 57#define SPRN_GEN_SRR0 SPRN_SRR0 58#define SPRN_GEN_SRR1 SPRN_SRR1 59 60#define CRIT_SET_KSTACK \ 61 ld r1,PACA_CRIT_STACK(r13); \ 62 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 63#define SPRN_CRIT_SRR0 SPRN_CSRR0 64#define SPRN_CRIT_SRR1 SPRN_CSRR1 65 66#define DBG_SET_KSTACK \ 67 ld r1,PACA_DBG_STACK(r13); \ 68 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 69#define SPRN_DBG_SRR0 SPRN_DSRR0 70#define SPRN_DBG_SRR1 SPRN_DSRR1 71 72#define MC_SET_KSTACK \ 73 ld r1,PACA_MC_STACK(r13); \ 74 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 75#define SPRN_MC_SRR0 SPRN_MCSRR0 76#define SPRN_MC_SRR1 SPRN_MCSRR1 77 78#define NORMAL_EXCEPTION_PROLOG(n, addition) \ 79 EXCEPTION_PROLOG(n, GEN, addition##_GEN) 80 81#define CRIT_EXCEPTION_PROLOG(n, addition) \ 82 EXCEPTION_PROLOG(n, CRIT, addition##_CRIT) 83 84#define DBG_EXCEPTION_PROLOG(n, addition) \ 85 EXCEPTION_PROLOG(n, DBG, addition##_DBG) 86 87#define MC_EXCEPTION_PROLOG(n, addition) \ 88 EXCEPTION_PROLOG(n, MC, addition##_MC) 89 90 91/* Variants of the "addition" argument for the prolog 92 */ 93#define PROLOG_ADDITION_NONE_GEN 94#define PROLOG_ADDITION_NONE_CRIT 95#define PROLOG_ADDITION_NONE_DBG 96#define PROLOG_ADDITION_NONE_MC 97 98#define PROLOG_ADDITION_MASKABLE_GEN \ 99 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \ 100 cmpwi cr0,r11,0; /* yes -> go out of line */ \ 101 beq masked_interrupt_book3e; 102 103#define PROLOG_ADDITION_2REGS_GEN \ 104 std r14,PACA_EXGEN+EX_R14(r13); \ 105 std r15,PACA_EXGEN+EX_R15(r13) 106 107#define PROLOG_ADDITION_1REG_GEN \ 108 std r14,PACA_EXGEN+EX_R14(r13); 109 110#define PROLOG_ADDITION_2REGS_CRIT \ 111 std r14,PACA_EXCRIT+EX_R14(r13); \ 112 std r15,PACA_EXCRIT+EX_R15(r13) 113 114#define PROLOG_ADDITION_2REGS_DBG \ 115 std r14,PACA_EXDBG+EX_R14(r13); \ 116 std r15,PACA_EXDBG+EX_R15(r13) 117 118#define PROLOG_ADDITION_2REGS_MC \ 119 std r14,PACA_EXMC+EX_R14(r13); \ 120 std r15,PACA_EXMC+EX_R15(r13) 121 122/* Core exception code for all exceptions except TLB misses. 123 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type 124 */ 125#define EXCEPTION_COMMON(n, excf, ints) \ 126 std r0,GPR0(r1); /* save r0 in stackframe */ \ 127 std r2,GPR2(r1); /* save r2 in stackframe */ \ 128 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 129 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 130 std r9,GPR9(r1); /* save r9 in stackframe */ \ 131 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 132 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 133 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \ 134 ld r3,excf+EX_R10(r13); /* get back r10 */ \ 135 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 136 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \ 137 std r12,GPR12(r1); /* save r12 in stackframe */ \ 138 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 139 mflr r6; /* save LR in stackframe */ \ 140 mfctr r7; /* save CTR in stackframe */ \ 141 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 142 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 143 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 144 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \ 145 ld r12,exception_marker@toc(r2); \ 146 li r0,0; \ 147 std r3,GPR10(r1); /* save r10 to stackframe */ \ 148 std r4,GPR11(r1); /* save r11 to stackframe */ \ 149 std r5,GPR13(r1); /* save it to stackframe */ \ 150 std r6,_LINK(r1); \ 151 std r7,_CTR(r1); \ 152 std r8,_XER(r1); \ 153 li r3,(n)+1; /* indicate partial regs in trap */ \ 154 std r9,0(r1); /* store stack frame back link */ \ 155 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 156 std r9,GPR1(r1); /* store stack frame back link */ \ 157 std r11,SOFTE(r1); /* and save it to stackframe */ \ 158 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 159 std r3,_TRAP(r1); /* set trap number */ \ 160 std r0,RESULT(r1); /* clear regs->result */ \ 161 ints; 162 163/* Variants for the "ints" argument */ 164#define INTS_KEEP 165#define INTS_DISABLE_SOFT \ 166 stb r0,PACASOFTIRQEN(r13); /* mark interrupts soft-disabled */ \ 167 TRACE_DISABLE_INTS; 168#define INTS_DISABLE_HARD \ 169 stb r0,PACAHARDIRQEN(r13); /* and hard disabled */ 170#define INTS_DISABLE_ALL \ 171 INTS_DISABLE_SOFT \ 172 INTS_DISABLE_HARD 173 174/* This is called by exceptions that used INTS_KEEP (that is did not clear 175 * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE 176 * to it's previous value 177 * 178 * XXX In the long run, we may want to open-code it in order to separate the 179 * load from the wrtee, thus limiting the latency caused by the dependency 180 * but at this point, I'll favor code clarity until we have a near to final 181 * implementation 182 */ 183#define INTS_RESTORE_HARD \ 184 ld r11,_MSR(r1); \ 185 wrtee r11; 186 187/* XXX FIXME: Restore r14/r15 when necessary */ 188#define BAD_STACK_TRAMPOLINE(n) \ 189exc_##n##_bad_stack: \ 190 li r1,(n); /* get exception number */ \ 191 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 192 b bad_stack_book3e; /* bad stack error */ 193 194#define EXCEPTION_STUB(loc, label) \ 195 . = interrupt_base_book3e + loc; \ 196 nop; /* To make debug interrupts happy */ \ 197 b exc_##label##_book3e; 198 199#define ACK_NONE(r) 200#define ACK_DEC(r) \ 201 lis r,TSR_DIS@h; \ 202 mtspr SPRN_TSR,r 203#define ACK_FIT(r) \ 204 lis r,TSR_FIS@h; \ 205 mtspr SPRN_TSR,r 206 207#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \ 208 START_EXCEPTION(label); \ 209 NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \ 210 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \ 211 ack(r8); \ 212 addi r3,r1,STACK_FRAME_OVERHEAD; \ 213 bl hdlr; \ 214 b .ret_from_except_lite; 215 216/* This value is used to mark exception frames on the stack. */ 217 .section ".toc","aw" 218exception_marker: 219 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 220 221 222/* 223 * And here we have the exception vectors ! 224 */ 225 226 .text 227 .balign 0x1000 228 .globl interrupt_base_book3e 229interrupt_base_book3e: /* fake trap */ 230 /* Note: If real debug exceptions are supported by the HW, the vector 231 * below will have to be patched up to point to an appropriate handler 232 */ 233 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */ 234 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */ 235 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 236 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 237 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 238 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 239 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 240 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 241 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 242 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 243 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 244 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 245 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 246 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 247 EXCEPTION_STUB(0x1c0, data_tlb_miss) 248 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 249 EXCEPTION_STUB(0x280, doorbell) 250 EXCEPTION_STUB(0x2a0, doorbell_crit) 251 252 .globl interrupt_end_book3e 253interrupt_end_book3e: 254 255/* Critical Input Interrupt */ 256 START_EXCEPTION(critical_input); 257 CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE) 258// EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL) 259// bl special_reg_save_crit 260// addi r3,r1,STACK_FRAME_OVERHEAD 261// bl .critical_exception 262// b ret_from_crit_except 263 b . 264 265/* Machine Check Interrupt */ 266 START_EXCEPTION(machine_check); 267 CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE) 268// EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL) 269// bl special_reg_save_mc 270// addi r3,r1,STACK_FRAME_OVERHEAD 271// bl .machine_check_exception 272// b ret_from_mc_except 273 b . 274 275/* Data Storage Interrupt */ 276 START_EXCEPTION(data_storage) 277 NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS) 278 mfspr r14,SPRN_DEAR 279 mfspr r15,SPRN_ESR 280 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP) 281 b storage_fault_common 282 283/* Instruction Storage Interrupt */ 284 START_EXCEPTION(instruction_storage); 285 NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS) 286 li r15,0 287 mr r14,r10 288 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP) 289 b storage_fault_common 290 291/* External Input Interrupt */ 292 MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE) 293 294/* Alignment */ 295 START_EXCEPTION(alignment); 296 NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS) 297 mfspr r14,SPRN_DEAR 298 mfspr r15,SPRN_ESR 299 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP) 300 b alignment_more /* no room, go out of line */ 301 302/* Program Interrupt */ 303 START_EXCEPTION(program); 304 NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG) 305 mfspr r14,SPRN_ESR 306 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT) 307 std r14,_DSISR(r1) 308 addi r3,r1,STACK_FRAME_OVERHEAD 309 ld r14,PACA_EXGEN+EX_R14(r13) 310 bl .save_nvgprs 311 INTS_RESTORE_HARD 312 bl .program_check_exception 313 b .ret_from_except 314 315/* Floating Point Unavailable Interrupt */ 316 START_EXCEPTION(fp_unavailable); 317 NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE) 318 /* we can probably do a shorter exception entry for that one... */ 319 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP) 320 bne 1f /* if from user, just load it up */ 321 bl .save_nvgprs 322 addi r3,r1,STACK_FRAME_OVERHEAD 323 INTS_RESTORE_HARD 324 bl .kernel_fp_unavailable_exception 325 BUG_OPCODE 3261: ld r12,_MSR(r1) 327 bl .load_up_fpu 328 b fast_exception_return 329 330/* Decrementer Interrupt */ 331 MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC) 332 333/* Fixed Interval Timer Interrupt */ 334 MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT) 335 336/* Watchdog Timer Interrupt */ 337 START_EXCEPTION(watchdog); 338 CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE) 339// EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL) 340// bl special_reg_save_crit 341// addi r3,r1,STACK_FRAME_OVERHEAD 342// bl .unknown_exception 343// b ret_from_crit_except 344 b . 345 346/* System Call Interrupt */ 347 START_EXCEPTION(system_call) 348 mr r9,r13 /* keep a copy of userland r13 */ 349 mfspr r11,SPRN_SRR0 /* get return address */ 350 mfspr r12,SPRN_SRR1 /* get previous MSR */ 351 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 352 b system_call_common 353 354/* Auxillary Processor Unavailable Interrupt */ 355 START_EXCEPTION(ap_unavailable); 356 NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE) 357 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP) 358 addi r3,r1,STACK_FRAME_OVERHEAD 359 bl .save_nvgprs 360 INTS_RESTORE_HARD 361 bl .unknown_exception 362 b .ret_from_except 363 364/* Debug exception as a critical interrupt*/ 365 START_EXCEPTION(debug_crit); 366 CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS) 367 368 /* 369 * If there is a single step or branch-taken exception in an 370 * exception entry sequence, it was probably meant to apply to 371 * the code where the exception occurred (since exception entry 372 * doesn't turn off DE automatically). We simulate the effect 373 * of turning off DE on entry to an exception handler by turning 374 * off DE in the CSRR1 value and clearing the debug status. 375 */ 376 377 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 378 andis. r15,r14,DBSR_IC@h 379 beq+ 1f 380 381 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 382 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e) 383 cmpld cr0,r10,r14 384 cmpld cr1,r10,r15 385 blt+ cr0,1f 386 bge+ cr1,1f 387 388 /* here it looks like we got an inappropriate debug exception. */ 389 lis r14,DBSR_IC@h /* clear the IC event */ 390 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 391 mtspr SPRN_DBSR,r14 392 mtspr SPRN_CSRR1,r11 393 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 394 ld r1,PACA_EXCRIT+EX_R1(r13) 395 ld r14,PACA_EXCRIT+EX_R14(r13) 396 ld r15,PACA_EXCRIT+EX_R15(r13) 397 mtcr r10 398 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 399 ld r11,PACA_EXCRIT+EX_R11(r13) 400 mfspr r13,SPRN_SPRG_CRIT_SCRATCH 401 rfci 402 403 /* Normal debug exception */ 404 /* XXX We only handle coming from userspace for now since we can't 405 * quite save properly an interrupted kernel state yet 406 */ 4071: andi. r14,r11,MSR_PR; /* check for userspace again */ 408 beq kernel_dbg_exc; /* if from kernel mode */ 409 410 /* Now we mash up things to make it look like we are coming on a 411 * normal exception 412 */ 413 mfspr r15,SPRN_SPRG_CRIT_SCRATCH 414 mtspr SPRN_SPRG_GEN_SCRATCH,r15 415 mfspr r14,SPRN_DBSR 416 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL) 417 std r14,_DSISR(r1) 418 addi r3,r1,STACK_FRAME_OVERHEAD 419 mr r4,r14 420 ld r14,PACA_EXCRIT+EX_R14(r13) 421 ld r15,PACA_EXCRIT+EX_R15(r13) 422 bl .save_nvgprs 423 bl .DebugException 424 b .ret_from_except 425 426kernel_dbg_exc: 427 b . /* NYI */ 428 429/* Doorbell interrupt */ 430 MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE) 431 432/* Doorbell critical Interrupt */ 433 START_EXCEPTION(doorbell_crit); 434 CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE) 435// EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL) 436// bl special_reg_save_crit 437// addi r3,r1,STACK_FRAME_OVERHEAD 438// bl .doorbell_critical_exception 439// b ret_from_crit_except 440 b . 441 442 443/* 444 * An interrupt came in while soft-disabled; clear EE in SRR1, 445 * clear paca->hard_enabled and return. 446 */ 447masked_interrupt_book3e: 448 mtcr r10 449 stb r11,PACAHARDIRQEN(r13) 450 mfspr r10,SPRN_SRR1 451 rldicl r11,r10,48,1 /* clear MSR_EE */ 452 rotldi r10,r11,16 453 mtspr SPRN_SRR1,r10 454 ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */ 455 ld r11,PACA_EXGEN+EX_R11(r13); 456 mfspr r13,SPRN_SPRG_GEN_SCRATCH; 457 rfi 458 b . 459 460/* 461 * This is called from 0x300 and 0x400 handlers after the prologs with 462 * r14 and r15 containing the fault address and error code, with the 463 * original values stashed away in the PACA 464 */ 465storage_fault_common: 466 std r14,_DAR(r1) 467 std r15,_DSISR(r1) 468 addi r3,r1,STACK_FRAME_OVERHEAD 469 mr r4,r14 470 mr r5,r15 471 ld r14,PACA_EXGEN+EX_R14(r13) 472 ld r15,PACA_EXGEN+EX_R15(r13) 473 INTS_RESTORE_HARD 474 bl .do_page_fault 475 cmpdi r3,0 476 bne- 1f 477 b .ret_from_except_lite 4781: bl .save_nvgprs 479 mr r5,r3 480 addi r3,r1,STACK_FRAME_OVERHEAD 481 ld r4,_DAR(r1) 482 bl .bad_page_fault 483 b .ret_from_except 484 485/* 486 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 487 * continues here. 488 */ 489alignment_more: 490 std r14,_DAR(r1) 491 std r15,_DSISR(r1) 492 addi r3,r1,STACK_FRAME_OVERHEAD 493 ld r14,PACA_EXGEN+EX_R14(r13) 494 ld r15,PACA_EXGEN+EX_R15(r13) 495 bl .save_nvgprs 496 INTS_RESTORE_HARD 497 bl .alignment_exception 498 b .ret_from_except 499 500/* 501 * We branch here from entry_64.S for the last stage of the exception 502 * return code path. MSR:EE is expected to be off at that point 503 */ 504_GLOBAL(exception_return_book3e) 505 b 1f 506 507/* This is the return from load_up_fpu fast path which could do with 508 * less GPR restores in fact, but for now we have a single return path 509 */ 510 .globl fast_exception_return 511fast_exception_return: 512 wrteei 0 5131: mr r0,r13 514 ld r10,_MSR(r1) 515 REST_4GPRS(2, r1) 516 andi. r6,r10,MSR_PR 517 REST_2GPRS(6, r1) 518 beq 1f 519 ACCOUNT_CPU_USER_EXIT(r10, r11) 520 ld r0,GPR13(r1) 521 5221: stdcx. r0,0,r1 /* to clear the reservation */ 523 524 ld r8,_CCR(r1) 525 ld r9,_LINK(r1) 526 ld r10,_CTR(r1) 527 ld r11,_XER(r1) 528 mtcr r8 529 mtlr r9 530 mtctr r10 531 mtxer r11 532 REST_2GPRS(8, r1) 533 ld r10,GPR10(r1) 534 ld r11,GPR11(r1) 535 ld r12,GPR12(r1) 536 mtspr SPRN_SPRG_GEN_SCRATCH,r0 537 538 std r10,PACA_EXGEN+EX_R10(r13); 539 std r11,PACA_EXGEN+EX_R11(r13); 540 ld r10,_NIP(r1) 541 ld r11,_MSR(r1) 542 ld r0,GPR0(r1) 543 ld r1,GPR1(r1) 544 mtspr SPRN_SRR0,r10 545 mtspr SPRN_SRR1,r11 546 ld r10,PACA_EXGEN+EX_R10(r13) 547 ld r11,PACA_EXGEN+EX_R11(r13) 548 mfspr r13,SPRN_SPRG_GEN_SCRATCH 549 rfi 550 551/* 552 * Trampolines used when spotting a bad kernel stack pointer in 553 * the exception entry code. 554 * 555 * TODO: move some bits like SRR0 read to trampoline, pass PACA 556 * index around, etc... to handle crit & mcheck 557 */ 558BAD_STACK_TRAMPOLINE(0x000) 559BAD_STACK_TRAMPOLINE(0x100) 560BAD_STACK_TRAMPOLINE(0x200) 561BAD_STACK_TRAMPOLINE(0x300) 562BAD_STACK_TRAMPOLINE(0x400) 563BAD_STACK_TRAMPOLINE(0x500) 564BAD_STACK_TRAMPOLINE(0x600) 565BAD_STACK_TRAMPOLINE(0x700) 566BAD_STACK_TRAMPOLINE(0x800) 567BAD_STACK_TRAMPOLINE(0x900) 568BAD_STACK_TRAMPOLINE(0x980) 569BAD_STACK_TRAMPOLINE(0x9f0) 570BAD_STACK_TRAMPOLINE(0xa00) 571BAD_STACK_TRAMPOLINE(0xb00) 572BAD_STACK_TRAMPOLINE(0xc00) 573BAD_STACK_TRAMPOLINE(0xd00) 574BAD_STACK_TRAMPOLINE(0xe00) 575BAD_STACK_TRAMPOLINE(0xf00) 576BAD_STACK_TRAMPOLINE(0xf20) 577BAD_STACK_TRAMPOLINE(0x2070) 578BAD_STACK_TRAMPOLINE(0x2080) 579 580 .globl bad_stack_book3e 581bad_stack_book3e: 582 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 583 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 584 ld r1,PACAEMERGSP(r13) 585 subi r1,r1,64+INT_FRAME_SIZE 586 std r10,_NIP(r1) 587 std r11,_MSR(r1) 588 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 589 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 590 std r10,GPR1(r1) 591 std r11,_CCR(r1) 592 mfspr r10,SPRN_DEAR 593 mfspr r11,SPRN_ESR 594 std r10,_DAR(r1) 595 std r11,_DSISR(r1) 596 std r0,GPR0(r1); /* save r0 in stackframe */ \ 597 std r2,GPR2(r1); /* save r2 in stackframe */ \ 598 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 599 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 600 std r9,GPR9(r1); /* save r9 in stackframe */ \ 601 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 602 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 603 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 604 std r3,GPR10(r1); /* save r10 to stackframe */ \ 605 std r4,GPR11(r1); /* save r11 to stackframe */ \ 606 std r12,GPR12(r1); /* save r12 in stackframe */ \ 607 std r5,GPR13(r1); /* save it to stackframe */ \ 608 mflr r10 609 mfctr r11 610 mfxer r12 611 std r10,_LINK(r1) 612 std r11,_CTR(r1) 613 std r12,_XER(r1) 614 SAVE_10GPRS(14,r1) 615 SAVE_8GPRS(24,r1) 616 lhz r12,PACA_TRAP_SAVE(r13) 617 std r12,_TRAP(r1) 618 addi r11,r1,INT_FRAME_SIZE 619 std r11,0(r1) 620 li r12,0 621 std r12,0(r11) 622 ld r2,PACATOC(r13) 6231: addi r3,r1,STACK_FRAME_OVERHEAD 624 bl .kernel_bad_stack 625 b 1b 626 627/* 628 * Setup the initial TLB for a core. This current implementation 629 * assume that whatever we are running off will not conflict with 630 * the new mapping at PAGE_OFFSET. 631 */ 632_GLOBAL(initial_tlb_book3e) 633 634 /* Look for the first TLB with IPROT set */ 635 mfspr r4,SPRN_TLB0CFG 636 andi. r3,r4,TLBnCFG_IPROT 637 lis r3,MAS0_TLBSEL(0)@h 638 bne found_iprot 639 640 mfspr r4,SPRN_TLB1CFG 641 andi. r3,r4,TLBnCFG_IPROT 642 lis r3,MAS0_TLBSEL(1)@h 643 bne found_iprot 644 645 mfspr r4,SPRN_TLB2CFG 646 andi. r3,r4,TLBnCFG_IPROT 647 lis r3,MAS0_TLBSEL(2)@h 648 bne found_iprot 649 650 lis r3,MAS0_TLBSEL(3)@h 651 mfspr r4,SPRN_TLB3CFG 652 /* fall through */ 653 654found_iprot: 655 andi. r5,r4,TLBnCFG_HES 656 bne have_hes 657 658 mflr r8 /* save LR */ 659/* 1. Find the index of the entry we're executing in 660 * 661 * r3 = MAS0_TLBSEL (for the iprot array) 662 * r4 = SPRN_TLBnCFG 663 */ 664 bl invstr /* Find our address */ 665invstr: mflr r6 /* Make it accessible */ 666 mfmsr r7 667 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 668 mfspr r7,SPRN_PID 669 slwi r7,r7,16 670 or r7,r7,r5 671 mtspr SPRN_MAS6,r7 672 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 673 674 mfspr r3,SPRN_MAS0 675 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 676 677 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 678 oris r7,r7,MAS1_IPROT@h 679 mtspr SPRN_MAS1,r7 680 tlbwe 681 682/* 2. Invalidate all entries except the entry we're executing in 683 * 684 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 685 * r4 = SPRN_TLBnCFG 686 * r5 = ESEL of entry we are running in 687 */ 688 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 689 li r6,0 /* Set Entry counter to 0 */ 6901: mr r7,r3 /* Set MAS0(TLBSEL) */ 691 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 692 mtspr SPRN_MAS0,r7 693 tlbre 694 mfspr r7,SPRN_MAS1 695 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 696 cmpw r5,r6 697 beq skpinv /* Dont update the current execution TLB */ 698 mtspr SPRN_MAS1,r7 699 tlbwe 700 isync 701skpinv: addi r6,r6,1 /* Increment */ 702 cmpw r6,r4 /* Are we done? */ 703 bne 1b /* If not, repeat */ 704 705 /* Invalidate all TLBs */ 706 PPC_TLBILX_ALL(0,0) 707 sync 708 isync 709 710/* 3. Setup a temp mapping and jump to it 711 * 712 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 713 * r5 = ESEL of entry we are running in 714 */ 715 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 716 addi r7,r7,0x1 717 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 718 mtspr SPRN_MAS0,r4 719 tlbre 720 721 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 722 mtspr SPRN_MAS0,r4 723 724 mfspr r7,SPRN_MAS1 725 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 726 mtspr SPRN_MAS1,r6 727 728 tlbwe 729 730 mfmsr r6 731 xori r6,r6,MSR_IS 732 mtspr SPRN_SRR1,r6 733 bl 1f /* Find our address */ 7341: mflr r6 735 addi r6,r6,(2f - 1b) 736 mtspr SPRN_SRR0,r6 737 rfi 7382: 739 740/* 4. Clear out PIDs & Search info 741 * 742 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 743 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 744 * r5 = MAS3 745 */ 746 li r6,0 747 mtspr SPRN_MAS6,r6 748 mtspr SPRN_PID,r6 749 750/* 5. Invalidate mapping we started in 751 * 752 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 753 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 754 * r5 = MAS3 755 */ 756 mtspr SPRN_MAS0,r3 757 tlbre 758 mfspr r6,SPRN_MAS1 759 rlwinm r6,r6,0,2,0 /* clear IPROT */ 760 mtspr SPRN_MAS1,r6 761 tlbwe 762 763 /* Invalidate TLB1 */ 764 PPC_TLBILX_ALL(0,0) 765 sync 766 isync 767 768/* The mapping only needs to be cache-coherent on SMP */ 769#ifdef CONFIG_SMP 770#define M_IF_SMP MAS2_M 771#else 772#define M_IF_SMP 0 773#endif 774 775/* 6. Setup KERNELBASE mapping in TLB[0] 776 * 777 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 778 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 779 * r5 = MAS3 780 */ 781 rlwinm r3,r3,0,16,3 /* clear ESEL */ 782 mtspr SPRN_MAS0,r3 783 lis r6,(MAS1_VALID|MAS1_IPROT)@h 784 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 785 mtspr SPRN_MAS1,r6 786 787 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP) 788 mtspr SPRN_MAS2,r6 789 790 rlwinm r5,r5,0,0,25 791 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 792 mtspr SPRN_MAS3,r5 793 li r5,-1 794 rlwinm r5,r5,0,0,25 795 796 tlbwe 797 798/* 7. Jump to KERNELBASE mapping 799 * 800 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 801 */ 802 /* Now we branch the new virtual address mapped by this entry */ 803 LOAD_REG_IMMEDIATE(r6,2f) 804 lis r7,MSR_KERNEL@h 805 ori r7,r7,MSR_KERNEL@l 806 mtspr SPRN_SRR0,r6 807 mtspr SPRN_SRR1,r7 808 rfi /* start execution out of TLB1[0] entry */ 8092: 810 811/* 8. Clear out the temp mapping 812 * 813 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 814 */ 815 mtspr SPRN_MAS0,r4 816 tlbre 817 mfspr r5,SPRN_MAS1 818 rlwinm r5,r5,0,2,0 /* clear IPROT */ 819 mtspr SPRN_MAS1,r5 820 tlbwe 821 822 /* Invalidate TLB1 */ 823 PPC_TLBILX_ALL(0,0) 824 sync 825 isync 826 827 /* We translate LR and return */ 828 tovirt(r8,r8) 829 mtlr r8 830 blr 831 832have_hes: 833 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 834 * kernel linear mapping. We also set MAS8 once for all here though 835 * that will have to be made dependent on whether we are running under 836 * a hypervisor I suppose. 837 */ 838 ori r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS 839 mtspr SPRN_MAS0,r3 840 lis r3,(MAS1_VALID | MAS1_IPROT)@h 841 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 842 mtspr SPRN_MAS1,r3 843 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 844 mtspr SPRN_MAS2,r3 845 li r3,MAS3_SR | MAS3_SW | MAS3_SX 846 mtspr SPRN_MAS7_MAS3,r3 847 li r3,0 848 mtspr SPRN_MAS8,r3 849 850 /* Write the TLB entry */ 851 tlbwe 852 853 /* Now we branch the new virtual address mapped by this entry */ 854 LOAD_REG_IMMEDIATE(r3,1f) 855 mtctr r3 856 bctr 857 8581: /* We are now running at PAGE_OFFSET, clean the TLB of everything 859 * else (XXX we should scan for bolted crap from the firmware too) 860 */ 861 PPC_TLBILX(0,0,0) 862 sync 863 isync 864 865 /* We translate LR and return */ 866 mflr r3 867 tovirt(r3,r3) 868 mtlr r3 869 blr 870 871/* 872 * Main entry (boot CPU, thread 0) 873 * 874 * We enter here from head_64.S, possibly after the prom_init trampoline 875 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 876 * mode. Anything else is as it was left by the bootloader 877 * 878 * Initial requirements of this port: 879 * 880 * - Kernel loaded at 0 physical 881 * - A good lump of memory mapped 0:0 by UTLB entry 0 882 * - MSR:IS & MSR:DS set to 0 883 * 884 * Note that some of the above requirements will be relaxed in the future 885 * as the kernel becomes smarter at dealing with different initial conditions 886 * but for now you have to be careful 887 */ 888_GLOBAL(start_initialization_book3e) 889 mflr r28 890 891 /* First, we need to setup some initial TLBs to map the kernel 892 * text, data and bss at PAGE_OFFSET. We don't have a real mode 893 * and always use AS 0, so we just set it up to match our link 894 * address and never use 0 based addresses. 895 */ 896 bl .initial_tlb_book3e 897 898 /* Init global core bits */ 899 bl .init_core_book3e 900 901 /* Init per-thread bits */ 902 bl .init_thread_book3e 903 904 /* Return to common init code */ 905 tovirt(r28,r28) 906 mtlr r28 907 blr 908 909 910/* 911 * Secondary core/processor entry 912 * 913 * This is entered for thread 0 of a secondary core, all other threads 914 * are expected to be stopped. It's similar to start_initialization_book3e 915 * except that it's generally entered from the holding loop in head_64.S 916 * after CPUs have been gathered by Open Firmware. 917 * 918 * We assume we are in 32 bits mode running with whatever TLB entry was 919 * set for us by the firmware or POR engine. 920 */ 921_GLOBAL(book3e_secondary_core_init_tlb_set) 922 li r4,1 923 b .generic_secondary_smp_init 924 925_GLOBAL(book3e_secondary_core_init) 926 mflr r28 927 928 /* Do we need to setup initial TLB entry ? */ 929 cmplwi r4,0 930 bne 2f 931 932 /* Setup TLB for this core */ 933 bl .initial_tlb_book3e 934 935 /* We can return from the above running at a different 936 * address, so recalculate r2 (TOC) 937 */ 938 bl .relative_toc 939 940 /* Init global core bits */ 9412: bl .init_core_book3e 942 943 /* Init per-thread bits */ 9443: bl .init_thread_book3e 945 946 /* Return to common init code at proper virtual address. 947 * 948 * Due to various previous assumptions, we know we entered this 949 * function at either the final PAGE_OFFSET mapping or using a 950 * 1:1 mapping at 0, so we don't bother doing a complicated check 951 * here, we just ensure the return address has the right top bits. 952 * 953 * Note that if we ever want to be smarter about where we can be 954 * started from, we have to be careful that by the time we reach 955 * the code below we may already be running at a different location 956 * than the one we were called from since initial_tlb_book3e can 957 * have moved us already. 958 */ 959 cmpdi cr0,r28,0 960 blt 1f 961 lis r3,PAGE_OFFSET@highest 962 sldi r3,r3,32 963 or r28,r28,r3 9641: mtlr r28 965 blr 966 967_GLOBAL(book3e_secondary_thread_init) 968 mflr r28 969 b 3b 970 971_STATIC(init_core_book3e) 972 /* Establish the interrupt vector base */ 973 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e) 974 mtspr SPRN_IVPR,r3 975 sync 976 blr 977 978_STATIC(init_thread_book3e) 979 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 980 mtspr SPRN_EPCR,r3 981 982 /* Make sure interrupts are off */ 983 wrteei 0 984 985 /* disable all timers and clear out status */ 986 li r3,0 987 mtspr SPRN_TCR,r3 988 mfspr r3,SPRN_TSR 989 mtspr SPRN_TSR,r3 990 991 blr 992 993_GLOBAL(__setup_base_ivors) 994 SET_IVOR(0, 0x020) /* Critical Input */ 995 SET_IVOR(1, 0x000) /* Machine Check */ 996 SET_IVOR(2, 0x060) /* Data Storage */ 997 SET_IVOR(3, 0x080) /* Instruction Storage */ 998 SET_IVOR(4, 0x0a0) /* External Input */ 999 SET_IVOR(5, 0x0c0) /* Alignment */ 1000 SET_IVOR(6, 0x0e0) /* Program */ 1001 SET_IVOR(7, 0x100) /* FP Unavailable */ 1002 SET_IVOR(8, 0x120) /* System Call */ 1003 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1004 SET_IVOR(10, 0x160) /* Decrementer */ 1005 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1006 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1007 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1008 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1009 SET_IVOR(15, 0x040) /* Debug */ 1010 1011 sync 1012 1013 blr 1014