1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_NOHASH_32_PTE_85xx_H 3 #define _ASM_POWERPC_NOHASH_32_PTE_85xx_H 4 #ifdef __KERNEL__ 5 6 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based 7 * processors 8 * 9 MMU Assist Register 3: 10 11 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 12 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR 13 14 - PRESENT *must* be in the bottom two bits because swap PTEs use 15 the top 30 bits. 16 17 */ 18 19 /* Definitions for FSL Book-E Cores */ 20 #define _PAGE_READ 0x00001 /* H: Read permission (SR) */ 21 #define _PAGE_PRESENT 0x00002 /* S: PTE contains a translation */ 22 #define _PAGE_WRITE 0x00004 /* S: Write permission (SW) */ 23 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */ 24 #define _PAGE_EXEC 0x00010 /* H: SX permission */ 25 #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */ 26 27 #define _PAGE_ENDIAN 0x00040 /* H: E bit */ 28 #define _PAGE_GUARDED 0x00080 /* H: G bit */ 29 #define _PAGE_COHERENT 0x00100 /* H: M bit */ 30 #define _PAGE_NO_CACHE 0x00200 /* H: I bit */ 31 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */ 32 #define _PAGE_SPECIAL 0x00800 /* S: Special page */ 33 34 /* No page size encoding in the linux PTE */ 35 #define _PAGE_PSIZE 0 36 37 #define _PMD_PRESENT 0 38 #define _PMD_PRESENT_MASK (PAGE_MASK) 39 #define _PMD_BAD (~PAGE_MASK) 40 #define _PMD_USER 0 41 42 #define _PTE_NONE_MASK 0 43 44 #define PTE_WIMGE_SHIFT (6) 45 46 /* 47 * We define 2 sets of base prot bits, one for basic pages (ie, 48 * cacheable kernel and user pages) and one for non cacheable 49 * pages. We always set _PAGE_COHERENT when SMP is enabled or 50 * the processor might need it for DMA coherency. 51 */ 52 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 53 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 54 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 55 #else 56 #define _PAGE_BASE (_PAGE_BASE_NC) 57 #endif 58 59 #include <asm/pgtable-masks.h> 60 61 #endif /* __KERNEL__ */ 62 #endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_85xx_H */ 63