1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 #ifndef _ASM_POWERPC_EXCEPTION_H 3 #define _ASM_POWERPC_EXCEPTION_H 4 /* 5 * Extracted from head_64.S 6 * 7 * PowerPC version 8 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 9 * 10 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 11 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 12 * Adapted for Power Macintosh by Paul Mackerras. 13 * Low-level exception handlers and MMU support 14 * rewritten by Paul Mackerras. 15 * Copyright (C) 1996 Paul Mackerras. 16 * 17 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 18 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 19 * 20 * This file contains the low-level support and setup for the 21 * PowerPC-64 platform, including trap and interrupt dispatch. 22 */ 23 /* 24 * The following macros define the code that appears as 25 * the prologue to each of the exception handlers. They 26 * are split into two parts to allow a single kernel binary 27 * to be used for pSeries and iSeries. 28 * 29 * We make as much of the exception code common between native 30 * exception handlers (including pSeries LPAR) and iSeries LPAR 31 * implementations as possible. 32 */ 33 #include <asm/head-64.h> 34 #include <asm/feature-fixups.h> 35 36 /* PACA save area offsets (exgen, exmc, etc) */ 37 #define EX_R9 0 38 #define EX_R10 8 39 #define EX_R11 16 40 #define EX_R12 24 41 #define EX_R13 32 42 #define EX_DAR 40 43 #define EX_DSISR 48 44 #define EX_CCR 52 45 #define EX_CFAR 56 46 #define EX_PPR 64 47 #if defined(CONFIG_RELOCATABLE) 48 #define EX_CTR 72 49 #define EX_SIZE 10 /* size in u64 units */ 50 #else 51 #define EX_SIZE 9 /* size in u64 units */ 52 #endif 53 54 /* 55 * maximum recursive depth of MCE exceptions 56 */ 57 #define MAX_MCE_DEPTH 4 58 59 /* 60 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 61 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 62 * with EX_DAR. 63 */ 64 #define EX_R3 EX_DAR 65 66 #define STF_ENTRY_BARRIER_SLOT \ 67 STF_ENTRY_BARRIER_FIXUP_SECTION; \ 68 nop; \ 69 nop; \ 70 nop 71 72 #define STF_EXIT_BARRIER_SLOT \ 73 STF_EXIT_BARRIER_FIXUP_SECTION; \ 74 nop; \ 75 nop; \ 76 nop; \ 77 nop; \ 78 nop; \ 79 nop 80 81 /* 82 * r10 must be free to use, r13 must be paca 83 */ 84 #define INTERRUPT_TO_KERNEL \ 85 STF_ENTRY_BARRIER_SLOT 86 87 /* 88 * Macros for annotating the expected destination of (h)rfid 89 * 90 * The nop instructions allow us to insert one or more instructions to flush the 91 * L1-D cache when returning to userspace or a guest. 92 */ 93 #define RFI_FLUSH_SLOT \ 94 RFI_FLUSH_FIXUP_SECTION; \ 95 nop; \ 96 nop; \ 97 nop 98 99 #define RFI_TO_KERNEL \ 100 rfid 101 102 #define RFI_TO_USER \ 103 STF_EXIT_BARRIER_SLOT; \ 104 RFI_FLUSH_SLOT; \ 105 rfid; \ 106 b rfi_flush_fallback 107 108 #define RFI_TO_USER_OR_KERNEL \ 109 STF_EXIT_BARRIER_SLOT; \ 110 RFI_FLUSH_SLOT; \ 111 rfid; \ 112 b rfi_flush_fallback 113 114 #define RFI_TO_GUEST \ 115 STF_EXIT_BARRIER_SLOT; \ 116 RFI_FLUSH_SLOT; \ 117 rfid; \ 118 b rfi_flush_fallback 119 120 #define HRFI_TO_KERNEL \ 121 hrfid 122 123 #define HRFI_TO_USER \ 124 STF_EXIT_BARRIER_SLOT; \ 125 RFI_FLUSH_SLOT; \ 126 hrfid; \ 127 b hrfi_flush_fallback 128 129 #define HRFI_TO_USER_OR_KERNEL \ 130 STF_EXIT_BARRIER_SLOT; \ 131 RFI_FLUSH_SLOT; \ 132 hrfid; \ 133 b hrfi_flush_fallback 134 135 #define HRFI_TO_GUEST \ 136 STF_EXIT_BARRIER_SLOT; \ 137 RFI_FLUSH_SLOT; \ 138 hrfid; \ 139 b hrfi_flush_fallback 140 141 #define HRFI_TO_UNKNOWN \ 142 STF_EXIT_BARRIER_SLOT; \ 143 RFI_FLUSH_SLOT; \ 144 hrfid; \ 145 b hrfi_flush_fallback 146 147 #ifdef CONFIG_RELOCATABLE 148 #define __EXCEPTION_PROLOG_2_RELON(label, h) \ 149 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 150 LOAD_HANDLER(r12,label); \ 151 mtctr r12; \ 152 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 153 li r10,MSR_RI; \ 154 mtmsrd r10,1; /* Set RI (EE=0) */ \ 155 bctr; 156 #else 157 /* If not relocatable, we can jump directly -- and save messing with LR */ 158 #define __EXCEPTION_PROLOG_2_RELON(label, h) \ 159 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 160 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 161 li r10,MSR_RI; \ 162 mtmsrd r10,1; /* Set RI (EE=0) */ \ 163 b label; 164 #endif 165 #define EXCEPTION_PROLOG_2_RELON(label, h) \ 166 __EXCEPTION_PROLOG_2_RELON(label, h) 167 168 /* 169 * As EXCEPTION_PROLOG(), except we've already got relocation on so no need to 170 * rfid. Save LR in case we're CONFIG_RELOCATABLE, in which case 171 * EXCEPTION_PROLOG_2_RELON will be using LR. 172 */ 173 #define EXCEPTION_RELON_PROLOG(area, label, h, extra, vec) \ 174 SET_SCRATCH0(r13); /* save r13 */ \ 175 EXCEPTION_PROLOG_0(area); \ 176 EXCEPTION_PROLOG_1(area, extra, vec); \ 177 EXCEPTION_PROLOG_2_RELON(label, h) 178 179 /* 180 * We're short on space and time in the exception prolog, so we can't 181 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 182 * Instead we get the base of the kernel from paca->kernelbase and or in the low 183 * part of label. This requires that the label be within 64KB of kernelbase, and 184 * that kernelbase be 64K aligned. 185 */ 186 #define LOAD_HANDLER(reg, label) \ 187 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 188 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 189 190 #define __LOAD_HANDLER(reg, label) \ 191 ld reg,PACAKBASE(r13); \ 192 ori reg,reg,(ABS_ADDR(label))@l; 193 194 /* 195 * Branches from unrelocated code (e.g., interrupts) to labels outside 196 * head-y require >64K offsets. 197 */ 198 #define __LOAD_FAR_HANDLER(reg, label) \ 199 ld reg,PACAKBASE(r13); \ 200 ori reg,reg,(ABS_ADDR(label))@l; \ 201 addis reg,reg,(ABS_ADDR(label))@h; 202 203 /* Exception register prefixes */ 204 #define EXC_HV H 205 #define EXC_STD 206 207 #if defined(CONFIG_RELOCATABLE) 208 /* 209 * If we support interrupts with relocation on AND we're a relocatable kernel, 210 * we need to use CTR to get to the 2nd level handler. So, save/restore it 211 * when required. 212 */ 213 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 214 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 215 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 216 #else 217 /* ...else CTR is unused and in register. */ 218 #define SAVE_CTR(reg, area) 219 #define GET_CTR(reg, area) mfctr reg 220 #define RESTORE_CTR(reg, area) 221 #endif 222 223 /* 224 * PPR save/restore macros used in exceptions_64s.S 225 * Used for P7 or later processors 226 */ 227 #define SAVE_PPR(area, ra) \ 228 BEGIN_FTR_SECTION_NESTED(940) \ 229 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ 230 std ra,_PPR(r1); \ 231 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 232 233 #define RESTORE_PPR_PACA(area, ra) \ 234 BEGIN_FTR_SECTION_NESTED(941) \ 235 ld ra,area+EX_PPR(r13); \ 236 mtspr SPRN_PPR,ra; \ 237 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 238 239 /* 240 * Get an SPR into a register if the CPU has the given feature 241 */ 242 #define OPT_GET_SPR(ra, spr, ftr) \ 243 BEGIN_FTR_SECTION_NESTED(943) \ 244 mfspr ra,spr; \ 245 END_FTR_SECTION_NESTED(ftr,ftr,943) 246 247 /* 248 * Set an SPR from a register if the CPU has the given feature 249 */ 250 #define OPT_SET_SPR(ra, spr, ftr) \ 251 BEGIN_FTR_SECTION_NESTED(943) \ 252 mtspr spr,ra; \ 253 END_FTR_SECTION_NESTED(ftr,ftr,943) 254 255 /* 256 * Save a register to the PACA if the CPU has the given feature 257 */ 258 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 259 BEGIN_FTR_SECTION_NESTED(943) \ 260 std ra,offset(r13); \ 261 END_FTR_SECTION_NESTED(ftr,ftr,943) 262 263 #define EXCEPTION_PROLOG_0(area) \ 264 GET_PACA(r13); \ 265 std r9,area+EX_R9(r13); /* save r9 */ \ 266 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 267 HMT_MEDIUM; \ 268 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 269 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 270 271 #define __EXCEPTION_PROLOG_1_PRE(area) \ 272 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 273 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 274 INTERRUPT_TO_KERNEL; \ 275 SAVE_CTR(r10, area); \ 276 mfcr r9; 277 278 #define __EXCEPTION_PROLOG_1_POST(area) \ 279 std r11,area+EX_R11(r13); \ 280 std r12,area+EX_R12(r13); \ 281 GET_SCRATCH0(r10); \ 282 std r10,area+EX_R13(r13) 283 284 /* 285 * This version of the EXCEPTION_PROLOG_1 will carry 286 * addition parameter called "bitmask" to support 287 * checking of the interrupt maskable level in the SOFTEN_TEST. 288 * Intended to be used in MASKABLE_EXCPETION_* macros. 289 */ 290 #define MASKABLE_EXCEPTION_PROLOG_1(area, extra, vec, bitmask) \ 291 __EXCEPTION_PROLOG_1_PRE(area); \ 292 extra(vec, bitmask); \ 293 __EXCEPTION_PROLOG_1_POST(area); 294 295 /* 296 * This version of the EXCEPTION_PROLOG_1 is intended 297 * to be used in STD_EXCEPTION* macros 298 */ 299 #define _EXCEPTION_PROLOG_1(area, extra, vec) \ 300 __EXCEPTION_PROLOG_1_PRE(area); \ 301 extra(vec); \ 302 __EXCEPTION_PROLOG_1_POST(area); 303 304 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 305 _EXCEPTION_PROLOG_1(area, extra, vec) 306 307 #define __EXCEPTION_PROLOG_2(label, h) \ 308 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 309 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 310 LOAD_HANDLER(r12,label) \ 311 mtspr SPRN_##h##SRR0,r12; \ 312 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 313 mtspr SPRN_##h##SRR1,r10; \ 314 h##RFI_TO_KERNEL; \ 315 b . /* prevent speculative execution */ 316 #define EXCEPTION_PROLOG_2(label, h) \ 317 __EXCEPTION_PROLOG_2(label, h) 318 319 /* _NORI variant keeps MSR_RI clear */ 320 #define __EXCEPTION_PROLOG_2_NORI(label, h) \ 321 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 322 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 323 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 324 LOAD_HANDLER(r12,label) \ 325 mtspr SPRN_##h##SRR0,r12; \ 326 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 327 mtspr SPRN_##h##SRR1,r10; \ 328 h##RFI_TO_KERNEL; \ 329 b . /* prevent speculative execution */ 330 331 #define EXCEPTION_PROLOG_2_NORI(label, h) \ 332 __EXCEPTION_PROLOG_2_NORI(label, h) 333 334 #define EXCEPTION_PROLOG(area, label, h, extra, vec) \ 335 SET_SCRATCH0(r13); /* save r13 */ \ 336 EXCEPTION_PROLOG_0(area); \ 337 EXCEPTION_PROLOG_1(area, extra, vec); \ 338 EXCEPTION_PROLOG_2(label, h); 339 340 #define __KVMTEST(h, n) \ 341 lbz r10,HSTATE_IN_GUEST(r13); \ 342 cmpwi r10,0; \ 343 bne do_kvm_##h##n 344 345 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 346 /* 347 * If hv is possible, interrupts come into to the hv version 348 * of the kvmppc_interrupt code, which then jumps to the PR handler, 349 * kvmppc_interrupt_pr, if the guest is a PR guest. 350 */ 351 #define kvmppc_interrupt kvmppc_interrupt_hv 352 #else 353 #define kvmppc_interrupt kvmppc_interrupt_pr 354 #endif 355 356 /* 357 * Branch to label using its 0xC000 address. This results in instruction 358 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 359 * on using mtmsr rather than rfid. 360 * 361 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 362 * load KBASE for a slight optimisation. 363 */ 364 #define BRANCH_TO_C000(reg, label) \ 365 __LOAD_HANDLER(reg, label); \ 366 mtctr reg; \ 367 bctr 368 369 #ifdef CONFIG_RELOCATABLE 370 #define BRANCH_TO_COMMON(reg, label) \ 371 __LOAD_HANDLER(reg, label); \ 372 mtctr reg; \ 373 bctr 374 375 #define BRANCH_LINK_TO_FAR(label) \ 376 __LOAD_FAR_HANDLER(r12, label); \ 377 mtctr r12; \ 378 bctrl 379 380 /* 381 * KVM requires __LOAD_FAR_HANDLER. 382 * 383 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 384 * explicitly use r9 then reload it from PACA before branching. Hence 385 * the double-underscore. 386 */ 387 #define __BRANCH_TO_KVM_EXIT(area, label) \ 388 mfctr r9; \ 389 std r9,HSTATE_SCRATCH1(r13); \ 390 __LOAD_FAR_HANDLER(r9, label); \ 391 mtctr r9; \ 392 ld r9,area+EX_R9(r13); \ 393 bctr 394 395 #else 396 #define BRANCH_TO_COMMON(reg, label) \ 397 b label 398 399 #define BRANCH_LINK_TO_FAR(label) \ 400 bl label 401 402 #define __BRANCH_TO_KVM_EXIT(area, label) \ 403 ld r9,area+EX_R9(r13); \ 404 b label 405 406 #endif 407 408 /* Do not enable RI */ 409 #define EXCEPTION_PROLOG_NORI(area, label, h, extra, vec) \ 410 EXCEPTION_PROLOG_0(area); \ 411 EXCEPTION_PROLOG_1(area, extra, vec); \ 412 EXCEPTION_PROLOG_2_NORI(label, h); 413 414 415 #define __KVM_HANDLER(area, h, n) \ 416 BEGIN_FTR_SECTION_NESTED(947) \ 417 ld r10,area+EX_CFAR(r13); \ 418 std r10,HSTATE_CFAR(r13); \ 419 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 420 BEGIN_FTR_SECTION_NESTED(948) \ 421 ld r10,area+EX_PPR(r13); \ 422 std r10,HSTATE_PPR(r13); \ 423 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 424 ld r10,area+EX_R10(r13); \ 425 std r12,HSTATE_SCRATCH0(r13); \ 426 sldi r12,r9,32; \ 427 ori r12,r12,(n); \ 428 /* This reloads r9 before branching to kvmppc_interrupt */ \ 429 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 430 431 #define __KVM_HANDLER_SKIP(area, h, n) \ 432 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 433 beq 89f; \ 434 BEGIN_FTR_SECTION_NESTED(948) \ 435 ld r10,area+EX_PPR(r13); \ 436 std r10,HSTATE_PPR(r13); \ 437 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 438 ld r10,area+EX_R10(r13); \ 439 std r12,HSTATE_SCRATCH0(r13); \ 440 sldi r12,r9,32; \ 441 ori r12,r12,(n); \ 442 /* This reloads r9 before branching to kvmppc_interrupt */ \ 443 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 444 89: mtocrf 0x80,r9; \ 445 ld r9,area+EX_R9(r13); \ 446 ld r10,area+EX_R10(r13); \ 447 b kvmppc_skip_##h##interrupt 448 449 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 450 #define KVMTEST(h, n) __KVMTEST(h, n) 451 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 452 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 453 454 #else 455 #define KVMTEST(h, n) 456 #define KVM_HANDLER(area, h, n) 457 #define KVM_HANDLER_SKIP(area, h, n) 458 #endif 459 460 #define NOTEST(n) 461 462 #define EXCEPTION_PROLOG_COMMON_1() \ 463 std r9,_CCR(r1); /* save CR in stackframe */ \ 464 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 465 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 466 std r10,0(r1); /* make stack chain pointer */ \ 467 std r0,GPR0(r1); /* save r0 in stackframe */ \ 468 std r10,GPR1(r1); /* save r1 in stackframe */ \ 469 470 471 /* 472 * The common exception prolog is used for all except a few exceptions 473 * such as a segment miss on a kernel address. We have to be prepared 474 * to take another exception from the point where we first touch the 475 * kernel stack onwards. 476 * 477 * On entry r13 points to the paca, r9-r13 are saved in the paca, 478 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 479 * SRR1, and relocation is on. 480 */ 481 #define EXCEPTION_PROLOG_COMMON(n, area) \ 482 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 483 mr r10,r1; /* Save r1 */ \ 484 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 485 beq- 1f; \ 486 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 487 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 488 blt+ cr1,3f; /* abort if it is */ \ 489 li r1,(n); /* will be reloaded later */ \ 490 sth r1,PACA_TRAP_SAVE(r13); \ 491 std r3,area+EX_R3(r13); \ 492 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 493 RESTORE_CTR(r1, area); \ 494 b bad_stack; \ 495 3: EXCEPTION_PROLOG_COMMON_1(); \ 496 kuap_save_amr_and_lock r9, r10, cr1, cr0; \ 497 beq 4f; /* if from kernel mode */ \ 498 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 499 SAVE_PPR(area, r9); \ 500 4: EXCEPTION_PROLOG_COMMON_2(area) \ 501 EXCEPTION_PROLOG_COMMON_3(n) \ 502 ACCOUNT_STOLEN_TIME 503 504 /* Save original regs values from save area to stack frame. */ 505 #define EXCEPTION_PROLOG_COMMON_2(area) \ 506 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 507 ld r10,area+EX_R10(r13); \ 508 std r9,GPR9(r1); \ 509 std r10,GPR10(r1); \ 510 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 511 ld r10,area+EX_R12(r13); \ 512 ld r11,area+EX_R13(r13); \ 513 std r9,GPR11(r1); \ 514 std r10,GPR12(r1); \ 515 std r11,GPR13(r1); \ 516 BEGIN_FTR_SECTION_NESTED(66); \ 517 ld r10,area+EX_CFAR(r13); \ 518 std r10,ORIG_GPR3(r1); \ 519 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 520 GET_CTR(r10, area); \ 521 std r10,_CTR(r1); 522 523 #define EXCEPTION_PROLOG_COMMON_3(n) \ 524 std r2,GPR2(r1); /* save r2 in stackframe */ \ 525 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 526 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 527 mflr r9; /* Get LR, later save to stack */ \ 528 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 529 std r9,_LINK(r1); \ 530 lbz r10,PACAIRQSOFTMASK(r13); \ 531 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 532 std r10,SOFTE(r1); \ 533 std r11,_XER(r1); \ 534 li r9,(n)+1; \ 535 std r9,_TRAP(r1); /* set trap number */ \ 536 li r10,0; \ 537 ld r11,exception_marker@toc(r2); \ 538 std r10,RESULT(r1); /* clear regs->result */ \ 539 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 540 541 /* 542 * Exception vectors. 543 */ 544 #define STD_EXCEPTION(vec, label) \ 545 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_STD, KVMTEST_PR, vec); 546 547 /* Version of above for when we have to branch out-of-line */ 548 #define __OOL_EXCEPTION(vec, label, hdlr) \ 549 SET_SCRATCH0(r13) \ 550 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 551 b hdlr; 552 553 #define STD_EXCEPTION_OOL(vec, label) \ 554 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 555 EXCEPTION_PROLOG_2(label, EXC_STD) 556 557 #define STD_EXCEPTION_HV(loc, vec, label) \ 558 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec); 559 560 #define STD_EXCEPTION_HV_OOL(vec, label) \ 561 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 562 EXCEPTION_PROLOG_2(label, EXC_HV) 563 564 #define STD_RELON_EXCEPTION(loc, vec, label) \ 565 /* No guest interrupts come through here */ \ 566 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 567 568 #define STD_RELON_EXCEPTION_OOL(vec, label) \ 569 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 570 EXCEPTION_PROLOG_2_RELON(label, EXC_STD) 571 572 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 573 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec); 574 575 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 576 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 577 EXCEPTION_PROLOG_2_RELON(label, EXC_HV) 578 579 /* This associate vector numbers with bits in paca->irq_happened */ 580 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 581 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 582 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 583 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 584 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 585 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 586 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 587 #define SOFTEN_VALUE_0xf00 PACA_IRQ_PMI 588 589 #define __SOFTEN_TEST(h, vec, bitmask) \ 590 lbz r10,PACAIRQSOFTMASK(r13); \ 591 andi. r10,r10,bitmask; \ 592 li r10,SOFTEN_VALUE_##vec; \ 593 bne masked_##h##interrupt 594 595 #define _SOFTEN_TEST(h, vec, bitmask) __SOFTEN_TEST(h, vec, bitmask) 596 597 #define SOFTEN_TEST_PR(vec, bitmask) \ 598 KVMTEST(EXC_STD, vec); \ 599 _SOFTEN_TEST(EXC_STD, vec, bitmask) 600 601 #define SOFTEN_TEST_HV(vec, bitmask) \ 602 KVMTEST(EXC_HV, vec); \ 603 _SOFTEN_TEST(EXC_HV, vec, bitmask) 604 605 #define KVMTEST_PR(vec) \ 606 KVMTEST(EXC_STD, vec) 607 608 #define KVMTEST_HV(vec) \ 609 KVMTEST(EXC_HV, vec) 610 611 #define SOFTEN_NOTEST_PR(vec, bitmask) _SOFTEN_TEST(EXC_STD, vec, bitmask) 612 #define SOFTEN_NOTEST_HV(vec, bitmask) _SOFTEN_TEST(EXC_HV, vec, bitmask) 613 614 #define __MASKABLE_EXCEPTION(vec, label, h, extra, bitmask) \ 615 SET_SCRATCH0(r13); /* save r13 */ \ 616 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 617 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 618 EXCEPTION_PROLOG_2(label, h); 619 620 #define MASKABLE_EXCEPTION(vec, label, bitmask) \ 621 __MASKABLE_EXCEPTION(vec, label, EXC_STD, SOFTEN_TEST_PR, bitmask) 622 623 #define MASKABLE_EXCEPTION_OOL(vec, label, bitmask) \ 624 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec, bitmask);\ 625 EXCEPTION_PROLOG_2(label, EXC_STD) 626 627 #define MASKABLE_EXCEPTION_HV(vec, label, bitmask) \ 628 __MASKABLE_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask) 629 630 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \ 631 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 632 EXCEPTION_PROLOG_2(label, EXC_HV) 633 634 #define __MASKABLE_RELON_EXCEPTION(vec, label, h, extra, bitmask) \ 635 SET_SCRATCH0(r13); /* save r13 */ \ 636 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 637 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 638 EXCEPTION_PROLOG_2_RELON(label, h) 639 640 #define MASKABLE_RELON_EXCEPTION(vec, label, bitmask) \ 641 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_STD, SOFTEN_NOTEST_PR, bitmask) 642 643 #define MASKABLE_RELON_EXCEPTION_OOL(vec, label, bitmask) \ 644 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_PR, vec, bitmask);\ 645 EXCEPTION_PROLOG_2(label, EXC_STD); 646 647 #define MASKABLE_RELON_EXCEPTION_HV(vec, label, bitmask) \ 648 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask) 649 650 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \ 651 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 652 EXCEPTION_PROLOG_2_RELON(label, EXC_HV) 653 654 /* 655 * Our exception common code can be passed various "additions" 656 * to specify the behaviour of interrupts, whether to kick the 657 * runlatch, etc... 658 */ 659 660 /* 661 * This addition reconciles our actual IRQ state with the various software 662 * flags that track it. This may call C code. 663 */ 664 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 665 666 #define ADD_NVGPRS \ 667 bl save_nvgprs 668 669 #define RUNLATCH_ON \ 670 BEGIN_FTR_SECTION \ 671 ld r3, PACA_THREAD_INFO(r13); \ 672 ld r4,TI_LOCAL_FLAGS(r3); \ 673 andi. r0,r4,_TLF_RUNLATCH; \ 674 beql ppc64_runlatch_on_trampoline; \ 675 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 676 677 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 678 EXCEPTION_PROLOG_COMMON(trap, area); \ 679 /* Volatile regs are potentially clobbered here */ \ 680 additions; \ 681 addi r3,r1,STACK_FRAME_OVERHEAD; \ 682 bl hdlr; \ 683 b ret 684 685 /* 686 * Exception where stack is already set in r1, r1 is saved in r10, and it 687 * continues rather than returns. 688 */ 689 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 690 EXCEPTION_PROLOG_COMMON_1(); \ 691 kuap_save_amr_and_lock r9, r10, cr1; \ 692 EXCEPTION_PROLOG_COMMON_2(area); \ 693 EXCEPTION_PROLOG_COMMON_3(trap); \ 694 /* Volatile regs are potentially clobbered here */ \ 695 additions; \ 696 addi r3,r1,STACK_FRAME_OVERHEAD; \ 697 bl hdlr 698 699 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 700 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 701 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 702 703 /* 704 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 705 * in the idle task and therefore need the special idle handling 706 * (finish nap and runlatch) 707 */ 708 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 709 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 710 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 711 712 /* 713 * When the idle code in power4_idle puts the CPU into NAP mode, 714 * it has to do so in a loop, and relies on the external interrupt 715 * and decrementer interrupt entry code to get it out of the loop. 716 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 717 * to signal that it is in the loop and needs help to get out. 718 */ 719 #ifdef CONFIG_PPC_970_NAP 720 #define FINISH_NAP \ 721 BEGIN_FTR_SECTION \ 722 ld r11, PACA_THREAD_INFO(r13); \ 723 ld r9,TI_LOCAL_FLAGS(r11); \ 724 andi. r10,r9,_TLF_NAPPING; \ 725 bnel power4_fixup_nap; \ 726 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 727 #else 728 #define FINISH_NAP 729 #endif 730 731 #endif /* _ASM_POWERPC_EXCEPTION_H */ 732