1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 #include <asm/feature-fixups.h> 39 40 /* PACA save area offsets (exgen, exmc, etc) */ 41 #define EX_R9 0 42 #define EX_R10 8 43 #define EX_R11 16 44 #define EX_R12 24 45 #define EX_R13 32 46 #define EX_DAR 40 47 #define EX_DSISR 48 48 #define EX_CCR 52 49 #define EX_CFAR 56 50 #define EX_PPR 64 51 #if defined(CONFIG_RELOCATABLE) 52 #define EX_CTR 72 53 #define EX_SIZE 10 /* size in u64 units */ 54 #else 55 #define EX_SIZE 9 /* size in u64 units */ 56 #endif 57 58 /* 59 * maximum recursive depth of MCE exceptions 60 */ 61 #define MAX_MCE_DEPTH 4 62 63 /* 64 * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR 65 * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole 66 * in the save area so it's not necessary to overlap them. Could be used 67 * for future savings though if another 4 byte register was to be saved. 68 */ 69 #define EX_LR EX_DAR 70 71 /* 72 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and 73 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap 74 * with EX_DAR. 75 */ 76 #define EX_R3 EX_DAR 77 78 #define STF_ENTRY_BARRIER_SLOT \ 79 STF_ENTRY_BARRIER_FIXUP_SECTION; \ 80 nop; \ 81 nop; \ 82 nop 83 84 #define STF_EXIT_BARRIER_SLOT \ 85 STF_EXIT_BARRIER_FIXUP_SECTION; \ 86 nop; \ 87 nop; \ 88 nop; \ 89 nop; \ 90 nop; \ 91 nop 92 93 /* 94 * r10 must be free to use, r13 must be paca 95 */ 96 #define INTERRUPT_TO_KERNEL \ 97 STF_ENTRY_BARRIER_SLOT 98 99 /* 100 * Macros for annotating the expected destination of (h)rfid 101 * 102 * The nop instructions allow us to insert one or more instructions to flush the 103 * L1-D cache when returning to userspace or a guest. 104 */ 105 #define RFI_FLUSH_SLOT \ 106 RFI_FLUSH_FIXUP_SECTION; \ 107 nop; \ 108 nop; \ 109 nop 110 111 #define RFI_TO_KERNEL \ 112 rfid 113 114 #define RFI_TO_USER \ 115 STF_EXIT_BARRIER_SLOT; \ 116 RFI_FLUSH_SLOT; \ 117 rfid; \ 118 b rfi_flush_fallback 119 120 #define RFI_TO_USER_OR_KERNEL \ 121 STF_EXIT_BARRIER_SLOT; \ 122 RFI_FLUSH_SLOT; \ 123 rfid; \ 124 b rfi_flush_fallback 125 126 #define RFI_TO_GUEST \ 127 STF_EXIT_BARRIER_SLOT; \ 128 RFI_FLUSH_SLOT; \ 129 rfid; \ 130 b rfi_flush_fallback 131 132 #define HRFI_TO_KERNEL \ 133 hrfid 134 135 #define HRFI_TO_USER \ 136 STF_EXIT_BARRIER_SLOT; \ 137 RFI_FLUSH_SLOT; \ 138 hrfid; \ 139 b hrfi_flush_fallback 140 141 #define HRFI_TO_USER_OR_KERNEL \ 142 STF_EXIT_BARRIER_SLOT; \ 143 RFI_FLUSH_SLOT; \ 144 hrfid; \ 145 b hrfi_flush_fallback 146 147 #define HRFI_TO_GUEST \ 148 STF_EXIT_BARRIER_SLOT; \ 149 RFI_FLUSH_SLOT; \ 150 hrfid; \ 151 b hrfi_flush_fallback 152 153 #define HRFI_TO_UNKNOWN \ 154 STF_EXIT_BARRIER_SLOT; \ 155 RFI_FLUSH_SLOT; \ 156 hrfid; \ 157 b hrfi_flush_fallback 158 159 #ifdef CONFIG_RELOCATABLE 160 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 161 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 162 LOAD_HANDLER(r12,label); \ 163 mtctr r12; \ 164 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 165 li r10,MSR_RI; \ 166 mtmsrd r10,1; /* Set RI (EE=0) */ \ 167 bctr; 168 #else 169 /* If not relocatable, we can jump directly -- and save messing with LR */ 170 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 171 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 172 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 173 li r10,MSR_RI; \ 174 mtmsrd r10,1; /* Set RI (EE=0) */ \ 175 b label; 176 #endif 177 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 178 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 179 180 /* 181 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 182 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 183 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 184 */ 185 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 186 EXCEPTION_PROLOG_0(area); \ 187 EXCEPTION_PROLOG_1(area, extra, vec); \ 188 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 189 190 /* 191 * We're short on space and time in the exception prolog, so we can't 192 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 193 * Instead we get the base of the kernel from paca->kernelbase and or in the low 194 * part of label. This requires that the label be within 64KB of kernelbase, and 195 * that kernelbase be 64K aligned. 196 */ 197 #define LOAD_HANDLER(reg, label) \ 198 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 199 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 200 201 #define __LOAD_HANDLER(reg, label) \ 202 ld reg,PACAKBASE(r13); \ 203 ori reg,reg,(ABS_ADDR(label))@l; 204 205 /* 206 * Branches from unrelocated code (e.g., interrupts) to labels outside 207 * head-y require >64K offsets. 208 */ 209 #define __LOAD_FAR_HANDLER(reg, label) \ 210 ld reg,PACAKBASE(r13); \ 211 ori reg,reg,(ABS_ADDR(label))@l; \ 212 addis reg,reg,(ABS_ADDR(label))@h; 213 214 /* Exception register prefixes */ 215 #define EXC_HV H 216 #define EXC_STD 217 218 #if defined(CONFIG_RELOCATABLE) 219 /* 220 * If we support interrupts with relocation on AND we're a relocatable kernel, 221 * we need to use CTR to get to the 2nd level handler. So, save/restore it 222 * when required. 223 */ 224 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 225 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 226 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 227 #else 228 /* ...else CTR is unused and in register. */ 229 #define SAVE_CTR(reg, area) 230 #define GET_CTR(reg, area) mfctr reg 231 #define RESTORE_CTR(reg, area) 232 #endif 233 234 /* 235 * PPR save/restore macros used in exceptions_64s.S 236 * Used for P7 or later processors 237 */ 238 #define SAVE_PPR(area, ra, rb) \ 239 BEGIN_FTR_SECTION_NESTED(940) \ 240 ld ra,PACACURRENT(r13); \ 241 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 242 std rb,TASKTHREADPPR(ra); \ 243 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 244 245 #define RESTORE_PPR_PACA(area, ra) \ 246 BEGIN_FTR_SECTION_NESTED(941) \ 247 ld ra,area+EX_PPR(r13); \ 248 mtspr SPRN_PPR,ra; \ 249 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 250 251 /* 252 * Get an SPR into a register if the CPU has the given feature 253 */ 254 #define OPT_GET_SPR(ra, spr, ftr) \ 255 BEGIN_FTR_SECTION_NESTED(943) \ 256 mfspr ra,spr; \ 257 END_FTR_SECTION_NESTED(ftr,ftr,943) 258 259 /* 260 * Set an SPR from a register if the CPU has the given feature 261 */ 262 #define OPT_SET_SPR(ra, spr, ftr) \ 263 BEGIN_FTR_SECTION_NESTED(943) \ 264 mtspr spr,ra; \ 265 END_FTR_SECTION_NESTED(ftr,ftr,943) 266 267 /* 268 * Save a register to the PACA if the CPU has the given feature 269 */ 270 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 271 BEGIN_FTR_SECTION_NESTED(943) \ 272 std ra,offset(r13); \ 273 END_FTR_SECTION_NESTED(ftr,ftr,943) 274 275 #define EXCEPTION_PROLOG_0(area) \ 276 GET_PACA(r13); \ 277 std r9,area+EX_R9(r13); /* save r9 */ \ 278 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 279 HMT_MEDIUM; \ 280 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 281 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 282 283 #define __EXCEPTION_PROLOG_1_PRE(area) \ 284 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 285 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 286 INTERRUPT_TO_KERNEL; \ 287 SAVE_CTR(r10, area); \ 288 mfcr r9; 289 290 #define __EXCEPTION_PROLOG_1_POST(area) \ 291 std r11,area+EX_R11(r13); \ 292 std r12,area+EX_R12(r13); \ 293 GET_SCRATCH0(r10); \ 294 std r10,area+EX_R13(r13) 295 296 /* 297 * This version of the EXCEPTION_PROLOG_1 will carry 298 * addition parameter called "bitmask" to support 299 * checking of the interrupt maskable level in the SOFTEN_TEST. 300 * Intended to be used in MASKABLE_EXCPETION_* macros. 301 */ 302 #define MASKABLE_EXCEPTION_PROLOG_1(area, extra, vec, bitmask) \ 303 __EXCEPTION_PROLOG_1_PRE(area); \ 304 extra(vec, bitmask); \ 305 __EXCEPTION_PROLOG_1_POST(area); 306 307 /* 308 * This version of the EXCEPTION_PROLOG_1 is intended 309 * to be used in STD_EXCEPTION* macros 310 */ 311 #define _EXCEPTION_PROLOG_1(area, extra, vec) \ 312 __EXCEPTION_PROLOG_1_PRE(area); \ 313 extra(vec); \ 314 __EXCEPTION_PROLOG_1_POST(area); 315 316 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 317 _EXCEPTION_PROLOG_1(area, extra, vec) 318 319 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 320 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 321 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 322 LOAD_HANDLER(r12,label) \ 323 mtspr SPRN_##h##SRR0,r12; \ 324 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 325 mtspr SPRN_##h##SRR1,r10; \ 326 h##RFI_TO_KERNEL; \ 327 b . /* prevent speculative execution */ 328 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 329 __EXCEPTION_PROLOG_PSERIES_1(label, h) 330 331 /* _NORI variant keeps MSR_RI clear */ 332 #define __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 333 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 334 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \ 335 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 336 LOAD_HANDLER(r12,label) \ 337 mtspr SPRN_##h##SRR0,r12; \ 338 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 339 mtspr SPRN_##h##SRR1,r10; \ 340 h##RFI_TO_KERNEL; \ 341 b . /* prevent speculative execution */ 342 343 #define EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \ 344 __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) 345 346 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 347 EXCEPTION_PROLOG_0(area); \ 348 EXCEPTION_PROLOG_1(area, extra, vec); \ 349 EXCEPTION_PROLOG_PSERIES_1(label, h); 350 351 #define __KVMTEST(h, n) \ 352 lbz r10,HSTATE_IN_GUEST(r13); \ 353 cmpwi r10,0; \ 354 bne do_kvm_##h##n 355 356 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 357 /* 358 * If hv is possible, interrupts come into to the hv version 359 * of the kvmppc_interrupt code, which then jumps to the PR handler, 360 * kvmppc_interrupt_pr, if the guest is a PR guest. 361 */ 362 #define kvmppc_interrupt kvmppc_interrupt_hv 363 #else 364 #define kvmppc_interrupt kvmppc_interrupt_pr 365 #endif 366 367 /* 368 * Branch to label using its 0xC000 address. This results in instruction 369 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 370 * on using mtmsr rather than rfid. 371 * 372 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 373 * load KBASE for a slight optimisation. 374 */ 375 #define BRANCH_TO_C000(reg, label) \ 376 __LOAD_HANDLER(reg, label); \ 377 mtctr reg; \ 378 bctr 379 380 #ifdef CONFIG_RELOCATABLE 381 #define BRANCH_TO_COMMON(reg, label) \ 382 __LOAD_HANDLER(reg, label); \ 383 mtctr reg; \ 384 bctr 385 386 #define BRANCH_LINK_TO_FAR(label) \ 387 __LOAD_FAR_HANDLER(r12, label); \ 388 mtctr r12; \ 389 bctrl 390 391 /* 392 * KVM requires __LOAD_FAR_HANDLER. 393 * 394 * __BRANCH_TO_KVM_EXIT branches are also a special case because they 395 * explicitly use r9 then reload it from PACA before branching. Hence 396 * the double-underscore. 397 */ 398 #define __BRANCH_TO_KVM_EXIT(area, label) \ 399 mfctr r9; \ 400 std r9,HSTATE_SCRATCH1(r13); \ 401 __LOAD_FAR_HANDLER(r9, label); \ 402 mtctr r9; \ 403 ld r9,area+EX_R9(r13); \ 404 bctr 405 406 #else 407 #define BRANCH_TO_COMMON(reg, label) \ 408 b label 409 410 #define BRANCH_LINK_TO_FAR(label) \ 411 bl label 412 413 #define __BRANCH_TO_KVM_EXIT(area, label) \ 414 ld r9,area+EX_R9(r13); \ 415 b label 416 417 #endif 418 419 /* Do not enable RI */ 420 #define EXCEPTION_PROLOG_PSERIES_NORI(area, label, h, extra, vec) \ 421 EXCEPTION_PROLOG_0(area); \ 422 EXCEPTION_PROLOG_1(area, extra, vec); \ 423 EXCEPTION_PROLOG_PSERIES_1_NORI(label, h); 424 425 426 #define __KVM_HANDLER(area, h, n) \ 427 BEGIN_FTR_SECTION_NESTED(947) \ 428 ld r10,area+EX_CFAR(r13); \ 429 std r10,HSTATE_CFAR(r13); \ 430 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 431 BEGIN_FTR_SECTION_NESTED(948) \ 432 ld r10,area+EX_PPR(r13); \ 433 std r10,HSTATE_PPR(r13); \ 434 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 435 ld r10,area+EX_R10(r13); \ 436 std r12,HSTATE_SCRATCH0(r13); \ 437 sldi r12,r9,32; \ 438 ori r12,r12,(n); \ 439 /* This reloads r9 before branching to kvmppc_interrupt */ \ 440 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt) 441 442 #define __KVM_HANDLER_SKIP(area, h, n) \ 443 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 444 beq 89f; \ 445 BEGIN_FTR_SECTION_NESTED(948) \ 446 ld r10,area+EX_PPR(r13); \ 447 std r10,HSTATE_PPR(r13); \ 448 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 449 ld r10,area+EX_R10(r13); \ 450 std r12,HSTATE_SCRATCH0(r13); \ 451 sldi r12,r9,32; \ 452 ori r12,r12,(n); \ 453 /* This reloads r9 before branching to kvmppc_interrupt */ \ 454 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \ 455 89: mtocrf 0x80,r9; \ 456 ld r9,area+EX_R9(r13); \ 457 ld r10,area+EX_R10(r13); \ 458 b kvmppc_skip_##h##interrupt 459 460 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 461 #define KVMTEST(h, n) __KVMTEST(h, n) 462 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 463 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 464 465 #else 466 #define KVMTEST(h, n) 467 #define KVM_HANDLER(area, h, n) 468 #define KVM_HANDLER_SKIP(area, h, n) 469 #endif 470 471 #define NOTEST(n) 472 473 #define EXCEPTION_PROLOG_COMMON_1() \ 474 std r9,_CCR(r1); /* save CR in stackframe */ \ 475 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 476 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 477 std r10,0(r1); /* make stack chain pointer */ \ 478 std r0,GPR0(r1); /* save r0 in stackframe */ \ 479 std r10,GPR1(r1); /* save r1 in stackframe */ \ 480 481 482 /* 483 * The common exception prolog is used for all except a few exceptions 484 * such as a segment miss on a kernel address. We have to be prepared 485 * to take another exception from the point where we first touch the 486 * kernel stack onwards. 487 * 488 * On entry r13 points to the paca, r9-r13 are saved in the paca, 489 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 490 * SRR1, and relocation is on. 491 */ 492 #define EXCEPTION_PROLOG_COMMON(n, area) \ 493 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 494 mr r10,r1; /* Save r1 */ \ 495 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 496 beq- 1f; \ 497 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 498 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 499 blt+ cr1,3f; /* abort if it is */ \ 500 li r1,(n); /* will be reloaded later */ \ 501 sth r1,PACA_TRAP_SAVE(r13); \ 502 std r3,area+EX_R3(r13); \ 503 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 504 RESTORE_CTR(r1, area); \ 505 b bad_stack; \ 506 3: EXCEPTION_PROLOG_COMMON_1(); \ 507 beq 4f; /* if from kernel mode */ \ 508 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 509 SAVE_PPR(area, r9, r10); \ 510 4: EXCEPTION_PROLOG_COMMON_2(area) \ 511 EXCEPTION_PROLOG_COMMON_3(n) \ 512 ACCOUNT_STOLEN_TIME 513 514 /* Save original regs values from save area to stack frame. */ 515 #define EXCEPTION_PROLOG_COMMON_2(area) \ 516 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 517 ld r10,area+EX_R10(r13); \ 518 std r9,GPR9(r1); \ 519 std r10,GPR10(r1); \ 520 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 521 ld r10,area+EX_R12(r13); \ 522 ld r11,area+EX_R13(r13); \ 523 std r9,GPR11(r1); \ 524 std r10,GPR12(r1); \ 525 std r11,GPR13(r1); \ 526 BEGIN_FTR_SECTION_NESTED(66); \ 527 ld r10,area+EX_CFAR(r13); \ 528 std r10,ORIG_GPR3(r1); \ 529 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 530 GET_CTR(r10, area); \ 531 std r10,_CTR(r1); 532 533 #define EXCEPTION_PROLOG_COMMON_3(n) \ 534 std r2,GPR2(r1); /* save r2 in stackframe */ \ 535 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 536 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 537 mflr r9; /* Get LR, later save to stack */ \ 538 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 539 std r9,_LINK(r1); \ 540 lbz r10,PACAIRQSOFTMASK(r13); \ 541 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 542 std r10,SOFTE(r1); \ 543 std r11,_XER(r1); \ 544 li r9,(n)+1; \ 545 std r9,_TRAP(r1); /* set trap number */ \ 546 li r10,0; \ 547 ld r11,exception_marker@toc(r2); \ 548 std r10,RESULT(r1); /* clear regs->result */ \ 549 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 550 551 /* 552 * Exception vectors. 553 */ 554 #define STD_EXCEPTION_PSERIES(vec, label) \ 555 SET_SCRATCH0(r13); /* save r13 */ \ 556 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 557 EXC_STD, KVMTEST_PR, vec); \ 558 559 /* Version of above for when we have to branch out-of-line */ 560 #define __OOL_EXCEPTION(vec, label, hdlr) \ 561 SET_SCRATCH0(r13) \ 562 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 563 b hdlr; 564 565 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ 566 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 567 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 568 569 #define STD_EXCEPTION_HV(loc, vec, label) \ 570 SET_SCRATCH0(r13); /* save r13 */ \ 571 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 572 EXC_HV, KVMTEST_HV, vec); 573 574 #define STD_EXCEPTION_HV_OOL(vec, label) \ 575 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 576 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 577 578 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 579 /* No guest interrupts come through here */ \ 580 SET_SCRATCH0(r13); /* save r13 */ \ 581 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 582 583 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ 584 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 585 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD) 586 587 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 588 SET_SCRATCH0(r13); /* save r13 */ \ 589 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \ 590 EXC_HV, KVMTEST_HV, vec); 591 592 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 593 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 594 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 595 596 /* This associate vector numbers with bits in paca->irq_happened */ 597 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 598 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 599 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 600 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 601 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 602 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 603 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 604 #define SOFTEN_VALUE_0xf00 PACA_IRQ_PMI 605 606 #define __SOFTEN_TEST(h, vec, bitmask) \ 607 lbz r10,PACAIRQSOFTMASK(r13); \ 608 andi. r10,r10,bitmask; \ 609 li r10,SOFTEN_VALUE_##vec; \ 610 bne masked_##h##interrupt 611 612 #define _SOFTEN_TEST(h, vec, bitmask) __SOFTEN_TEST(h, vec, bitmask) 613 614 #define SOFTEN_TEST_PR(vec, bitmask) \ 615 KVMTEST(EXC_STD, vec); \ 616 _SOFTEN_TEST(EXC_STD, vec, bitmask) 617 618 #define SOFTEN_TEST_HV(vec, bitmask) \ 619 KVMTEST(EXC_HV, vec); \ 620 _SOFTEN_TEST(EXC_HV, vec, bitmask) 621 622 #define KVMTEST_PR(vec) \ 623 KVMTEST(EXC_STD, vec) 624 625 #define KVMTEST_HV(vec) \ 626 KVMTEST(EXC_HV, vec) 627 628 #define SOFTEN_NOTEST_PR(vec, bitmask) _SOFTEN_TEST(EXC_STD, vec, bitmask) 629 #define SOFTEN_NOTEST_HV(vec, bitmask) _SOFTEN_TEST(EXC_HV, vec, bitmask) 630 631 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 632 SET_SCRATCH0(r13); /* save r13 */ \ 633 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 634 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 635 EXCEPTION_PROLOG_PSERIES_1(label, h); 636 637 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 638 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) 639 640 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label, bitmask) \ 641 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 642 EXC_STD, SOFTEN_TEST_PR, bitmask) 643 644 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label, bitmask) \ 645 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec, bitmask);\ 646 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 647 648 #define MASKABLE_EXCEPTION_HV(loc, vec, label, bitmask) \ 649 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 650 EXC_HV, SOFTEN_TEST_HV, bitmask) 651 652 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \ 653 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 654 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 655 656 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) \ 657 SET_SCRATCH0(r13); /* save r13 */ \ 658 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 659 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \ 660 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 661 662 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask)\ 663 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra, bitmask) 664 665 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label, bitmask) \ 666 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 667 EXC_STD, SOFTEN_NOTEST_PR, bitmask) 668 669 #define MASKABLE_RELON_EXCEPTION_PSERIES_OOL(vec, label, bitmask) \ 670 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_PR, vec, bitmask);\ 671 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD); 672 673 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label, bitmask) \ 674 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 675 EXC_HV, SOFTEN_TEST_HV, bitmask) 676 677 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \ 678 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\ 679 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 680 681 /* 682 * Our exception common code can be passed various "additions" 683 * to specify the behaviour of interrupts, whether to kick the 684 * runlatch, etc... 685 */ 686 687 /* 688 * This addition reconciles our actual IRQ state with the various software 689 * flags that track it. This may call C code. 690 */ 691 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 692 693 #define ADD_NVGPRS \ 694 bl save_nvgprs 695 696 #define RUNLATCH_ON \ 697 BEGIN_FTR_SECTION \ 698 CURRENT_THREAD_INFO(r3, r1); \ 699 ld r4,TI_LOCAL_FLAGS(r3); \ 700 andi. r0,r4,_TLF_RUNLATCH; \ 701 beql ppc64_runlatch_on_trampoline; \ 702 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 703 704 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \ 705 EXCEPTION_PROLOG_COMMON(trap, area); \ 706 /* Volatile regs are potentially clobbered here */ \ 707 additions; \ 708 addi r3,r1,STACK_FRAME_OVERHEAD; \ 709 bl hdlr; \ 710 b ret 711 712 /* 713 * Exception where stack is already set in r1, r1 is saved in r10, and it 714 * continues rather than returns. 715 */ 716 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \ 717 EXCEPTION_PROLOG_COMMON_1(); \ 718 EXCEPTION_PROLOG_COMMON_2(area); \ 719 EXCEPTION_PROLOG_COMMON_3(trap); \ 720 /* Volatile regs are potentially clobbered here */ \ 721 additions; \ 722 addi r3,r1,STACK_FRAME_OVERHEAD; \ 723 bl hdlr 724 725 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 726 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 727 ret_from_except, ADD_NVGPRS;ADD_RECONCILE) 728 729 /* 730 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 731 * in the idle task and therefore need the special idle handling 732 * (finish nap and runlatch) 733 */ 734 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 735 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \ 736 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 737 738 /* 739 * When the idle code in power4_idle puts the CPU into NAP mode, 740 * it has to do so in a loop, and relies on the external interrupt 741 * and decrementer interrupt entry code to get it out of the loop. 742 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 743 * to signal that it is in the loop and needs help to get out. 744 */ 745 #ifdef CONFIG_PPC_970_NAP 746 #define FINISH_NAP \ 747 BEGIN_FTR_SECTION \ 748 CURRENT_THREAD_INFO(r11, r1); \ 749 ld r9,TI_LOCAL_FLAGS(r11); \ 750 andi. r10,r9,_TLF_NAPPING; \ 751 bnel power4_fixup_nap; \ 752 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 753 #else 754 #define FINISH_NAP 755 #endif 756 757 #endif /* _ASM_POWERPC_EXCEPTION_H */ 758