xref: /linux/arch/powerpc/boot/dts/mpc8377_wlan.dts (revision bba2c3615bd6cfee7456d1130f2e6b01b3f4e9ba) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8377E WLAN Device Tree Source
4 *
5 * Copyright 2007-2009 Freescale Semiconductor Inc.
6 * Copyright 2009 MontaVista Software, Inc.
7 */
8
9/dts-v1/;
10
11/ {
12	compatible = "fsl,mpc8377wlan";
13	model = "fsl,mpc8377wlan";
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	aliases {
18		ethernet0 = &enet0;
19		ethernet1 = &enet1;
20		serial0 = &serial0;
21		serial1 = &serial1;
22		pci0 = &pci0;
23		pci1 = &pci1;
24		pci2 = &pci2;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		PowerPC,8377@0 {
32			device_type = "cpu";
33			reg = <0x0>;
34			d-cache-line-size = <32>;
35			i-cache-line-size = <32>;
36			d-cache-size = <32768>;
37			i-cache-size = <32768>;
38			timebase-frequency = <0>;
39			bus-frequency = <0>;
40			clock-frequency = <0>;
41		};
42	};
43
44	memory@0 {
45		device_type = "memory";
46		reg = <0x00000000 0x20000000>;	// 512MB at 0
47	};
48
49	localbus@e0005000 {
50		#address-cells = <2>;
51		#size-cells = <1>;
52		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
53		reg = <0xe0005000 0x1000>;
54		interrupts = <77 0x8>;
55		interrupt-parent = <&ipic>;
56		ranges = <0x0 0x0 0xfc000000 0x04000000>;
57
58		flash@0,0 {
59			#address-cells = <1>;
60			#size-cells = <1>;
61			compatible = "cfi-flash";
62			reg = <0x0 0x0 0x4000000>;
63			bank-width = <2>;
64			device-width = <1>;
65
66			partition@0 {
67				reg = <0 0x80000>;
68				label = "u-boot";
69				read-only;
70			};
71
72			partition@a0000 {
73				reg = <0xa0000 0x300000>;
74				label = "kernel";
75			};
76
77			partition@3a0000 {
78				reg = <0x3a0000 0x3c60000>;
79				label = "rootfs";
80			};
81		};
82	};
83
84	immr@e0000000 {
85		#address-cells = <1>;
86		#size-cells = <1>;
87		device_type = "soc";
88		compatible = "simple-bus";
89		ranges = <0x0 0xe0000000 0x00100000>;
90		reg = <0xe0000000 0x00000200>;
91		bus-frequency = <0>;
92
93		watchdog@200 {
94			device_type = "watchdog";
95			compatible = "mpc83xx_wdt";
96			reg = <0x200 0x100>;
97		};
98
99		gpio1: gpio-controller@c00 {
100			#gpio-cells = <2>;
101			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
102			reg = <0xc00 0x100>;
103			interrupts = <74 0x8>;
104			interrupt-parent = <&ipic>;
105			gpio-controller;
106		};
107
108		gpio2: gpio-controller@d00 {
109			#gpio-cells = <2>;
110			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
111			reg = <0xd00 0x100>;
112			interrupts = <75 0x8>;
113			interrupt-parent = <&ipic>;
114			gpio-controller;
115		};
116
117		sleep-nexus {
118			#address-cells = <1>;
119			#size-cells = <1>;
120			compatible = "simple-bus";
121			sleep = <&pmc 0x0c000000>;
122			ranges;
123
124			i2c@3000 {
125				#address-cells = <1>;
126				#size-cells = <0>;
127				cell-index = <0>;
128				compatible = "fsl-i2c";
129				reg = <0x3000 0x100>;
130				interrupts = <14 0x8>;
131				interrupt-parent = <&ipic>;
132				dfsrr;
133
134				at24@50 {
135					compatible = "atmel,24c256";
136					reg = <0x50>;
137				};
138
139				rtc@68 {
140					compatible = "dallas,ds1339";
141					reg = <0x68>;
142				};
143			};
144
145			sdhci@2e000 {
146				compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
147				reg = <0x2e000 0x1000>;
148				interrupts = <42 0x8>;
149				interrupt-parent = <&ipic>;
150				sdhci,wp-inverted;
151				clock-frequency = <133333333>;
152			};
153		};
154
155		i2c@3100 {
156			#address-cells = <1>;
157			#size-cells = <0>;
158			cell-index = <1>;
159			compatible = "fsl-i2c";
160			reg = <0x3100 0x100>;
161			interrupts = <15 0x8>;
162			interrupt-parent = <&ipic>;
163			dfsrr;
164		};
165
166		spi@7000 {
167			cell-index = <0>;
168			compatible = "fsl,spi";
169			reg = <0x7000 0x1000>;
170			interrupts = <16 0x8>;
171			interrupt-parent = <&ipic>;
172			mode = "cpu";
173		};
174
175		dma@82a8 {
176			#address-cells = <1>;
177			#size-cells = <1>;
178			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
179			reg = <0x82a8 4>;
180			ranges = <0 0x8100 0x1a8>;
181			interrupt-parent = <&ipic>;
182			interrupts = <71 8>;
183			cell-index = <0>;
184			dma-channel@0 {
185				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
186				reg = <0 0x80>;
187				cell-index = <0>;
188				interrupt-parent = <&ipic>;
189				interrupts = <71 8>;
190			};
191			dma-channel@80 {
192				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
193				reg = <0x80 0x80>;
194				cell-index = <1>;
195				interrupt-parent = <&ipic>;
196				interrupts = <71 8>;
197			};
198			dma-channel@100 {
199				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
200				reg = <0x100 0x80>;
201				cell-index = <2>;
202				interrupt-parent = <&ipic>;
203				interrupts = <71 8>;
204			};
205			dma-channel@180 {
206				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
207				reg = <0x180 0x28>;
208				cell-index = <3>;
209				interrupt-parent = <&ipic>;
210				interrupts = <71 8>;
211			};
212		};
213
214		usb@23000 {
215			compatible = "fsl-usb2-dr";
216			reg = <0x23000 0x1000>;
217			#address-cells = <1>;
218			#size-cells = <0>;
219			interrupt-parent = <&ipic>;
220			interrupts = <38 0x8>;
221			phy_type = "ulpi";
222			sleep = <&pmc 0x00c00000>;
223		};
224
225		enet0: ethernet@24000 {
226			#address-cells = <1>;
227			#size-cells = <1>;
228			cell-index = <0>;
229			device_type = "network";
230			model = "eTSEC";
231			compatible = "gianfar";
232			reg = <0x24000 0x1000>;
233			ranges = <0x0 0x24000 0x1000>;
234			local-mac-address = [ 00 00 00 00 00 00 ];
235			interrupts = <32 0x8 33 0x8 34 0x8>;
236			phy-connection-type = "mii";
237			interrupt-parent = <&ipic>;
238			tbi-handle = <&tbi0>;
239			phy-handle = <&phy2>;
240			sleep = <&pmc 0xc0000000>;
241			fsl,magic-packet;
242
243			mdio@520 {
244				#address-cells = <1>;
245				#size-cells = <0>;
246				compatible = "fsl,gianfar-mdio";
247				reg = <0x520 0x20>;
248
249				phy2: ethernet-phy@2 {
250					interrupt-parent = <&ipic>;
251					interrupts = <17 0x8>;
252					reg = <0x2>;
253				};
254
255				phy3: ethernet-phy@3 {
256					interrupt-parent = <&ipic>;
257					interrupts = <18 0x8>;
258					reg = <0x3>;
259				};
260
261				tbi0: tbi-phy@11 {
262					reg = <0x11>;
263					device_type = "tbi-phy";
264				};
265			};
266		};
267
268		enet1: ethernet@25000 {
269			#address-cells = <1>;
270			#size-cells = <1>;
271			cell-index = <1>;
272			device_type = "network";
273			model = "eTSEC";
274			compatible = "gianfar";
275			reg = <0x25000 0x1000>;
276			ranges = <0x0 0x25000 0x1000>;
277			local-mac-address = [ 00 00 00 00 00 00 ];
278			interrupts = <35 0x8 36 0x8 37 0x8>;
279			phy-connection-type = "mii";
280			interrupt-parent = <&ipic>;
281			phy-handle = <&phy3>;
282			tbi-handle = <&tbi1>;
283			sleep = <&pmc 0x30000000>;
284			fsl,magic-packet;
285
286			mdio@520 {
287				#address-cells = <1>;
288				#size-cells = <0>;
289				compatible = "fsl,gianfar-tbi";
290				reg = <0x520 0x20>;
291
292				tbi1: tbi-phy@11 {
293					reg = <0x11>;
294					device_type = "tbi-phy";
295				};
296			};
297		};
298
299		serial0: serial@4500 {
300			cell-index = <0>;
301			device_type = "serial";
302			compatible = "fsl,ns16550", "ns16550";
303			reg = <0x4500 0x100>;
304			clock-frequency = <0>;
305			interrupts = <9 0x8>;
306			interrupt-parent = <&ipic>;
307		};
308
309		serial1: serial@4600 {
310			cell-index = <1>;
311			device_type = "serial";
312			compatible = "fsl,ns16550", "ns16550";
313			reg = <0x4600 0x100>;
314			clock-frequency = <0>;
315			interrupts = <10 0x8>;
316			interrupt-parent = <&ipic>;
317		};
318
319		crypto@30000 {
320			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
321				     "fsl,sec2.1", "fsl,sec2.0";
322			reg = <0x30000 0x10000>;
323			interrupts = <11 0x8>;
324			interrupt-parent = <&ipic>;
325			fsl,num-channels = <4>;
326			fsl,channel-fifo-len = <24>;
327			fsl,exec-units-mask = <0x9fe>;
328			fsl,descriptor-types-mask = <0x3ab0ebf>;
329			sleep = <&pmc 0x03000000>;
330		};
331
332		sata@18000 {
333			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
334			reg = <0x18000 0x1000>;
335			interrupts = <44 0x8>;
336			interrupt-parent = <&ipic>;
337			sleep = <&pmc 0x000000c0>;
338		};
339
340		sata@19000 {
341			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
342			reg = <0x19000 0x1000>;
343			interrupts = <45 0x8>;
344			interrupt-parent = <&ipic>;
345			sleep = <&pmc 0x00000030>;
346		};
347
348		/* IPIC
349		 * interrupts cell = <intr #, sense>
350		 * sense values match linux IORESOURCE_IRQ_* defines:
351		 * sense == 8: Level, low assertion
352		 * sense == 2: Edge, high-to-low change
353		 */
354		ipic: interrupt-controller@700 {
355			compatible = "fsl,ipic";
356			interrupt-controller;
357			#address-cells = <0>;
358			#interrupt-cells = <2>;
359			reg = <0x700 0x100>;
360		};
361
362		pmc: power@b00 {
363			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
364			reg = <0xb00 0x100 0xa00 0x100>;
365			interrupts = <80 0x8>;
366			interrupt-parent = <&ipic>;
367		};
368	};
369
370	pci0: pci@e0008500 {
371		interrupt-map-mask = <0xf800 0 0 7>;
372		interrupt-map = <
373				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
374
375				/* IDSEL AD14 IRQ6 inta */
376				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
377
378				/* IDSEL AD15 IRQ5 inta */
379				 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
380		interrupt-parent = <&ipic>;
381		interrupts = <66 0x8>;
382		bus-range = <0 0>;
383		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
384		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
385		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
386		sleep = <&pmc 0x00010000>;
387		clock-frequency = <66666666>;
388		#interrupt-cells = <1>;
389		#size-cells = <2>;
390		#address-cells = <3>;
391		reg = <0xe0008500 0x100		/* internal registers */
392		       0xe0008300 0x8>;		/* config space access registers */
393		compatible = "fsl,mpc8349-pci";
394		device_type = "pci";
395	};
396
397	pci1: pcie@e0009000 {
398		#address-cells = <3>;
399		#size-cells = <2>;
400		#interrupt-cells = <1>;
401		device_type = "pci";
402		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
403		reg = <0xe0009000 0x00001000>;
404		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
405		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
406		bus-range = <0 255>;
407		interrupt-map-mask = <0xf800 0 0 7>;
408		interrupt-map = <0 0 0 1 &ipic 1 8
409				 0 0 0 2 &ipic 1 8
410				 0 0 0 3 &ipic 1 8
411				 0 0 0 4 &ipic 1 8>;
412		sleep = <&pmc 0x00300000>;
413		clock-frequency = <0>;
414
415		pcie@0 {
416			#address-cells = <3>;
417			#size-cells = <2>;
418			device_type = "pci";
419			reg = <0 0 0 0 0>;
420			ranges = <0x02000000 0 0xa8000000
421				  0x02000000 0 0xa8000000
422				  0 0x10000000
423				  0x01000000 0 0x00000000
424				  0x01000000 0 0x00000000
425				  0 0x00800000>;
426		};
427	};
428
429	pci2: pcie@e000a000 {
430		#address-cells = <3>;
431		#size-cells = <2>;
432		#interrupt-cells = <1>;
433		device_type = "pci";
434		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
435		reg = <0xe000a000 0x00001000>;
436		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
437			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
438		bus-range = <0 255>;
439		interrupt-map-mask = <0xf800 0 0 7>;
440		interrupt-map = <0 0 0 1 &ipic 2 8
441				 0 0 0 2 &ipic 2 8
442				 0 0 0 3 &ipic 2 8
443				 0 0 0 4 &ipic 2 8>;
444		sleep = <&pmc 0x000c0000>;
445		clock-frequency = <0>;
446
447		pcie@0 {
448			#address-cells = <3>;
449			#size-cells = <2>;
450			device_type = "pci";
451			reg = <0 0 0 0 0>;
452			ranges = <0x02000000 0 0xc8000000
453				  0x02000000 0 0xc8000000
454				  0 0x10000000
455				  0x01000000 0 0x00000000
456				  0x01000000 0 0x00000000
457				  0 0x00800000>;
458		};
459	};
460};
461