1 /* 2 * Unaligned memory access handler 3 * 4 * Copyright (C) 2001 Randolph Chung <tausq@debian.org> 5 * Significantly tweaked by LaMont Jones <lamont@debian.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 */ 22 23 #include <linux/config.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <asm/uaccess.h> 27 28 /* #define DEBUG_UNALIGNED 1 */ 29 30 #ifdef DEBUG_UNALIGNED 31 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __FUNCTION__ ); printk(KERN_DEBUG fmt, ##args ); } while (0) 32 #else 33 #define DPRINTF(fmt, args...) 34 #endif 35 36 #ifdef __LP64__ 37 #define RFMT "%016lx" 38 #else 39 #define RFMT "%08lx" 40 #endif 41 42 #define FIXUP_BRANCH(lbl) \ 43 "\tldil L%%" #lbl ", %%r1\n" \ 44 "\tldo R%%" #lbl "(%%r1), %%r1\n" \ 45 "\tbv,n %%r0(%%r1)\n" 46 /* If you use FIXUP_BRANCH, then you must list this clobber */ 47 #define FIXUP_BRANCH_CLOBBER "r1" 48 49 /* 1111 1100 0000 0000 0001 0011 1100 0000 */ 50 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6) 51 #define OPCODE2(a,b) ((a)<<26|(b)<<1) 52 #define OPCODE3(a,b) ((a)<<26|(b)<<2) 53 #define OPCODE4(a) ((a)<<26) 54 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf) 55 #define OPCODE2_MASK OPCODE2(0x3f,1) 56 #define OPCODE3_MASK OPCODE3(0x3f,1) 57 #define OPCODE4_MASK OPCODE4(0x3f) 58 59 /* skip LDB - never unaligned (index) */ 60 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1) 61 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2) 62 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3) 63 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4) 64 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5) 65 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6) 66 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7) 67 /* skip LDB - never unaligned (short) */ 68 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1) 69 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2) 70 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3) 71 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4) 72 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5) 73 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6) 74 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7) 75 /* skip STB - never unaligned */ 76 #define OPCODE_STH OPCODE1(0x03,1,0x9) 77 #define OPCODE_STW OPCODE1(0x03,1,0xa) 78 #define OPCODE_STD OPCODE1(0x03,1,0xb) 79 /* skip STBY - never unaligned */ 80 /* skip STDBY - never unaligned */ 81 #define OPCODE_STWA OPCODE1(0x03,1,0xe) 82 #define OPCODE_STDA OPCODE1(0x03,1,0xf) 83 84 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0) 85 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1) 86 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8) 87 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9) 88 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0) 89 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1) 90 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8) 91 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9) 92 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0) 93 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8) 94 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0) 95 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8) 96 97 #define OPCODE_LDD_L OPCODE2(0x14,0) 98 #define OPCODE_FLDD_L OPCODE2(0x14,1) 99 #define OPCODE_STD_L OPCODE2(0x1c,0) 100 #define OPCODE_FSTD_L OPCODE2(0x1c,1) 101 102 #define OPCODE_LDW_M OPCODE3(0x17,1) 103 #define OPCODE_FLDW_L OPCODE3(0x17,0) 104 #define OPCODE_FSTW_L OPCODE3(0x1f,0) 105 #define OPCODE_STW_M OPCODE3(0x1f,1) 106 107 #define OPCODE_LDH_L OPCODE4(0x11) 108 #define OPCODE_LDW_L OPCODE4(0x12) 109 #define OPCODE_LDWM OPCODE4(0x13) 110 #define OPCODE_STH_L OPCODE4(0x19) 111 #define OPCODE_STW_L OPCODE4(0x1A) 112 #define OPCODE_STWM OPCODE4(0x1B) 113 114 #define MAJOR_OP(i) (((i)>>26)&0x3f) 115 #define R1(i) (((i)>>21)&0x1f) 116 #define R2(i) (((i)>>16)&0x1f) 117 #define R3(i) ((i)&0x1f) 118 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1)) 119 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0)) 120 #define IM5_2(i) IM((i)>>16,5) 121 #define IM5_3(i) IM((i),5) 122 #define IM14(i) IM((i),14) 123 124 #define ERR_NOTHANDLED -1 125 #define ERR_PAGEFAULT -2 126 127 int unaligned_enabled __read_mostly = 1; 128 129 void die_if_kernel (char *str, struct pt_regs *regs, long err); 130 131 static int emulate_ldh(struct pt_regs *regs, int toreg) 132 { 133 unsigned long saddr = regs->ior; 134 unsigned long val = 0; 135 int ret; 136 137 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n", 138 regs->isr, regs->ior, toreg); 139 140 __asm__ __volatile__ ( 141 " mtsp %4, %%sr1\n" 142 "1: ldbs 0(%%sr1,%3), %%r20\n" 143 "2: ldbs 1(%%sr1,%3), %0\n" 144 " depw %%r20, 23, 24, %0\n" 145 " copy %%r0, %1\n" 146 "3: \n" 147 " .section .fixup,\"ax\"\n" 148 "4: ldi -2, %1\n" 149 FIXUP_BRANCH(3b) 150 " .previous\n" 151 " .section __ex_table,\"aw\"\n" 152 #ifdef __LP64__ 153 " .dword 1b,4b\n" 154 " .dword 2b,4b\n" 155 #else 156 " .word 1b,4b\n" 157 " .word 2b,4b\n" 158 #endif 159 " .previous\n" 160 : "=r" (val), "=r" (ret) 161 : "0" (val), "r" (saddr), "r" (regs->isr) 162 : "r20", FIXUP_BRANCH_CLOBBER ); 163 164 DPRINTF("val = 0x" RFMT "\n", val); 165 166 if (toreg) 167 regs->gr[toreg] = val; 168 169 return ret; 170 } 171 172 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop) 173 { 174 unsigned long saddr = regs->ior; 175 unsigned long val = 0; 176 int ret; 177 178 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n", 179 regs->isr, regs->ior, toreg); 180 181 __asm__ __volatile__ ( 182 " zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */ 183 " mtsp %4, %%sr1\n" 184 " depw %%r0,31,2,%3\n" 185 "1: ldw 0(%%sr1,%3),%0\n" 186 "2: ldw 4(%%sr1,%3),%%r20\n" 187 " subi 32,%%r19,%%r19\n" 188 " mtctl %%r19,11\n" 189 " vshd %0,%%r20,%0\n" 190 " copy %%r0, %1\n" 191 "3: \n" 192 " .section .fixup,\"ax\"\n" 193 "4: ldi -2, %1\n" 194 FIXUP_BRANCH(3b) 195 " .previous\n" 196 " .section __ex_table,\"aw\"\n" 197 #ifdef __LP64__ 198 " .dword 1b,4b\n" 199 " .dword 2b,4b\n" 200 #else 201 " .word 1b,4b\n" 202 " .word 2b,4b\n" 203 #endif 204 " .previous\n" 205 : "=r" (val), "=r" (ret) 206 : "0" (val), "r" (saddr), "r" (regs->isr) 207 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 208 209 DPRINTF("val = 0x" RFMT "\n", val); 210 211 if (flop) 212 ((__u32*)(regs->fr))[toreg] = val; 213 else if (toreg) 214 regs->gr[toreg] = val; 215 216 return ret; 217 } 218 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) 219 { 220 unsigned long saddr = regs->ior; 221 __u64 val = 0; 222 int ret; 223 224 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n", 225 regs->isr, regs->ior, toreg); 226 #ifdef CONFIG_PA20 227 228 #ifndef __LP64__ 229 if (!flop) 230 return -1; 231 #endif 232 __asm__ __volatile__ ( 233 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */ 234 " mtsp %4, %%sr1\n" 235 " depd %%r0,63,3,%3\n" 236 "1: ldd 0(%%sr1,%3),%0\n" 237 "2: ldd 8(%%sr1,%3),%%r20\n" 238 " subi 64,%%r19,%%r19\n" 239 " mtsar %%r19\n" 240 " shrpd %0,%%r20,%%sar,%0\n" 241 " copy %%r0, %1\n" 242 "3: \n" 243 " .section .fixup,\"ax\"\n" 244 "4: ldi -2, %1\n" 245 FIXUP_BRANCH(3b) 246 " .previous\n" 247 " .section __ex_table,\"aw\"\n" 248 #ifdef __LP64__ 249 " .dword 1b,4b\n" 250 " .dword 2b,4b\n" 251 #else 252 " .word 1b,4b\n" 253 " .word 2b,4b\n" 254 #endif 255 " .previous\n" 256 : "=r" (val), "=r" (ret) 257 : "0" (val), "r" (saddr), "r" (regs->isr) 258 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 259 #else 260 { 261 unsigned long valh=0,vall=0; 262 __asm__ __volatile__ ( 263 " zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */ 264 " mtsp %6, %%sr1\n" 265 " dep %%r0,31,2,%5\n" 266 "1: ldw 0(%%sr1,%5),%0\n" 267 "2: ldw 4(%%sr1,%5),%1\n" 268 "3: ldw 8(%%sr1,%5),%%r20\n" 269 " subi 32,%%r19,%%r19\n" 270 " mtsar %%r19\n" 271 " vshd %0,%1,%0\n" 272 " vshd %1,%%r20,%1\n" 273 " copy %%r0, %2\n" 274 "4: \n" 275 " .section .fixup,\"ax\"\n" 276 "5: ldi -2, %2\n" 277 FIXUP_BRANCH(4b) 278 " .previous\n" 279 " .section __ex_table,\"aw\"\n" 280 #ifdef __LP64__ 281 " .dword 1b,5b\n" 282 " .dword 2b,5b\n" 283 " .dword 3b,5b\n" 284 #else 285 " .word 1b,5b\n" 286 " .word 2b,5b\n" 287 " .word 3b,5b\n" 288 #endif 289 " .previous\n" 290 : "=r" (valh), "=r" (vall), "=r" (ret) 291 : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr) 292 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 293 val=((__u64)valh<<32)|(__u64)vall; 294 } 295 #endif 296 297 DPRINTF("val = 0x%llx\n", val); 298 299 if (flop) 300 regs->fr[toreg] = val; 301 else if (toreg) 302 regs->gr[toreg] = val; 303 304 return ret; 305 } 306 307 static int emulate_sth(struct pt_regs *regs, int frreg) 308 { 309 unsigned long val = regs->gr[frreg]; 310 int ret; 311 312 if (!frreg) 313 val = 0; 314 315 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg, 316 val, regs->isr, regs->ior); 317 318 __asm__ __volatile__ ( 319 " mtsp %3, %%sr1\n" 320 " extrw,u %1, 23, 8, %%r19\n" 321 "1: stb %1, 1(%%sr1, %2)\n" 322 "2: stb %%r19, 0(%%sr1, %2)\n" 323 " copy %%r0, %0\n" 324 "3: \n" 325 " .section .fixup,\"ax\"\n" 326 "4: ldi -2, %0\n" 327 FIXUP_BRANCH(3b) 328 " .previous\n" 329 " .section __ex_table,\"aw\"\n" 330 #ifdef __LP64__ 331 " .dword 1b,4b\n" 332 " .dword 2b,4b\n" 333 #else 334 " .word 1b,4b\n" 335 " .word 2b,4b\n" 336 #endif 337 " .previous\n" 338 : "=r" (ret) 339 : "r" (val), "r" (regs->ior), "r" (regs->isr) 340 : "r19", FIXUP_BRANCH_CLOBBER ); 341 342 return ret; 343 } 344 345 static int emulate_stw(struct pt_regs *regs, int frreg, int flop) 346 { 347 unsigned long val; 348 int ret; 349 350 if (flop) 351 val = ((__u32*)(regs->fr))[frreg]; 352 else if (frreg) 353 val = regs->gr[frreg]; 354 else 355 val = 0; 356 357 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg, 358 val, regs->isr, regs->ior); 359 360 361 __asm__ __volatile__ ( 362 " mtsp %3, %%sr1\n" 363 " zdep %2, 28, 2, %%r19\n" 364 " dep %%r0, 31, 2, %2\n" 365 " mtsar %%r19\n" 366 " depwi,z -2, %%sar, 32, %%r19\n" 367 "1: ldw 0(%%sr1,%2),%%r20\n" 368 "2: ldw 4(%%sr1,%2),%%r21\n" 369 " vshd %%r0, %1, %%r22\n" 370 " vshd %1, %%r0, %%r1\n" 371 " and %%r20, %%r19, %%r20\n" 372 " andcm %%r21, %%r19, %%r21\n" 373 " or %%r22, %%r20, %%r20\n" 374 " or %%r1, %%r21, %%r21\n" 375 " stw %%r20,0(%%sr1,%2)\n" 376 " stw %%r21,4(%%sr1,%2)\n" 377 " copy %%r0, %0\n" 378 "3: \n" 379 " .section .fixup,\"ax\"\n" 380 "4: ldi -2, %0\n" 381 FIXUP_BRANCH(3b) 382 " .previous\n" 383 " .section __ex_table,\"aw\"\n" 384 #ifdef __LP64__ 385 " .dword 1b,4b\n" 386 " .dword 2b,4b\n" 387 #else 388 " .word 1b,4b\n" 389 " .word 2b,4b\n" 390 #endif 391 " .previous\n" 392 : "=r" (ret) 393 : "r" (val), "r" (regs->ior), "r" (regs->isr) 394 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER ); 395 396 return 0; 397 } 398 static int emulate_std(struct pt_regs *regs, int frreg, int flop) 399 { 400 __u64 val; 401 int ret; 402 403 if (flop) 404 val = regs->fr[frreg]; 405 else if (frreg) 406 val = regs->gr[frreg]; 407 else 408 val = 0; 409 410 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg, 411 val, regs->isr, regs->ior); 412 413 #ifdef CONFIG_PA20 414 #ifndef __LP64__ 415 if (!flop) 416 return -1; 417 #endif 418 __asm__ __volatile__ ( 419 " mtsp %3, %%sr1\n" 420 " depd,z %2, 60, 3, %%r19\n" 421 " depd %%r0, 63, 3, %2\n" 422 " mtsar %%r19\n" 423 " depdi,z -2, %%sar, 64, %%r19\n" 424 "1: ldd 0(%%sr1,%2),%%r20\n" 425 "2: ldd 8(%%sr1,%2),%%r21\n" 426 " shrpd %%r0, %1, %%sar, %%r22\n" 427 " shrpd %1, %%r0, %%sar, %%r1\n" 428 " and %%r20, %%r19, %%r20\n" 429 " andcm %%r21, %%r19, %%r21\n" 430 " or %%r22, %%r20, %%r20\n" 431 " or %%r1, %%r21, %%r21\n" 432 "3: std %%r20,0(%%sr1,%2)\n" 433 "4: std %%r21,8(%%sr1,%2)\n" 434 " copy %%r0, %0\n" 435 "5: \n" 436 " .section .fixup,\"ax\"\n" 437 "6: ldi -2, %0\n" 438 FIXUP_BRANCH(5b) 439 " .previous\n" 440 " .section __ex_table,\"aw\"\n" 441 #ifdef __LP64__ 442 " .dword 1b,6b\n" 443 " .dword 2b,6b\n" 444 " .dword 3b,6b\n" 445 " .dword 4b,6b\n" 446 #else 447 " .word 1b,6b\n" 448 " .word 2b,6b\n" 449 " .word 3b,6b\n" 450 " .word 4b,6b\n" 451 #endif 452 " .previous\n" 453 : "=r" (ret) 454 : "r" (val), "r" (regs->ior), "r" (regs->isr) 455 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER ); 456 #else 457 { 458 unsigned long valh=(val>>32),vall=(val&0xffffffffl); 459 __asm__ __volatile__ ( 460 " mtsp %4, %%sr1\n" 461 " zdep %2, 29, 2, %%r19\n" 462 " dep %%r0, 31, 2, %2\n" 463 " mtsar %%r19\n" 464 " zvdepi -2, 32, %%r19\n" 465 "1: ldw 0(%%sr1,%3),%%r20\n" 466 "2: ldw 8(%%sr1,%3),%%r21\n" 467 " vshd %1, %2, %%r1\n" 468 " vshd %%r0, %1, %1\n" 469 " vshd %2, %%r0, %2\n" 470 " and %%r20, %%r19, %%r20\n" 471 " andcm %%r21, %%r19, %%r21\n" 472 " or %1, %%r20, %1\n" 473 " or %2, %%r21, %2\n" 474 "3: stw %1,0(%%sr1,%1)\n" 475 "4: stw %%r1,4(%%sr1,%3)\n" 476 "5: stw %2,8(%%sr1,%3)\n" 477 " copy %%r0, %0\n" 478 "6: \n" 479 " .section .fixup,\"ax\"\n" 480 "7: ldi -2, %0\n" 481 FIXUP_BRANCH(6b) 482 " .previous\n" 483 " .section __ex_table,\"aw\"\n" 484 #ifdef __LP64__ 485 " .dword 1b,7b\n" 486 " .dword 2b,7b\n" 487 " .dword 3b,7b\n" 488 " .dword 4b,7b\n" 489 " .dword 5b,7b\n" 490 #else 491 " .word 1b,7b\n" 492 " .word 2b,7b\n" 493 " .word 3b,7b\n" 494 " .word 4b,7b\n" 495 " .word 5b,7b\n" 496 #endif 497 " .previous\n" 498 : "=r" (ret) 499 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr) 500 : "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER ); 501 } 502 #endif 503 504 return ret; 505 } 506 507 void handle_unaligned(struct pt_regs *regs) 508 { 509 static unsigned long unaligned_count = 0; 510 static unsigned long last_time = 0; 511 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; 512 int modify = 0; 513 int ret = ERR_NOTHANDLED; 514 struct siginfo si; 515 register int flop=0; /* true if this is a flop */ 516 517 /* log a message with pacing */ 518 if (user_mode(regs)) { 519 if (current->thread.flags & PARISC_UAC_SIGBUS) { 520 goto force_sigbus; 521 } 522 523 if (unaligned_count > 5 && jiffies - last_time > 5*HZ) { 524 unaligned_count = 0; 525 last_time = jiffies; 526 } 527 528 if (!(current->thread.flags & PARISC_UAC_NOPRINT) 529 && ++unaligned_count < 5) { 530 char buf[256]; 531 sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n", 532 current->comm, current->pid, regs->ior, regs->iaoq[0]); 533 printk(KERN_WARNING "%s", buf); 534 #ifdef DEBUG_UNALIGNED 535 show_regs(regs); 536 #endif 537 } 538 539 if (!unaligned_enabled) 540 goto force_sigbus; 541 } 542 543 /* handle modification - OK, it's ugly, see the instruction manual */ 544 switch (MAJOR_OP(regs->iir)) 545 { 546 case 0x03: 547 case 0x09: 548 case 0x0b: 549 if (regs->iir&0x20) 550 { 551 modify = 1; 552 if (regs->iir&0x1000) /* short loads */ 553 if (regs->iir&0x200) 554 newbase += IM5_3(regs->iir); 555 else 556 newbase += IM5_2(regs->iir); 557 else if (regs->iir&0x2000) /* scaled indexed */ 558 { 559 int shift=0; 560 switch (regs->iir & OPCODE1_MASK) 561 { 562 case OPCODE_LDH_I: 563 shift= 1; break; 564 case OPCODE_LDW_I: 565 shift= 2; break; 566 case OPCODE_LDD_I: 567 case OPCODE_LDDA_I: 568 shift= 3; break; 569 } 570 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; 571 } else /* simple indexed */ 572 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); 573 } 574 break; 575 case 0x13: 576 case 0x1b: 577 modify = 1; 578 newbase += IM14(regs->iir); 579 break; 580 case 0x14: 581 case 0x1c: 582 if (regs->iir&8) 583 { 584 modify = 1; 585 newbase += IM14(regs->iir&~0xe); 586 } 587 break; 588 case 0x16: 589 case 0x1e: 590 modify = 1; 591 newbase += IM14(regs->iir&6); 592 break; 593 case 0x17: 594 case 0x1f: 595 if (regs->iir&4) 596 { 597 modify = 1; 598 newbase += IM14(regs->iir&~4); 599 } 600 break; 601 } 602 603 /* TODO: make this cleaner... */ 604 switch (regs->iir & OPCODE1_MASK) 605 { 606 case OPCODE_LDH_I: 607 case OPCODE_LDH_S: 608 ret = emulate_ldh(regs, R3(regs->iir)); 609 break; 610 611 case OPCODE_LDW_I: 612 case OPCODE_LDWA_I: 613 case OPCODE_LDW_S: 614 case OPCODE_LDWA_S: 615 ret = emulate_ldw(regs, R3(regs->iir),0); 616 break; 617 618 case OPCODE_STH: 619 ret = emulate_sth(regs, R2(regs->iir)); 620 break; 621 622 case OPCODE_STW: 623 case OPCODE_STWA: 624 ret = emulate_stw(regs, R2(regs->iir),0); 625 break; 626 627 #ifdef CONFIG_PA20 628 case OPCODE_LDD_I: 629 case OPCODE_LDDA_I: 630 case OPCODE_LDD_S: 631 case OPCODE_LDDA_S: 632 ret = emulate_ldd(regs, R3(regs->iir),0); 633 break; 634 635 case OPCODE_STD: 636 case OPCODE_STDA: 637 ret = emulate_std(regs, R2(regs->iir),0); 638 break; 639 #endif 640 641 case OPCODE_FLDWX: 642 case OPCODE_FLDWS: 643 case OPCODE_FLDWXR: 644 case OPCODE_FLDWSR: 645 flop=1; 646 ret = emulate_ldw(regs,FR3(regs->iir),1); 647 break; 648 649 case OPCODE_FLDDX: 650 case OPCODE_FLDDS: 651 flop=1; 652 ret = emulate_ldd(regs,R3(regs->iir),1); 653 break; 654 655 case OPCODE_FSTWX: 656 case OPCODE_FSTWS: 657 case OPCODE_FSTWXR: 658 case OPCODE_FSTWSR: 659 flop=1; 660 ret = emulate_stw(regs,FR3(regs->iir),1); 661 break; 662 663 case OPCODE_FSTDX: 664 case OPCODE_FSTDS: 665 flop=1; 666 ret = emulate_std(regs,R3(regs->iir),1); 667 break; 668 669 case OPCODE_LDCD_I: 670 case OPCODE_LDCW_I: 671 case OPCODE_LDCD_S: 672 case OPCODE_LDCW_S: 673 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */ 674 break; 675 } 676 #ifdef CONFIG_PA20 677 switch (regs->iir & OPCODE2_MASK) 678 { 679 case OPCODE_FLDD_L: 680 flop=1; 681 ret = emulate_ldd(regs,R2(regs->iir),1); 682 break; 683 case OPCODE_FSTD_L: 684 flop=1; 685 ret = emulate_std(regs, R2(regs->iir),1); 686 break; 687 688 #ifdef CONFIG_PA20 689 case OPCODE_LDD_L: 690 ret = emulate_ldd(regs, R2(regs->iir),0); 691 break; 692 case OPCODE_STD_L: 693 ret = emulate_std(regs, R2(regs->iir),0); 694 break; 695 #endif 696 } 697 #endif 698 switch (regs->iir & OPCODE3_MASK) 699 { 700 case OPCODE_FLDW_L: 701 flop=1; 702 ret = emulate_ldw(regs, R2(regs->iir),0); 703 break; 704 case OPCODE_LDW_M: 705 ret = emulate_ldw(regs, R2(regs->iir),1); 706 break; 707 708 case OPCODE_FSTW_L: 709 flop=1; 710 ret = emulate_stw(regs, R2(regs->iir),1); 711 break; 712 case OPCODE_STW_M: 713 ret = emulate_stw(regs, R2(regs->iir),0); 714 break; 715 } 716 switch (regs->iir & OPCODE4_MASK) 717 { 718 case OPCODE_LDH_L: 719 ret = emulate_ldh(regs, R2(regs->iir)); 720 break; 721 case OPCODE_LDW_L: 722 case OPCODE_LDWM: 723 ret = emulate_ldw(regs, R2(regs->iir),0); 724 break; 725 case OPCODE_STH_L: 726 ret = emulate_sth(regs, R2(regs->iir)); 727 break; 728 case OPCODE_STW_L: 729 case OPCODE_STWM: 730 ret = emulate_stw(regs, R2(regs->iir),0); 731 break; 732 } 733 734 if (modify && R1(regs->iir)) 735 regs->gr[R1(regs->iir)] = newbase; 736 737 738 if (ret == ERR_NOTHANDLED) 739 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir); 740 741 DPRINTF("ret = %d\n", ret); 742 743 if (ret) 744 { 745 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret); 746 die_if_kernel("Unaligned data reference", regs, 28); 747 748 if (ret == ERR_PAGEFAULT) 749 { 750 si.si_signo = SIGSEGV; 751 si.si_errno = 0; 752 si.si_code = SEGV_MAPERR; 753 si.si_addr = (void __user *)regs->ior; 754 force_sig_info(SIGSEGV, &si, current); 755 } 756 else 757 { 758 force_sigbus: 759 /* couldn't handle it ... */ 760 si.si_signo = SIGBUS; 761 si.si_errno = 0; 762 si.si_code = BUS_ADRALN; 763 si.si_addr = (void __user *)regs->ior; 764 force_sig_info(SIGBUS, &si, current); 765 } 766 767 return; 768 } 769 770 /* else we handled it, let life go on. */ 771 regs->gr[0]|=PSW_N; 772 } 773 774 /* 775 * NB: check_unaligned() is only used for PCXS processors right 776 * now, so we only check for PA1.1 encodings at this point. 777 */ 778 779 int 780 check_unaligned(struct pt_regs *regs) 781 { 782 unsigned long align_mask; 783 784 /* Get alignment mask */ 785 786 align_mask = 0UL; 787 switch (regs->iir & OPCODE1_MASK) { 788 789 case OPCODE_LDH_I: 790 case OPCODE_LDH_S: 791 case OPCODE_STH: 792 align_mask = 1UL; 793 break; 794 795 case OPCODE_LDW_I: 796 case OPCODE_LDWA_I: 797 case OPCODE_LDW_S: 798 case OPCODE_LDWA_S: 799 case OPCODE_STW: 800 case OPCODE_STWA: 801 align_mask = 3UL; 802 break; 803 804 default: 805 switch (regs->iir & OPCODE4_MASK) { 806 case OPCODE_LDH_L: 807 case OPCODE_STH_L: 808 align_mask = 1UL; 809 break; 810 case OPCODE_LDW_L: 811 case OPCODE_LDWM: 812 case OPCODE_STW_L: 813 case OPCODE_STWM: 814 align_mask = 3UL; 815 break; 816 } 817 break; 818 } 819 820 return (int)(regs->ior & align_mask); 821 } 822 823